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* [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw
@ 2021-07-05  4:09 psatheesh
  2021-07-05  4:09 ` [dpdk-dev] [PATCH 2/2] net/cnxk: " psatheesh
  2021-07-06 10:47 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: " psatheesh
  0 siblings, 2 replies; 6+ messages in thread
From: psatheesh @ 2021-07-05  4:09 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, Satheesh Paul

From: Satheesh Paul <psatheesh@marvell.com>

Add roc API for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h      | 24 ++++++--
 drivers/common/cnxk/roc_nix_ops.c   | 14 +++++
 drivers/common/cnxk/roc_npc.h       | 11 ++++
 drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_npc_priv.h  |  9 +--
 drivers/common/cnxk/roc_npc_utils.c |  6 +-
 drivers/common/cnxk/roc_utils.c     |  2 +-
 7 files changed, 136 insertions(+), 16 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 9c529d754..b254f005a 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -278,14 +278,28 @@ struct ready_msg_rsp {
 	uint16_t __io rclk_freq; /* RCLK frequency */
 };
 
+enum npc_pkind_type {
+	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+	NPC_RX_CHLEN24B_PKIND,
+	NPC_RX_CPT_HDR_PKIND,
+	NPC_RX_CHLEN90B_PKIND,
+	NPC_TX_HIGIG_PKIND,
+	NPC_RX_HIGIG_PKIND,
+	NPC_RX_EXDSA_PKIND,
+	NPC_RX_EDSA_PKIND,
+	NPC_TX_DEF_PKIND,
+};
+
 /* Struct to set pkind */
 struct npc_set_pkind {
 	struct mbox_msghdr hdr;
-#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
-#define ROC_PRIV_FLAGS_EDSA    BIT_ULL(1)
-#define ROC_PRIV_FLAGS_HIGIG   BIT_ULL(2)
-#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
-#define ROC_PRIV_FLAGS_CUSTOM  BIT_ULL(63)
+#define ROC_PRIV_FLAGS_DEFAULT	  BIT_ULL(0)
+#define ROC_PRIV_FLAGS_EDSA	  BIT_ULL(1)
+#define ROC_PRIV_FLAGS_HIGIG	  BIT_ULL(2)
+#define ROC_PRIV_FLAGS_LEN_90B	  BIT_ULL(3)
+#define ROC_PRIV_FLAGS_EXDSA	  BIT_ULL(4)
+#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
+#define ROC_PRIV_FLAGS_CUSTOM	  BIT_ULL(63)
 	uint64_t __io mode;
 #define PKIND_TX BIT_ULL(0)
 #define PKIND_RX BIT_ULL(1)
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index eeb85a54f..0e28302e7 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	    switch_header_type != ROC_PRIV_FLAGS_EDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 	    switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&
+	    switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
+	    switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
 		plt_err("switch header type is not supported");
 		return NIX_ERR_PARAM;
@@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	if (req == NULL)
 		return rc;
 	req->mode = switch_header_type;
+
+	if (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_CHLEN90B_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_EXDSA_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
+	}
+
 	req->dir = PKIND_RX;
 	rc = mbox_process_msg(mbox, (void *)&rsp);
 	if (rc)
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 2c0a536c9..bab25fd72 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -36,6 +36,7 @@ enum roc_npc_item_type {
 	ROC_NPC_ITEM_TYPE_CPT_HDR,
 	ROC_NPC_ITEM_TYPE_L3_CUSTOM,
 	ROC_NPC_ITEM_TYPE_QINQ,
+	ROC_NPC_ITEM_TYPE_RAW,
 	ROC_NPC_ITEM_TYPE_END,
 };
 
@@ -47,6 +48,16 @@ struct roc_npc_item_info {
 	const void *last; /* For range */
 };
 
+struct roc_npc_flow_item_raw {
+	uint32_t relative : 1; /**< Look for pattern after the previous item. */
+	uint32_t search : 1;   /**< Search pattern from offset. */
+	uint32_t reserved : 30; /**< Reserved, must be set to zero. */
+	int32_t offset;		/**< Absolute or relative offset for pattern. */
+	uint16_t limit;		/**< Search area limit for start of pattern. */
+	uint16_t length;	/**< Pattern length. */
+	const uint8_t *pattern; /**< Byte string to look for. */
+};
+
 #define ROC_NPC_MAX_ACTION_COUNT 12
 
 enum roc_npc_action_type {
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index d07f91db3..8125035dd 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst)
 	return npc_update_parse_state(pst, &info, lid, lt, 0);
 }
 
+static int
+npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,
+			  const struct roc_npc_flow_item_raw *raw_mask,
+			  struct npc_parse_item_info *info, uint8_t *spec_buf,
+			  uint8_t *mask_buf)
+{
+	uint32_t custom_hdr_size = 0;
+
+	memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	custom_hdr_size = raw_spec->offset + raw_spec->length;
+
+	memcpy(spec_buf + raw_spec->offset, raw_spec->pattern,
+	       raw_spec->length);
+
+	if (raw_mask->pattern) {
+		memcpy(mask_buf + raw_spec->offset, raw_mask->pattern,
+		       raw_spec->length);
+	} else {
+		memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);
+	}
+
+	info->len = custom_hdr_size;
+	info->spec = spec_buf;
+	info->mask = mask_buf;
+
+	return 0;
+}
+
 int
 npc_parse_lb(struct npc_parse_state *pst)
 {
 	const struct roc_npc_item_info *pattern = pst->pattern;
 	const struct roc_npc_item_info *last_pattern;
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	char hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt, lflags;
+	int lid, lt, lflags, len = 0;
 	int nr_vlans = 0;
 	int rc;
 
@@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst)
 		info.len = pst->pattern->size;
 		lt = NPC_LT_LB_STAG_QINQ;
 		lflags = NPC_F_STAG_CTAG;
+	} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {
+		raw_spec = pst->pattern->spec;
+		if (raw_spec->relative)
+			return 0;
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		if (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+			lt = NPC_LT_LB_VLAN_EXDSA;
+		} else if (pst->npc->switch_header_type ==
+			   ROC_PRIV_FLAGS_EXDSA) {
+			lt = NPC_LT_LB_EXDSA;
+		} else {
+			return -EINVAL;
+		}
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		info.hw_hdr_len = 0;
 	} else {
 		return 0;
 	}
 
 	info.hw_mask = &hw_mask;
-	info.spec = NULL;
-	info.mask = NULL;
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 
 	rc = npc_parse_item_basic(pst->pattern, &info);
@@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst)
 int
 npc_parse_lc(struct npc_parse_state *pst)
 {
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt;
+	int lid, lt, len = 0;
 	int rc;
 
 	if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS)
@@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst)
 		lt = NPC_LT_LC_CUSTOM0;
 		info.len = pst->pattern->size;
 		break;
+	case ROC_NPC_ITEM_TYPE_RAW:
+		raw_spec = pst->pattern->spec;
+		if (!raw_spec->relative)
+			return 0;
+
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		lid = NPC_LID_LC;
+		lt = NPC_LT_LC_NGIO;
+		info.hw_mask = &hw_mask;
+		npc_get_hw_supp_mask(pst, &info, lid, lt);
+		break;
 	default:
 		/* No match at this layer */
 		return 0;
@@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst)
 
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 	rc = npc_parse_item_basic(pst->pattern, &info);
+
 	if (rc != 0)
 		return rc;
 
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index 484c3aeb1..5b884e3fd 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -5,10 +5,11 @@
 #ifndef _ROC_NPC_PRIV_H_
 #define _ROC_NPC_PRIV_H_
 
-#define NPC_IH_LENGTH	  8
-#define NPC_TPID_LENGTH	  2
-#define NPC_HIGIG2_LENGTH 16
-#define NPC_COUNTER_NONE  (-1)
+#define NPC_IH_LENGTH	     8
+#define NPC_TPID_LENGTH	     2
+#define NPC_HIGIG2_LENGTH    16
+#define NPC_MAX_RAW_ITEM_LEN 16
+#define NPC_COUNTER_NONE     (-1)
 
 #define NPC_RSS_GRPS 8
 
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 5c97588e6..5fcb56c35 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 	}
 
 	/* We have valid spec */
-	info->spec = item->spec;
+	if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+		info->spec = item->spec;
 
 	/* If mask is not set, use default mask, err if default mask is
 	 * also NULL.
@@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 			return NPC_ERR_PARAM;
 		info->mask = info->def_mask;
 	} else {
-		info->mask = item->mask;
+		if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+			info->mask = item->mask;
 	}
 
 	/* mask specified must be subset of hw supported mask
diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c
index 542252fe4..9cb8708a7 100644
--- a/drivers/common/cnxk/roc_utils.c
+++ b/drivers/common/cnxk/roc_utils.c
@@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode)
 		err_msg = "NPC invalid spec";
 		break;
 	case NPC_ERR_INVALID_MASK:
-		err_msg = "NPC  invalid mask";
+		err_msg = "NPC invalid mask";
 		break;
 	case NPC_ERR_INVALID_KEX:
 		err_msg = "NPC invalid key";
-- 
2.25.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH 2/2] net/cnxk: add support for rte flow item raw
  2021-07-05  4:09 [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw psatheesh
@ 2021-07-05  4:09 ` psatheesh
  2021-07-06 10:47 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: " psatheesh
  1 sibling, 0 replies; 6+ messages in thread
From: psatheesh @ 2021-07-05  4:09 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, Satheesh Paul

From: Satheesh Paul <psatheesh@marvell.com>

Add support for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 169 +++++++++++++++++++++++--
 drivers/net/cnxk/cnxk_ethdev_devargs.c |   7 +
 drivers/net/cnxk/cnxk_rte_flow.c       |  12 +-
 3 files changed, 172 insertions(+), 16 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index cb2a51e1d..a7b59a48e 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -104,7 +104,7 @@ Runtime Config Options
 
 - ``Rx&Tx scalar mode enable`` (default ``0``)
 
-   PMD supports both scalar and vector mode, it may be selected at runtime
+   Ethdev supports both scalar and vector mode, it may be selected at runtime
    using ``scalar_enable`` ``devargs`` parameter.
 
 - ``RSS reta size`` (default ``64``)
@@ -151,7 +151,7 @@ Runtime Config Options
 
       -a 0002:02:00.0,max_sqb_count=64
 
-   With the above configuration, each send queue's descriptor buffer count is
+   With the above configuration, each send queue's decscriptor buffer count is
    limited to a maximum of 64 buffers.
 
 - ``Switch header enable`` (default ``none``)
@@ -165,7 +165,7 @@ Runtime Config Options
 
    With the above configuration, higig2 will be enabled on that port and the
    traffic on this port should be higig2 traffic only. Supported switch header
-   types are "higig2", "dsa", "chlen90b" and "chlen24b".
+   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
 
 - ``RSS tag as XOR`` (default ``0``)
 
@@ -186,6 +186,7 @@ Runtime Config Options
       -a 0002:02:00.0,tag_as_xor=1
 
 
+
 .. note::
 
    Above devarg parameters are configurable per device, user needs to pass the
@@ -196,7 +197,7 @@ Limitations
 -----------
 
 ``mempool_cnxk`` external mempool handler dependency
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The OCTEON CN9K/CN10K SoC family NIC has inbuilt HW assisted external mempool manager.
 ``net_cnxk`` pmd only works with ``mempool_cnxk`` mempool handler
@@ -209,12 +210,6 @@ CRC stripping
 The OCTEON CN9K/CN10K SoC family NICs strip the CRC for every packet being received by
 the host interface irrespective of the offload configuration.
 
-RTE flow GRE support
-~~~~~~~~~~~~~~~~~~~~
-
-- ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing
-  bits in the GRE header are equal to 0.
-
 Debugging Options
 -----------------
 
@@ -229,3 +224,157 @@ Debugging Options
    +---+------------+-------------------------------------------------------+
    | 2 | NPC        | --log-level='pmd\.net.cnxk\.flow,8'                   |
    +---+------------+-------------------------------------------------------+
+
+RTE Flow Support
+----------------
+
+The OCTEON CN9K/CN10K SoC family NIC has support for the following patterns and
+actions.
+
+Patterns:
+
+.. _table_cnxk_supported_flow_item_types:
+
+.. table:: Item types
+
+   +----+--------------------------------+
+   | #  | Pattern Type                   |
+   +====+================================+
+   | 1  | RTE_FLOW_ITEM_TYPE_ETH         |
+   +----+--------------------------------+
+   | 2  | RTE_FLOW_ITEM_TYPE_VLAN        |
+   +----+--------------------------------+
+   | 3  | RTE_FLOW_ITEM_TYPE_E_TAG       |
+   +----+--------------------------------+
+   | 4  | RTE_FLOW_ITEM_TYPE_IPV4        |
+   +----+--------------------------------+
+   | 5  | RTE_FLOW_ITEM_TYPE_IPV6        |
+   +----+--------------------------------+
+   | 6  | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|
+   +----+--------------------------------+
+   | 7  | RTE_FLOW_ITEM_TYPE_MPLS        |
+   +----+--------------------------------+
+   | 8  | RTE_FLOW_ITEM_TYPE_ICMP        |
+   +----+--------------------------------+
+   | 9  | RTE_FLOW_ITEM_TYPE_UDP         |
+   +----+--------------------------------+
+   | 10 | RTE_FLOW_ITEM_TYPE_TCP         |
+   +----+--------------------------------+
+   | 11 | RTE_FLOW_ITEM_TYPE_SCTP        |
+   +----+--------------------------------+
+   | 12 | RTE_FLOW_ITEM_TYPE_ESP         |
+   +----+--------------------------------+
+   | 13 | RTE_FLOW_ITEM_TYPE_GRE         |
+   +----+--------------------------------+
+   | 14 | RTE_FLOW_ITEM_TYPE_NVGRE       |
+   +----+--------------------------------+
+   | 15 | RTE_FLOW_ITEM_TYPE_VXLAN       |
+   +----+--------------------------------+
+   | 16 | RTE_FLOW_ITEM_TYPE_GTPC        |
+   +----+--------------------------------+
+   | 17 | RTE_FLOW_ITEM_TYPE_GTPU        |
+   +----+--------------------------------+
+   | 18 | RTE_FLOW_ITEM_TYPE_GENEVE      |
+   +----+--------------------------------+
+   | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE   |
+   +----+--------------------------------+
+   | 20 | RTE_FLOW_ITEM_TYPE_IPV6_EXT    |
+   +----+--------------------------------+
+   | 21 | RTE_FLOW_ITEM_TYPE_VOID        |
+   +----+--------------------------------+
+   | 22 | RTE_FLOW_ITEM_TYPE_ANY         |
+   +----+--------------------------------+
+   | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY     |
+   +----+--------------------------------+
+   | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2      |
+   +----+--------------------------------+
+   | 25 | RTE_FLOW_ITEM_TYPE_RAW         |
+   +----+--------------------------------+
+
+.. note::
+
+   ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing
+   bits in the GRE header are equal to 0.
+
+Actions:
+
+.. _table_cnxk_supported_ingress_action_types:
+
+.. table:: Ingress action types
+
+   +----+-----------------------------------------+
+   | #  | Action Type                             |
+   +====+=========================================+
+   | 1  | RTE_FLOW_ACTION_TYPE_VOID               |
+   +----+-----------------------------------------+
+   | 2  | RTE_FLOW_ACTION_TYPE_MARK               |
+   +----+-----------------------------------------+
+   | 3  | RTE_FLOW_ACTION_TYPE_FLAG               |
+   +----+-----------------------------------------+
+   | 4  | RTE_FLOW_ACTION_TYPE_COUNT              |
+   +----+-----------------------------------------+
+   | 5  | RTE_FLOW_ACTION_TYPE_DROP               |
+   +----+-----------------------------------------+
+   | 6  | RTE_FLOW_ACTION_TYPE_QUEUE              |
+   +----+-----------------------------------------+
+   | 7  | RTE_FLOW_ACTION_TYPE_RSS                |
+   +----+-----------------------------------------+
+   | 8  | RTE_FLOW_ACTION_TYPE_PF                 |
+   +----+-----------------------------------------+
+   | 9  | RTE_FLOW_ACTION_TYPE_VF                 |
+   +----+-----------------------------------------+
+   | 10 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN        |
+   +----+-----------------------------------------+
+
+.. _table_cnxk_supported_egress_action_types:
+
+.. table:: Egress action types
+
+   +----+-----------------------------------------+
+   | #  | Action Type                             |
+   +====+=========================================+
+   | 1  | RTE_FLOW_ACTION_TYPE_COUNT              |
+   +----+-----------------------------------------+
+   | 2  | RTE_FLOW_ACTION_TYPE_DROP               |
+   +----+-----------------------------------------+
+   | 3  | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN       |
+   +----+-----------------------------------------+
+   | 4  | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID    |
+   +----+-----------------------------------------+
+   | 5  | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP    |
+   +----+-----------------------------------------+
+
+Custom protocols supported in RTE Flow
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.
+
+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.
+* ``NGIO`` can be parsed at L3 level.
+
+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the
+respective switch header.
+
+For example::
+
+   -a 0002:02:00.0,switch_header="vlan_exdsa"
+
+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the
+pattern.
+
+- ``relative`` Selects the layer at which parsing is done.
+
+  - 0 for ``exdsa`` and ``vlan_exdsa``.
+
+  - 1 for  ``NGIO``.
+
+- ``offset`` The offset in the header where the pattern should be matched.
+- ``length`` Length of the pattern.
+- ``pattern`` Pattern as a byte string.
+
+Example usage in testpmd::
+
+   ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \
+                  --rx-offloads=0x00080000 --rxq 8 --txq 8
+   testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \
+          spec ab pattern mask ab offset is 4 / end actions queue index 1 / end
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index c76b6281c..36b437a18 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
 
 	if (strcmp(value, "chlen90b") == 0)
 		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;
+
+	if (strcmp(value, "exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;
+
+	if (strcmp(value, "vlan_exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;
+
 	return 0;
 }
 
diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c
index 213125b56..32c1b5dee 100644
--- a/drivers/net/cnxk/cnxk_rte_flow.c
+++ b/drivers/net/cnxk/cnxk_rte_flow.c
@@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6,
 				     sizeof(struct rte_flow_item_ipv6)},
 	[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
-		ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
-		sizeof(struct rte_flow_item_arp_eth_ipv4)},
+			ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
+			sizeof(struct rte_flow_item_arp_eth_ipv4)},
 	[RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS,
 				     sizeof(struct rte_flow_item_mpls)},
 	[RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP,
@@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0},
 	[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY,
 					sizeof(uint32_t)},
-	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {
-		ROC_NPC_ITEM_TYPE_HIGIG2,
-		sizeof(struct rte_flow_item_higig2_hdr)}
-};
+	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2,
+				       sizeof(struct rte_flow_item_higig2_hdr)},
+	[RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW,
+				    sizeof(struct rte_flow_item_raw)}};
 
 static int
 npc_rss_action_validate(struct rte_eth_dev *eth_dev,
-- 
2.25.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH v2 1/2] common/cnxk: add support for rte flow item raw
  2021-07-05  4:09 [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw psatheesh
  2021-07-05  4:09 ` [dpdk-dev] [PATCH 2/2] net/cnxk: " psatheesh
@ 2021-07-06 10:47 ` psatheesh
  2021-07-06 10:47   ` [dpdk-dev] [PATCH v2 2/2] net/cnxk: " psatheesh
  1 sibling, 1 reply; 6+ messages in thread
From: psatheesh @ 2021-07-06 10:47 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, Satheesh Paul

From: Satheesh Paul <psatheesh@marvell.com>

Add roc API for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h      | 24 ++++++--
 drivers/common/cnxk/roc_nix_ops.c   | 14 +++++
 drivers/common/cnxk/roc_npc.h       | 11 ++++
 drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_npc_priv.h  |  9 +--
 drivers/common/cnxk/roc_npc_utils.c |  6 +-
 drivers/common/cnxk/roc_utils.c     |  2 +-
 7 files changed, 136 insertions(+), 16 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 9c529d754..b254f005a 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -278,14 +278,28 @@ struct ready_msg_rsp {
 	uint16_t __io rclk_freq; /* RCLK frequency */
 };
 
+enum npc_pkind_type {
+	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+	NPC_RX_CHLEN24B_PKIND,
+	NPC_RX_CPT_HDR_PKIND,
+	NPC_RX_CHLEN90B_PKIND,
+	NPC_TX_HIGIG_PKIND,
+	NPC_RX_HIGIG_PKIND,
+	NPC_RX_EXDSA_PKIND,
+	NPC_RX_EDSA_PKIND,
+	NPC_TX_DEF_PKIND,
+};
+
 /* Struct to set pkind */
 struct npc_set_pkind {
 	struct mbox_msghdr hdr;
-#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
-#define ROC_PRIV_FLAGS_EDSA    BIT_ULL(1)
-#define ROC_PRIV_FLAGS_HIGIG   BIT_ULL(2)
-#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
-#define ROC_PRIV_FLAGS_CUSTOM  BIT_ULL(63)
+#define ROC_PRIV_FLAGS_DEFAULT	  BIT_ULL(0)
+#define ROC_PRIV_FLAGS_EDSA	  BIT_ULL(1)
+#define ROC_PRIV_FLAGS_HIGIG	  BIT_ULL(2)
+#define ROC_PRIV_FLAGS_LEN_90B	  BIT_ULL(3)
+#define ROC_PRIV_FLAGS_EXDSA	  BIT_ULL(4)
+#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
+#define ROC_PRIV_FLAGS_CUSTOM	  BIT_ULL(63)
 	uint64_t __io mode;
 #define PKIND_TX BIT_ULL(0)
 #define PKIND_RX BIT_ULL(1)
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index eeb85a54f..0e28302e7 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	    switch_header_type != ROC_PRIV_FLAGS_EDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 	    switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&
+	    switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
+	    switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
 		plt_err("switch header type is not supported");
 		return NIX_ERR_PARAM;
@@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	if (req == NULL)
 		return rc;
 	req->mode = switch_header_type;
+
+	if (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_CHLEN90B_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_EXDSA_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
+	}
+
 	req->dir = PKIND_RX;
 	rc = mbox_process_msg(mbox, (void *)&rsp);
 	if (rc)
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 2c0a536c9..bab25fd72 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -36,6 +36,7 @@ enum roc_npc_item_type {
 	ROC_NPC_ITEM_TYPE_CPT_HDR,
 	ROC_NPC_ITEM_TYPE_L3_CUSTOM,
 	ROC_NPC_ITEM_TYPE_QINQ,
+	ROC_NPC_ITEM_TYPE_RAW,
 	ROC_NPC_ITEM_TYPE_END,
 };
 
@@ -47,6 +48,16 @@ struct roc_npc_item_info {
 	const void *last; /* For range */
 };
 
+struct roc_npc_flow_item_raw {
+	uint32_t relative : 1; /**< Look for pattern after the previous item. */
+	uint32_t search : 1;   /**< Search pattern from offset. */
+	uint32_t reserved : 30; /**< Reserved, must be set to zero. */
+	int32_t offset;		/**< Absolute or relative offset for pattern. */
+	uint16_t limit;		/**< Search area limit for start of pattern. */
+	uint16_t length;	/**< Pattern length. */
+	const uint8_t *pattern; /**< Byte string to look for. */
+};
+
 #define ROC_NPC_MAX_ACTION_COUNT 12
 
 enum roc_npc_action_type {
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index d07f91db3..8125035dd 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst)
 	return npc_update_parse_state(pst, &info, lid, lt, 0);
 }
 
+static int
+npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,
+			  const struct roc_npc_flow_item_raw *raw_mask,
+			  struct npc_parse_item_info *info, uint8_t *spec_buf,
+			  uint8_t *mask_buf)
+{
+	uint32_t custom_hdr_size = 0;
+
+	memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	custom_hdr_size = raw_spec->offset + raw_spec->length;
+
+	memcpy(spec_buf + raw_spec->offset, raw_spec->pattern,
+	       raw_spec->length);
+
+	if (raw_mask->pattern) {
+		memcpy(mask_buf + raw_spec->offset, raw_mask->pattern,
+		       raw_spec->length);
+	} else {
+		memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);
+	}
+
+	info->len = custom_hdr_size;
+	info->spec = spec_buf;
+	info->mask = mask_buf;
+
+	return 0;
+}
+
 int
 npc_parse_lb(struct npc_parse_state *pst)
 {
 	const struct roc_npc_item_info *pattern = pst->pattern;
 	const struct roc_npc_item_info *last_pattern;
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	char hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt, lflags;
+	int lid, lt, lflags, len = 0;
 	int nr_vlans = 0;
 	int rc;
 
@@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst)
 		info.len = pst->pattern->size;
 		lt = NPC_LT_LB_STAG_QINQ;
 		lflags = NPC_F_STAG_CTAG;
+	} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {
+		raw_spec = pst->pattern->spec;
+		if (raw_spec->relative)
+			return 0;
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		if (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+			lt = NPC_LT_LB_VLAN_EXDSA;
+		} else if (pst->npc->switch_header_type ==
+			   ROC_PRIV_FLAGS_EXDSA) {
+			lt = NPC_LT_LB_EXDSA;
+		} else {
+			return -EINVAL;
+		}
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		info.hw_hdr_len = 0;
 	} else {
 		return 0;
 	}
 
 	info.hw_mask = &hw_mask;
-	info.spec = NULL;
-	info.mask = NULL;
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 
 	rc = npc_parse_item_basic(pst->pattern, &info);
@@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst)
 int
 npc_parse_lc(struct npc_parse_state *pst)
 {
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt;
+	int lid, lt, len = 0;
 	int rc;
 
 	if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS)
@@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst)
 		lt = NPC_LT_LC_CUSTOM0;
 		info.len = pst->pattern->size;
 		break;
+	case ROC_NPC_ITEM_TYPE_RAW:
+		raw_spec = pst->pattern->spec;
+		if (!raw_spec->relative)
+			return 0;
+
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		lid = NPC_LID_LC;
+		lt = NPC_LT_LC_NGIO;
+		info.hw_mask = &hw_mask;
+		npc_get_hw_supp_mask(pst, &info, lid, lt);
+		break;
 	default:
 		/* No match at this layer */
 		return 0;
@@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst)
 
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 	rc = npc_parse_item_basic(pst->pattern, &info);
+
 	if (rc != 0)
 		return rc;
 
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index 484c3aeb1..5b884e3fd 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -5,10 +5,11 @@
 #ifndef _ROC_NPC_PRIV_H_
 #define _ROC_NPC_PRIV_H_
 
-#define NPC_IH_LENGTH	  8
-#define NPC_TPID_LENGTH	  2
-#define NPC_HIGIG2_LENGTH 16
-#define NPC_COUNTER_NONE  (-1)
+#define NPC_IH_LENGTH	     8
+#define NPC_TPID_LENGTH	     2
+#define NPC_HIGIG2_LENGTH    16
+#define NPC_MAX_RAW_ITEM_LEN 16
+#define NPC_COUNTER_NONE     (-1)
 
 #define NPC_RSS_GRPS 8
 
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 5c97588e6..5fcb56c35 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 	}
 
 	/* We have valid spec */
-	info->spec = item->spec;
+	if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+		info->spec = item->spec;
 
 	/* If mask is not set, use default mask, err if default mask is
 	 * also NULL.
@@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 			return NPC_ERR_PARAM;
 		info->mask = info->def_mask;
 	} else {
-		info->mask = item->mask;
+		if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+			info->mask = item->mask;
 	}
 
 	/* mask specified must be subset of hw supported mask
diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c
index 542252fe4..9cb8708a7 100644
--- a/drivers/common/cnxk/roc_utils.c
+++ b/drivers/common/cnxk/roc_utils.c
@@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode)
 		err_msg = "NPC invalid spec";
 		break;
 	case NPC_ERR_INVALID_MASK:
-		err_msg = "NPC  invalid mask";
+		err_msg = "NPC invalid mask";
 		break;
 	case NPC_ERR_INVALID_KEX:
 		err_msg = "NPC invalid key";
-- 
2.25.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH v2 2/2] net/cnxk: add support for rte flow item raw
  2021-07-06 10:47 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: " psatheesh
@ 2021-07-06 10:47   ` psatheesh
  0 siblings, 0 replies; 6+ messages in thread
From: psatheesh @ 2021-07-06 10:47 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, Satheesh Paul

From: Satheesh Paul <psatheesh@marvell.com>

Add support for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 37 +++++++++++++++++++++++++-
 drivers/net/cnxk/cnxk_ethdev_devargs.c |  7 +++++
 drivers/net/cnxk/cnxk_rte_flow.c       | 12 ++++-----
 3 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index cb2a51e1d..90d27dbaa 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -165,7 +165,7 @@ Runtime Config Options
 
    With the above configuration, higig2 will be enabled on that port and the
    traffic on this port should be higig2 traffic only. Supported switch header
-   types are "higig2", "dsa", "chlen90b" and "chlen24b".
+   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
 
 - ``RSS tag as XOR`` (default ``0``)
 
@@ -215,6 +215,41 @@ RTE flow GRE support
 - ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing
   bits in the GRE header are equal to 0.
 
+Custom protocols supported in RTE Flow
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.
+
+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.
+* ``NGIO`` can be parsed at L3 level.
+
+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the
+respective switch header.
+
+For example::
+
+   -a 0002:02:00.0,switch_header="vlan_exdsa"
+
+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the
+pattern.
+
+- ``relative`` Selects the layer at which parsing is done.
+
+  - 0 for ``exdsa`` and ``vlan_exdsa``.
+
+  - 1 for  ``NGIO``.
+
+- ``offset`` The offset in the header where the pattern should be matched.
+- ``length`` Length of the pattern.
+- ``pattern`` Pattern as a byte string.
+
+Example usage in testpmd::
+
+   ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \
+                  --rx-offloads=0x00080000 --rxq 8 --txq 8
+   testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \
+          spec ab pattern mask ab offset is 4 / end actions queue index 1 / end
+
 Debugging Options
 -----------------
 
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index c76b6281c..36b437a18 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
 
 	if (strcmp(value, "chlen90b") == 0)
 		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;
+
+	if (strcmp(value, "exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;
+
+	if (strcmp(value, "vlan_exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;
+
 	return 0;
 }
 
diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c
index 213125b56..32c1b5dee 100644
--- a/drivers/net/cnxk/cnxk_rte_flow.c
+++ b/drivers/net/cnxk/cnxk_rte_flow.c
@@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6,
 				     sizeof(struct rte_flow_item_ipv6)},
 	[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
-		ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
-		sizeof(struct rte_flow_item_arp_eth_ipv4)},
+			ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
+			sizeof(struct rte_flow_item_arp_eth_ipv4)},
 	[RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS,
 				     sizeof(struct rte_flow_item_mpls)},
 	[RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP,
@@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0},
 	[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY,
 					sizeof(uint32_t)},
-	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {
-		ROC_NPC_ITEM_TYPE_HIGIG2,
-		sizeof(struct rte_flow_item_higig2_hdr)}
-};
+	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2,
+				       sizeof(struct rte_flow_item_higig2_hdr)},
+	[RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW,
+				    sizeof(struct rte_flow_item_raw)}};
 
 static int
 npc_rss_action_validate(struct rte_eth_dev *eth_dev,
-- 
2.25.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw
  2021-07-12  6:49 [dpdk-dev] [PATCH 1/2] common/cnxk: " psatheesh
@ 2021-07-13 11:18 ` Jerin Jacob
  0 siblings, 0 replies; 6+ messages in thread
From: Jerin Jacob @ 2021-07-13 11:18 UTC (permalink / raw)
  To: Satheesh Paul
  Cc: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, dpdk-dev

On Mon, Jul 12, 2021 at 12:19 PM <psatheesh@marvell.com> wrote:
>
> From: Satheesh Paul <psatheesh@marvell.com>
>
> Add roc API for rte_flow_item_raw to parse custom L2 and L3 protocols.
>
> Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
> Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>


Applied to dpdk-next-net-mrvl/for-next-net. Thanks


> ---
>  drivers/common/cnxk/roc_mbox.h      | 24 ++++++--
>  drivers/common/cnxk/roc_nix_ops.c   | 14 +++++
>  drivers/common/cnxk/roc_npc.h       | 11 ++++
>  drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++--
>  drivers/common/cnxk/roc_npc_priv.h  |  9 +--
>  drivers/common/cnxk/roc_npc_utils.c |  6 +-
>  drivers/common/cnxk/roc_utils.c     |  2 +-
>  7 files changed, 136 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
> index 9c529d754..b254f005a 100644
> --- a/drivers/common/cnxk/roc_mbox.h
> +++ b/drivers/common/cnxk/roc_mbox.h
> @@ -278,14 +278,28 @@ struct ready_msg_rsp {
>         uint16_t __io rclk_freq; /* RCLK frequency */
>  };
>
> +enum npc_pkind_type {
> +       NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
> +       NPC_RX_CHLEN24B_PKIND,
> +       NPC_RX_CPT_HDR_PKIND,
> +       NPC_RX_CHLEN90B_PKIND,
> +       NPC_TX_HIGIG_PKIND,
> +       NPC_RX_HIGIG_PKIND,
> +       NPC_RX_EXDSA_PKIND,
> +       NPC_RX_EDSA_PKIND,
> +       NPC_TX_DEF_PKIND,
> +};
> +
>  /* Struct to set pkind */
>  struct npc_set_pkind {
>         struct mbox_msghdr hdr;
> -#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
> -#define ROC_PRIV_FLAGS_EDSA    BIT_ULL(1)
> -#define ROC_PRIV_FLAGS_HIGIG   BIT_ULL(2)
> -#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
> -#define ROC_PRIV_FLAGS_CUSTOM  BIT_ULL(63)
> +#define ROC_PRIV_FLAGS_DEFAULT   BIT_ULL(0)
> +#define ROC_PRIV_FLAGS_EDSA      BIT_ULL(1)
> +#define ROC_PRIV_FLAGS_HIGIG     BIT_ULL(2)
> +#define ROC_PRIV_FLAGS_LEN_90B   BIT_ULL(3)
> +#define ROC_PRIV_FLAGS_EXDSA     BIT_ULL(4)
> +#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
> +#define ROC_PRIV_FLAGS_CUSTOM    BIT_ULL(63)
>         uint64_t __io mode;
>  #define PKIND_TX BIT_ULL(0)
>  #define PKIND_RX BIT_ULL(1)
> diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
> index eeb85a54f..0e28302e7 100644
> --- a/drivers/common/cnxk/roc_nix_ops.c
> +++ b/drivers/common/cnxk/roc_nix_ops.c
> @@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
>             switch_header_type != ROC_PRIV_FLAGS_EDSA &&
>             switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
>             switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&
> +           switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
> +           switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
>             switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
>                 plt_err("switch header type is not supported");
>                 return NIX_ERR_PARAM;
> @@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
>         if (req == NULL)
>                 return rc;
>         req->mode = switch_header_type;
> +
> +       if (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
> +               req->mode = ROC_PRIV_FLAGS_CUSTOM;
> +               req->pkind = NPC_RX_CHLEN90B_PKIND;
> +       } else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) {
> +               req->mode = ROC_PRIV_FLAGS_CUSTOM;
> +               req->pkind = NPC_RX_EXDSA_PKIND;
> +       } else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
> +               req->mode = ROC_PRIV_FLAGS_CUSTOM;
> +               req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
> +       }
> +
>         req->dir = PKIND_RX;
>         rc = mbox_process_msg(mbox, (void *)&rsp);
>         if (rc)
> diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
> index 2c0a536c9..bab25fd72 100644
> --- a/drivers/common/cnxk/roc_npc.h
> +++ b/drivers/common/cnxk/roc_npc.h
> @@ -36,6 +36,7 @@ enum roc_npc_item_type {
>         ROC_NPC_ITEM_TYPE_CPT_HDR,
>         ROC_NPC_ITEM_TYPE_L3_CUSTOM,
>         ROC_NPC_ITEM_TYPE_QINQ,
> +       ROC_NPC_ITEM_TYPE_RAW,
>         ROC_NPC_ITEM_TYPE_END,
>  };
>
> @@ -47,6 +48,16 @@ struct roc_npc_item_info {
>         const void *last; /* For range */
>  };
>
> +struct roc_npc_flow_item_raw {
> +       uint32_t relative : 1; /**< Look for pattern after the previous item. */
> +       uint32_t search : 1;   /**< Search pattern from offset. */
> +       uint32_t reserved : 30; /**< Reserved, must be set to zero. */
> +       int32_t offset;         /**< Absolute or relative offset for pattern. */
> +       uint16_t limit;         /**< Search area limit for start of pattern. */
> +       uint16_t length;        /**< Pattern length. */
> +       const uint8_t *pattern; /**< Byte string to look for. */
> +};
> +
>  #define ROC_NPC_MAX_ACTION_COUNT 12
>
>  enum roc_npc_action_type {
> diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
> index d07f91db3..8125035dd 100644
> --- a/drivers/common/cnxk/roc_npc_parse.c
> +++ b/drivers/common/cnxk/roc_npc_parse.c
> @@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst)
>         return npc_update_parse_state(pst, &info, lid, lt, 0);
>  }
>
> +static int
> +npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,
> +                         const struct roc_npc_flow_item_raw *raw_mask,
> +                         struct npc_parse_item_info *info, uint8_t *spec_buf,
> +                         uint8_t *mask_buf)
> +{
> +       uint32_t custom_hdr_size = 0;
> +
> +       memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);
> +       memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);
> +       custom_hdr_size = raw_spec->offset + raw_spec->length;
> +
> +       memcpy(spec_buf + raw_spec->offset, raw_spec->pattern,
> +              raw_spec->length);
> +
> +       if (raw_mask->pattern) {
> +               memcpy(mask_buf + raw_spec->offset, raw_mask->pattern,
> +                      raw_spec->length);
> +       } else {
> +               memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);
> +       }
> +
> +       info->len = custom_hdr_size;
> +       info->spec = spec_buf;
> +       info->mask = mask_buf;
> +
> +       return 0;
> +}
> +
>  int
>  npc_parse_lb(struct npc_parse_state *pst)
>  {
>         const struct roc_npc_item_info *pattern = pst->pattern;
>         const struct roc_npc_item_info *last_pattern;
> +       const struct roc_npc_flow_item_raw *raw_spec;
> +       uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
> +       uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
>         char hw_mask[NPC_MAX_EXTRACT_HW_LEN];
>         struct npc_parse_item_info info;
> -       int lid, lt, lflags;
> +       int lid, lt, lflags, len = 0;
>         int nr_vlans = 0;
>         int rc;
>
> @@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst)
>                 info.len = pst->pattern->size;
>                 lt = NPC_LT_LB_STAG_QINQ;
>                 lflags = NPC_F_STAG_CTAG;
> +       } else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {
> +               raw_spec = pst->pattern->spec;
> +               if (raw_spec->relative)
> +                       return 0;
> +               len = raw_spec->length + raw_spec->offset;
> +               if (len > NPC_MAX_RAW_ITEM_LEN)
> +                       return -EINVAL;
> +
> +               if (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
> +                       lt = NPC_LT_LB_VLAN_EXDSA;
> +               } else if (pst->npc->switch_header_type ==
> +                          ROC_PRIV_FLAGS_EXDSA) {
> +                       lt = NPC_LT_LB_EXDSA;
> +               } else {
> +                       return -EINVAL;
> +               }
> +
> +               npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
> +                                                 pst->pattern->spec,
> +                                         (const struct roc_npc_flow_item_raw *)
> +                                                 pst->pattern->mask,
> +                                         &info, raw_spec_buf, raw_mask_buf);
> +
> +               info.hw_hdr_len = 0;
>         } else {
>                 return 0;
>         }
>
>         info.hw_mask = &hw_mask;
> -       info.spec = NULL;
> -       info.mask = NULL;
>         npc_get_hw_supp_mask(pst, &info, lid, lt);
>
>         rc = npc_parse_item_basic(pst->pattern, &info);
> @@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst)
>  int
>  npc_parse_lc(struct npc_parse_state *pst)
>  {
> +       const struct roc_npc_flow_item_raw *raw_spec;
> +       uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
> +       uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
>         uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];
>         struct npc_parse_item_info info;
> -       int lid, lt;
> +       int lid, lt, len = 0;
>         int rc;
>
>         if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS)
> @@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst)
>                 lt = NPC_LT_LC_CUSTOM0;
>                 info.len = pst->pattern->size;
>                 break;
> +       case ROC_NPC_ITEM_TYPE_RAW:
> +               raw_spec = pst->pattern->spec;
> +               if (!raw_spec->relative)
> +                       return 0;
> +
> +               len = raw_spec->length + raw_spec->offset;
> +               if (len > NPC_MAX_RAW_ITEM_LEN)
> +                       return -EINVAL;
> +
> +               npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
> +                                                 pst->pattern->spec,
> +                                         (const struct roc_npc_flow_item_raw *)
> +                                                 pst->pattern->mask,
> +                                         &info, raw_spec_buf, raw_mask_buf);
> +
> +               lid = NPC_LID_LC;
> +               lt = NPC_LT_LC_NGIO;
> +               info.hw_mask = &hw_mask;
> +               npc_get_hw_supp_mask(pst, &info, lid, lt);
> +               break;
>         default:
>                 /* No match at this layer */
>                 return 0;
> @@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst)
>
>         npc_get_hw_supp_mask(pst, &info, lid, lt);
>         rc = npc_parse_item_basic(pst->pattern, &info);
> +
>         if (rc != 0)
>                 return rc;
>
> diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
> index 484c3aeb1..5b884e3fd 100644
> --- a/drivers/common/cnxk/roc_npc_priv.h
> +++ b/drivers/common/cnxk/roc_npc_priv.h
> @@ -5,10 +5,11 @@
>  #ifndef _ROC_NPC_PRIV_H_
>  #define _ROC_NPC_PRIV_H_
>
> -#define NPC_IH_LENGTH    8
> -#define NPC_TPID_LENGTH          2
> -#define NPC_HIGIG2_LENGTH 16
> -#define NPC_COUNTER_NONE  (-1)
> +#define NPC_IH_LENGTH       8
> +#define NPC_TPID_LENGTH             2
> +#define NPC_HIGIG2_LENGTH    16
> +#define NPC_MAX_RAW_ITEM_LEN 16
> +#define NPC_COUNTER_NONE     (-1)
>
>  #define NPC_RSS_GRPS 8
>
> diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
> index 5c97588e6..5fcb56c35 100644
> --- a/drivers/common/cnxk/roc_npc_utils.c
> +++ b/drivers/common/cnxk/roc_npc_utils.c
> @@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
>         }
>
>         /* We have valid spec */
> -       info->spec = item->spec;
> +       if (item->type != ROC_NPC_ITEM_TYPE_RAW)
> +               info->spec = item->spec;
>
>         /* If mask is not set, use default mask, err if default mask is
>          * also NULL.
> @@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
>                         return NPC_ERR_PARAM;
>                 info->mask = info->def_mask;
>         } else {
> -               info->mask = item->mask;
> +               if (item->type != ROC_NPC_ITEM_TYPE_RAW)
> +                       info->mask = item->mask;
>         }
>
>         /* mask specified must be subset of hw supported mask
> diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c
> index 542252fe4..9cb8708a7 100644
> --- a/drivers/common/cnxk/roc_utils.c
> +++ b/drivers/common/cnxk/roc_utils.c
> @@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode)
>                 err_msg = "NPC invalid spec";
>                 break;
>         case NPC_ERR_INVALID_MASK:
> -               err_msg = "NPC  invalid mask";
> +               err_msg = "NPC invalid mask";
>                 break;
>         case NPC_ERR_INVALID_KEX:
>                 err_msg = "NPC invalid key";
> --
> 2.25.4
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw
@ 2021-07-12  6:49 psatheesh
  2021-07-13 11:18 ` Jerin Jacob
  0 siblings, 1 reply; 6+ messages in thread
From: psatheesh @ 2021-07-12  6:49 UTC (permalink / raw)
  To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, Satheesh Paul

From: Satheesh Paul <psatheesh@marvell.com>

Add roc API for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h      | 24 ++++++--
 drivers/common/cnxk/roc_nix_ops.c   | 14 +++++
 drivers/common/cnxk/roc_npc.h       | 11 ++++
 drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_npc_priv.h  |  9 +--
 drivers/common/cnxk/roc_npc_utils.c |  6 +-
 drivers/common/cnxk/roc_utils.c     |  2 +-
 7 files changed, 136 insertions(+), 16 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 9c529d754..b254f005a 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -278,14 +278,28 @@ struct ready_msg_rsp {
 	uint16_t __io rclk_freq; /* RCLK frequency */
 };
 
+enum npc_pkind_type {
+	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+	NPC_RX_CHLEN24B_PKIND,
+	NPC_RX_CPT_HDR_PKIND,
+	NPC_RX_CHLEN90B_PKIND,
+	NPC_TX_HIGIG_PKIND,
+	NPC_RX_HIGIG_PKIND,
+	NPC_RX_EXDSA_PKIND,
+	NPC_RX_EDSA_PKIND,
+	NPC_TX_DEF_PKIND,
+};
+
 /* Struct to set pkind */
 struct npc_set_pkind {
 	struct mbox_msghdr hdr;
-#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
-#define ROC_PRIV_FLAGS_EDSA    BIT_ULL(1)
-#define ROC_PRIV_FLAGS_HIGIG   BIT_ULL(2)
-#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
-#define ROC_PRIV_FLAGS_CUSTOM  BIT_ULL(63)
+#define ROC_PRIV_FLAGS_DEFAULT	  BIT_ULL(0)
+#define ROC_PRIV_FLAGS_EDSA	  BIT_ULL(1)
+#define ROC_PRIV_FLAGS_HIGIG	  BIT_ULL(2)
+#define ROC_PRIV_FLAGS_LEN_90B	  BIT_ULL(3)
+#define ROC_PRIV_FLAGS_EXDSA	  BIT_ULL(4)
+#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
+#define ROC_PRIV_FLAGS_CUSTOM	  BIT_ULL(63)
 	uint64_t __io mode;
 #define PKIND_TX BIT_ULL(0)
 #define PKIND_RX BIT_ULL(1)
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index eeb85a54f..0e28302e7 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	    switch_header_type != ROC_PRIV_FLAGS_EDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 	    switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&
+	    switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
+	    switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
 	    switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
 		plt_err("switch header type is not supported");
 		return NIX_ERR_PARAM;
@@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)
 	if (req == NULL)
 		return rc;
 	req->mode = switch_header_type;
+
+	if (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_CHLEN90B_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_EXDSA_PKIND;
+	} else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+		req->mode = ROC_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
+	}
+
 	req->dir = PKIND_RX;
 	rc = mbox_process_msg(mbox, (void *)&rsp);
 	if (rc)
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 2c0a536c9..bab25fd72 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -36,6 +36,7 @@ enum roc_npc_item_type {
 	ROC_NPC_ITEM_TYPE_CPT_HDR,
 	ROC_NPC_ITEM_TYPE_L3_CUSTOM,
 	ROC_NPC_ITEM_TYPE_QINQ,
+	ROC_NPC_ITEM_TYPE_RAW,
 	ROC_NPC_ITEM_TYPE_END,
 };
 
@@ -47,6 +48,16 @@ struct roc_npc_item_info {
 	const void *last; /* For range */
 };
 
+struct roc_npc_flow_item_raw {
+	uint32_t relative : 1; /**< Look for pattern after the previous item. */
+	uint32_t search : 1;   /**< Search pattern from offset. */
+	uint32_t reserved : 30; /**< Reserved, must be set to zero. */
+	int32_t offset;		/**< Absolute or relative offset for pattern. */
+	uint16_t limit;		/**< Search area limit for start of pattern. */
+	uint16_t length;	/**< Pattern length. */
+	const uint8_t *pattern; /**< Byte string to look for. */
+};
+
 #define ROC_NPC_MAX_ACTION_COUNT 12
 
 enum roc_npc_action_type {
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index d07f91db3..8125035dd 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst)
 	return npc_update_parse_state(pst, &info, lid, lt, 0);
 }
 
+static int
+npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,
+			  const struct roc_npc_flow_item_raw *raw_mask,
+			  struct npc_parse_item_info *info, uint8_t *spec_buf,
+			  uint8_t *mask_buf)
+{
+	uint32_t custom_hdr_size = 0;
+
+	memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+	custom_hdr_size = raw_spec->offset + raw_spec->length;
+
+	memcpy(spec_buf + raw_spec->offset, raw_spec->pattern,
+	       raw_spec->length);
+
+	if (raw_mask->pattern) {
+		memcpy(mask_buf + raw_spec->offset, raw_mask->pattern,
+		       raw_spec->length);
+	} else {
+		memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);
+	}
+
+	info->len = custom_hdr_size;
+	info->spec = spec_buf;
+	info->mask = mask_buf;
+
+	return 0;
+}
+
 int
 npc_parse_lb(struct npc_parse_state *pst)
 {
 	const struct roc_npc_item_info *pattern = pst->pattern;
 	const struct roc_npc_item_info *last_pattern;
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	char hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt, lflags;
+	int lid, lt, lflags, len = 0;
 	int nr_vlans = 0;
 	int rc;
 
@@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst)
 		info.len = pst->pattern->size;
 		lt = NPC_LT_LB_STAG_QINQ;
 		lflags = NPC_F_STAG_CTAG;
+	} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {
+		raw_spec = pst->pattern->spec;
+		if (raw_spec->relative)
+			return 0;
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		if (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) {
+			lt = NPC_LT_LB_VLAN_EXDSA;
+		} else if (pst->npc->switch_header_type ==
+			   ROC_PRIV_FLAGS_EXDSA) {
+			lt = NPC_LT_LB_EXDSA;
+		} else {
+			return -EINVAL;
+		}
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		info.hw_hdr_len = 0;
 	} else {
 		return 0;
 	}
 
 	info.hw_mask = &hw_mask;
-	info.spec = NULL;
-	info.mask = NULL;
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 
 	rc = npc_parse_item_basic(pst->pattern, &info);
@@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst)
 int
 npc_parse_lc(struct npc_parse_state *pst)
 {
+	const struct roc_npc_flow_item_raw *raw_spec;
+	uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+	uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
 	uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];
 	struct npc_parse_item_info info;
-	int lid, lt;
+	int lid, lt, len = 0;
 	int rc;
 
 	if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS)
@@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst)
 		lt = NPC_LT_LC_CUSTOM0;
 		info.len = pst->pattern->size;
 		break;
+	case ROC_NPC_ITEM_TYPE_RAW:
+		raw_spec = pst->pattern->spec;
+		if (!raw_spec->relative)
+			return 0;
+
+		len = raw_spec->length + raw_spec->offset;
+		if (len > NPC_MAX_RAW_ITEM_LEN)
+			return -EINVAL;
+
+		npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *)
+						  pst->pattern->spec,
+					  (const struct roc_npc_flow_item_raw *)
+						  pst->pattern->mask,
+					  &info, raw_spec_buf, raw_mask_buf);
+
+		lid = NPC_LID_LC;
+		lt = NPC_LT_LC_NGIO;
+		info.hw_mask = &hw_mask;
+		npc_get_hw_supp_mask(pst, &info, lid, lt);
+		break;
 	default:
 		/* No match at this layer */
 		return 0;
@@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst)
 
 	npc_get_hw_supp_mask(pst, &info, lid, lt);
 	rc = npc_parse_item_basic(pst->pattern, &info);
+
 	if (rc != 0)
 		return rc;
 
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index 484c3aeb1..5b884e3fd 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -5,10 +5,11 @@
 #ifndef _ROC_NPC_PRIV_H_
 #define _ROC_NPC_PRIV_H_
 
-#define NPC_IH_LENGTH	  8
-#define NPC_TPID_LENGTH	  2
-#define NPC_HIGIG2_LENGTH 16
-#define NPC_COUNTER_NONE  (-1)
+#define NPC_IH_LENGTH	     8
+#define NPC_TPID_LENGTH	     2
+#define NPC_HIGIG2_LENGTH    16
+#define NPC_MAX_RAW_ITEM_LEN 16
+#define NPC_COUNTER_NONE     (-1)
 
 #define NPC_RSS_GRPS 8
 
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 5c97588e6..5fcb56c35 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 	}
 
 	/* We have valid spec */
-	info->spec = item->spec;
+	if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+		info->spec = item->spec;
 
 	/* If mask is not set, use default mask, err if default mask is
 	 * also NULL.
@@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
 			return NPC_ERR_PARAM;
 		info->mask = info->def_mask;
 	} else {
-		info->mask = item->mask;
+		if (item->type != ROC_NPC_ITEM_TYPE_RAW)
+			info->mask = item->mask;
 	}
 
 	/* mask specified must be subset of hw supported mask
diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c
index 542252fe4..9cb8708a7 100644
--- a/drivers/common/cnxk/roc_utils.c
+++ b/drivers/common/cnxk/roc_utils.c
@@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode)
 		err_msg = "NPC invalid spec";
 		break;
 	case NPC_ERR_INVALID_MASK:
-		err_msg = "NPC  invalid mask";
+		err_msg = "NPC invalid mask";
 		break;
 	case NPC_ERR_INVALID_KEX:
 		err_msg = "NPC invalid key";
-- 
2.25.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-07-13 11:18 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-05  4:09 [dpdk-dev] [PATCH 1/2] common/cnxk: add support for rte flow item raw psatheesh
2021-07-05  4:09 ` [dpdk-dev] [PATCH 2/2] net/cnxk: " psatheesh
2021-07-06 10:47 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: " psatheesh
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2021-07-12  6:49 [dpdk-dev] [PATCH 1/2] common/cnxk: " psatheesh
2021-07-13 11:18 ` Jerin Jacob

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