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Tue, 06 Jul 2021 16:49:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id b3sm18058114pfi.179.2021.07.06.16.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jul 2021 16:49:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/36] target/arm: Add isar_feature_aa32_a32 Date: Tue, 6 Jul 2021 16:49:11 -0700 Message-Id: <20210706234932.356913-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210706234932.356913-1-richard.henderson@linaro.org> References: <20210706234932.356913-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a probe for whether A32 mode is supported. Fill in the field for the pre-v5 cpus. Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/cpu_tcg.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be9a4dceae..33f7ce9bc5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3802,6 +3802,11 @@ static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; } +static inline bool isar_feature_aa32_a32(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, STATE0) != 0; +} + static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d2d97115ea..980f62f35d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -73,6 +73,8 @@ static void arm926_initfn(Object *obj) cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + /* Similarly, we need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); } static void arm946_initfn(Object *obj) @@ -86,6 +88,9 @@ static void arm946_initfn(Object *obj) cpu->midr = 0x41059461; cpu->ctr = 0x0f004006; cpu->reset_sctlr = 0x00000078; + + /* We need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); } static void arm1026_initfn(Object *obj) @@ -115,6 +120,8 @@ static void arm1026_initfn(Object *obj) cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + /* Similarly, we need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ -- 2.25.1