From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84048C07E95 for ; Wed, 7 Jul 2021 09:27:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 632B361CC0 for ; Wed, 7 Jul 2021 09:27:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230484AbhGGJaU (ORCPT ); Wed, 7 Jul 2021 05:30:20 -0400 Received: from mail.kernel.org ([198.145.29.99]:50568 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230474AbhGGJaU (ORCPT ); Wed, 7 Jul 2021 05:30:20 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3307761CBA; Wed, 7 Jul 2021 09:27:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625650060; bh=eQRJz6lggUJb8SZU1qZY+jo9rN8hvlgDH0IFe/UbUmI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=U3e6mgB8MNLcTTkO5xbJIxRXSbMK/c9sK+jubLeOugqsbTIBPSa4X6Z3ndP93vyAe hR+fHsgYf1QS9kT2SS+LVFu8Y3xfOQI4qroFZTestEalaCNe14Gg7zmnMn+NRDrgMl F+NeGNZt7XPxnXeRaJWkmhKyTARP9OamRTjldI74l8k4QEqk7DW6ZefS7JRr/cFKNc liaCGjGaTXzit1wZ2Mub0W34RqweooKzwpiWUd8XXMC9dHLR7saWbI7tj7DNuDlAy1 OFRU4TFeCTXFKCiVtszIC2Me6SHhYH8nSLMjipSNyLqO954h6sVP+OeYZCNbUMrgy2 y1IoseVZkJR8w== Date: Wed, 7 Jul 2021 10:27:34 +0100 From: Will Deacon To: Bjorn Andersson Cc: Arnd Bergmann , Yassine Oudjana , Marc Zyngier , Robin Murphy , Catalin Marinas , Ard Biesheuvel , Android Kernel Team , Linux ARM , Mark Rutland , Vincent Whitchurch , linux-arm-msm Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Message-ID: <20210707092734.GA21603@willie-the-truck> References: <20210706102634.GB24903@arm.com> <59800d6c-364a-f4be-e341-c5b531657ba3@arm.com> <20210706133314.GB20327@willie-the-truck> <87zguz7b6b.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Jul 06, 2021 at 05:27:53PM -0500, Bjorn Andersson wrote: > On Tue 06 Jul 15:33 CDT 2021, Arnd Bergmann wrote: > > > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana wrote: > > > > (the numactl command helps run this both on the 'big' and 'little' > > > > cores without running into migration) > > > > > > > > Arnd > > > > > > Here are the results: > > > > Thanks, that was quick > > > > > $ numactl -C 0 line -M 1M > > > 128 > > > $ numactl -C 3 line -M 1M > > > 128 > > > $ numactl -C 0 cache > > > L1 cache: 512 bytes 1.37 nanoseconds 64 linesize -1.00 parallelism > > > L2 cache: 24576 bytes 2.75 nanoseconds 64 linesize 5.06 parallelism > > > L3 cache: 131072 bytes 7.89 nanoseconds 64 linesize 3.85 parallelism > > > L4 cache: 524288 bytes 15.86 nanoseconds 128 linesize 3.48 parallelism > > > Memory latency: 145.93 nanoseconds 4.88 parallelism > > > $ numactl -C 3 cache > > > L1 cache: 24576 bytes 1.29 nanoseconds 64 linesize 5.00 parallelism > > > L2 cache: 1048576 bytes 8.60 nanoseconds 128 linesize 3.07 parallelism > > > Memory latency: 143.29 nanoseconds 5.37 parallelism > > > > This is still somewhat inconclusive, but it does give some hope. The data that > > I found on random web sites was > > > > - 32KB L1, 2MB/1MB L2 [1][2] > > - 16KB L1, 1.5MB L2 [3] > > - 32KB L1, 1MB/512KB L2 [4] > > > > so none of the sizes really line up. My best guess is that the actual hierarchy > > > > 1MB per-core L2 cache on the two big CPU, 512KB per-core L2 cache on > > the two little ones, but no shared L2 or L3. The older Krait had a 4KB L0 > > cache, which could explain the 512-byte L1 output. > > > > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64 > > byte L1 line size that the 'cache' test reported? > > I can confirm that MSM8996, and a few derivatives, has 128 byte cache > lines. Do you know if the caches with 128-byte lines sit above the PoC? i.e. is non-coherent DMA coherent with this cache or not? Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08201C07E9C for ; Wed, 7 Jul 2021 10:15:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B940E61C92 for ; Wed, 7 Jul 2021 10:15:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B940E61C92 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; 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Wed, 07 Jul 2021 10:12:55 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m13qH-00EF8V-7v for linux-arm-kernel@lists.infradead.org; Wed, 07 Jul 2021 09:27:42 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3307761CBA; Wed, 7 Jul 2021 09:27:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625650060; bh=eQRJz6lggUJb8SZU1qZY+jo9rN8hvlgDH0IFe/UbUmI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=U3e6mgB8MNLcTTkO5xbJIxRXSbMK/c9sK+jubLeOugqsbTIBPSa4X6Z3ndP93vyAe hR+fHsgYf1QS9kT2SS+LVFu8Y3xfOQI4qroFZTestEalaCNe14Gg7zmnMn+NRDrgMl F+NeGNZt7XPxnXeRaJWkmhKyTARP9OamRTjldI74l8k4QEqk7DW6ZefS7JRr/cFKNc liaCGjGaTXzit1wZ2Mub0W34RqweooKzwpiWUd8XXMC9dHLR7saWbI7tj7DNuDlAy1 OFRU4TFeCTXFKCiVtszIC2Me6SHhYH8nSLMjipSNyLqO954h6sVP+OeYZCNbUMrgy2 y1IoseVZkJR8w== Date: Wed, 7 Jul 2021 10:27:34 +0100 From: Will Deacon To: Bjorn Andersson Cc: Arnd Bergmann , Yassine Oudjana , Marc Zyngier , Robin Murphy , Catalin Marinas , Ard Biesheuvel , Android Kernel Team , Linux ARM , Mark Rutland , Vincent Whitchurch , linux-arm-msm Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Message-ID: <20210707092734.GA21603@willie-the-truck> References: <20210706102634.GB24903@arm.com> <59800d6c-364a-f4be-e341-c5b531657ba3@arm.com> <20210706133314.GB20327@willie-the-truck> <87zguz7b6b.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210707_022741_387351_4E9964A6 X-CRM114-Status: GOOD ( 20.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 06, 2021 at 05:27:53PM -0500, Bjorn Andersson wrote: > On Tue 06 Jul 15:33 CDT 2021, Arnd Bergmann wrote: > > > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana wrote: > > > > (the numactl command helps run this both on the 'big' and 'little' > > > > cores without running into migration) > > > > > > > > Arnd > > > > > > Here are the results: > > > > Thanks, that was quick > > > > > $ numactl -C 0 line -M 1M > > > 128 > > > $ numactl -C 3 line -M 1M > > > 128 > > > $ numactl -C 0 cache > > > L1 cache: 512 bytes 1.37 nanoseconds 64 linesize -1.00 parallelism > > > L2 cache: 24576 bytes 2.75 nanoseconds 64 linesize 5.06 parallelism > > > L3 cache: 131072 bytes 7.89 nanoseconds 64 linesize 3.85 parallelism > > > L4 cache: 524288 bytes 15.86 nanoseconds 128 linesize 3.48 parallelism > > > Memory latency: 145.93 nanoseconds 4.88 parallelism > > > $ numactl -C 3 cache > > > L1 cache: 24576 bytes 1.29 nanoseconds 64 linesize 5.00 parallelism > > > L2 cache: 1048576 bytes 8.60 nanoseconds 128 linesize 3.07 parallelism > > > Memory latency: 143.29 nanoseconds 5.37 parallelism > > > > This is still somewhat inconclusive, but it does give some hope. The data that > > I found on random web sites was > > > > - 32KB L1, 2MB/1MB L2 [1][2] > > - 16KB L1, 1.5MB L2 [3] > > - 32KB L1, 1MB/512KB L2 [4] > > > > so none of the sizes really line up. My best guess is that the actual hierarchy > > > > 1MB per-core L2 cache on the two big CPU, 512KB per-core L2 cache on > > the two little ones, but no shared L2 or L3. The older Krait had a 4KB L0 > > cache, which could explain the 512-byte L1 output. > > > > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64 > > byte L1 line size that the 'cache' test reported? > > I can confirm that MSM8996, and a few derivatives, has 128 byte cache > lines. Do you know if the caches with 128-byte lines sit above the PoC? i.e. is non-coherent DMA coherent with this cache or not? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel