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The others use various tricks to reduce the tcg operation count. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 82 ++++++++++--------------- 1 file changed, 31 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index a422dc9ef4..840187a4d6 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -352,24 +352,23 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); - /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(t, t); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); + + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + + tcg_gen_extract_tl(dest, src1, a->shamt, 32 - a->shamt); + tcg_gen_ext32s_tl(dest, dest); return true; } static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); + + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + + tcg_gen_sextract_tl(dest, src1, a->shamt, 32 - a->shamt); return true; } @@ -388,64 +387,45 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; + return gen_shiftw(ctx, a, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); + TCGv ext2 = tcg_temp_new(); - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); + tcg_gen_andi_tl(ext2, src2, 31); + tcg_gen_ext32u_tl(dest, src1); + tcg_gen_shr_tl(dest, dest, ext2); + tcg_gen_ext32s_tl(dest, dest); - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + tcg_temp_free(ext2); return true; } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); + TCGv ext2 = tcg_temp_new(); + tcg_gen_andi_tl(ext2, src2, 31); /* - * first, trick to get it to act like working on 32 bits (get rid of - * upper 32, sign extend to fill space) + * First, trick to get it to act like working on 32 bits + * (get rid of upper 32, sign extend to fill space) */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + tcg_gen_ext32s_tl(dest, src1); + tcg_gen_sar_tl(dest, dest, ext2); + tcg_temp_free(ext2); return true; } -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1m1i6O-0007FA-Mr for mharc-qemu-riscv@gnu.org; Fri, 09 Jul 2021 00:27:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1i60-0006RF-Gr for qemu-riscv@nongnu.org; Fri, 09 Jul 2021 00:26:36 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:37752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1i5f-0001Vj-P8 for qemu-riscv@nongnu.org; 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envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Jul 2021 04:26:36 -0000 For trans_sllw, we can just use gen_shiftw. The others use various tricks to reduce the tcg operation count. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 82 ++++++++++--------------- 1 file changed, 31 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index a422dc9ef4..840187a4d6 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -352,24 +352,23 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); - /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(t, t); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); + + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + + tcg_gen_extract_tl(dest, src1, a->shamt, 32 - a->shamt); + tcg_gen_ext32s_tl(dest, dest); return true; } static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); + + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + + tcg_gen_sextract_tl(dest, src1, a->shamt, 32 - a->shamt); return true; } @@ -388,64 +387,45 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; + return gen_shiftw(ctx, a, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); + TCGv ext2 = tcg_temp_new(); - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); + tcg_gen_andi_tl(ext2, src2, 31); + tcg_gen_ext32u_tl(dest, src1); + tcg_gen_shr_tl(dest, dest, ext2); + tcg_gen_ext32s_tl(dest, dest); - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + tcg_temp_free(ext2); return true; } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); + TCGv ext2 = tcg_temp_new(); + tcg_gen_andi_tl(ext2, src2, 31); /* - * first, trick to get it to act like working on 32 bits (get rid of - * upper 32, sign extend to fill space) + * First, trick to get it to act like working on 32 bits + * (get rid of upper 32, sign extend to fill space) */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + tcg_gen_ext32s_tl(dest, src1); + tcg_gen_sar_tl(dest, dest, ext2); + tcg_temp_free(ext2); return true; } -- 2.25.1