Hi Huacai, I love your patch! Perhaps something to improve: [auto build test WARNING on tip/irq/core] [also build test WARNING on linux/master linus/master v5.13 next-20210708] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Huacai-Chen/irqchip-Add-LoongArch-related-irqchip-drivers/20210706-111309 base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 3d2ce675aba7e2425710e23268579a5d76c7e725 config: mips-loongson2k_defconfig (attached as .config) compiler: mips64el-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/04fd429333496372c9a6edc920872e35ede4c900 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Huacai-Chen/irqchip-Add-LoongArch-related-irqchip-drivers/20210706-111309 git checkout 04fd429333496372c9a6edc920872e35ede4c900 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): drivers/irqchip/irq-loongson-eiointc.c: In function 'eiointc_set_irq_route': drivers/irqchip/irq-loongson-eiointc.c:65:3: error: implicit declaration of function 'csr_any_send' [-Werror=implicit-function-declaration] 65 | csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node); | ^~~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c: At top level: >> drivers/irqchip/irq-loongson-eiointc.c:71:5: warning: no previous prototype for 'eiointc_set_irq_affinity' [-Wmissing-prototypes] 71 | int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c: In function 'eiointc_router_init': drivers/irqchip/irq-loongson-eiointc.c:116:3: error: implicit declaration of function 'eiointc_enable' [-Werror=implicit-function-declaration] 116 | eiointc_enable(); | ^~~~~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c:120:4: error: implicit declaration of function 'iocsr_writel' [-Werror=implicit-function-declaration] 120 | iocsr_writel(data, EIOINTC_REG_NODEMAP + i * 4); | ^~~~~~~~~~~~ In file included from include/linux/bits.h:6, from include/linux/bitops.h:6, from include/linux/kernel.h:12, from include/linux/interrupt.h:6, from drivers/irqchip/irq-loongson-eiointc.c:9: drivers/irqchip/irq-loongson-eiointc.c:130:14: error: implicit declaration of function 'cpu_logical_map' [-Werror=implicit-function-declaration] 130 | bit = BIT(cpu_logical_map(0)); | ^~~~~~~~~~~~~~~ include/vdso/bits.h:7:30: note: in definition of macro 'BIT' 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/irqchip/irq-loongson-eiointc.c: In function 'eiointc_irq_dispatch': drivers/irqchip/irq-loongson-eiointc.c:156:13: error: implicit declaration of function 'iocsr_readq' [-Werror=implicit-function-declaration] 156 | pending = iocsr_readq(EIOINTC_REG_ISR + (i << 3)); | ^~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c:157:3: error: implicit declaration of function 'iocsr_writeq' [-Werror=implicit-function-declaration] 157 | iocsr_writeq(pending, EIOINTC_REG_ISR + (i << 3)); | ^~~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c: At top level: >> drivers/irqchip/irq-loongson-eiointc.c:262:48: warning: 'struct acpi_madt_eio_pic' declared inside parameter list will not be visible outside of this definition or declaration 262 | struct fwnode_handle *eiointc_acpi_init(struct acpi_madt_eio_pic *acpi_eiointc) | ^~~~~~~~~~~~~~~~~ >> drivers/irqchip/irq-loongson-eiointc.c:262:23: warning: no previous prototype for 'eiointc_acpi_init' [-Wmissing-prototypes] 262 | struct fwnode_handle *eiointc_acpi_init(struct acpi_madt_eio_pic *acpi_eiointc) | ^~~~~~~~~~~~~~~~~ drivers/irqchip/irq-loongson-eiointc.c: In function 'eiointc_acpi_init': drivers/irqchip/irq-loongson-eiointc.c:293:15: error: 'LOONGSON_CPU_IRQ_BASE' undeclared (first use in this function); did you mean 'MIPS_CPU_IRQ_BASE'? 293 | parent_irq = LOONGSON_CPU_IRQ_BASE + acpi_eiointc->cascade; | ^~~~~~~~~~~~~~~~~~~~~ | MIPS_CPU_IRQ_BASE drivers/irqchip/irq-loongson-eiointc.c:293:15: note: each undeclared identifier is reported only once for each function it appears in drivers/irqchip/irq-loongson-eiointc.c:293:51: error: dereferencing pointer to incomplete type 'struct acpi_madt_eio_pic' 293 | parent_irq = LOONGSON_CPU_IRQ_BASE + acpi_eiointc->cascade; | ^~ cc1: some warnings being treated as errors vim +/eiointc_set_irq_affinity +71 drivers/irqchip/irq-loongson-eiointc.c 70 > 71 int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, 72 bool force) 73 { 74 unsigned int cpu; 75 unsigned long flags; 76 uint32_t vector, pos_off; 77 78 if (!IS_ENABLED(CONFIG_SMP)) 79 return -EPERM; 80 81 spin_lock_irqsave(&affinity_lock, flags); 82 83 if (!cpumask_intersects(affinity, cpu_online_mask)) { 84 spin_unlock_irqrestore(&affinity_lock, flags); 85 return -EINVAL; 86 } 87 cpu = cpumask_first_and(affinity, cpu_online_mask); 88 89 /* 90 * Control interrupt enable or disalbe through cpu 0 91 * which is reponsible for dispatching interrupts. 92 */ 93 vector = d->hwirq; 94 pos_off = vector >> 5; 95 96 csr_any_send(EIOINTC_REG_ENABLE + (pos_off << 2), 97 eiointc_priv->eiointc_en[pos_off] & (~((1 << (vector & 0x1F)))), 0x0, 0); 98 99 eiointc_set_irq_route(vector, cpu); 100 csr_any_send(EIOINTC_REG_ENABLE + (pos_off << 2), 101 eiointc_priv->eiointc_en[pos_off], 0x0, 0); 102 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 103 104 spin_unlock_irqrestore(&affinity_lock, flags); 105 106 return IRQ_SET_MASK_OK; 107 } 108 109 static int eiointc_router_init(unsigned int cpu) 110 { 111 int i, bit; 112 uint32_t data; 113 uint32_t node = cpu_to_node(cpu); 114 115 if (cpu == cpumask_first(cpumask_of_node(node))) { 116 eiointc_enable(); 117 118 for (i = 0; i < VEC_COUNT / 32; i++) { 119 data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2))); 120 iocsr_writel(data, EIOINTC_REG_NODEMAP + i * 4); 121 } 122 123 for (i = 0; i < VEC_COUNT / 32 / 4; i++) { 124 data = 0x02020202; /* Route to IP3 */ 125 iocsr_writel(data, EIOINTC_REG_IPMAP + i * 4); 126 } 127 128 for (i = 0; i < VEC_COUNT / 4; i++) { 129 /* Route to Node-0 Core-0 */ 130 bit = BIT(cpu_logical_map(0)); 131 data = bit | (bit << 8) | (bit << 16) | (bit << 24); 132 iocsr_writel(data, EIOINTC_REG_ROUTE + i * 4); 133 } 134 135 for (i = 0; i < VEC_COUNT / 32; i++) { 136 data = 0xffffffff; 137 iocsr_writel(data, EIOINTC_REG_ENABLE + i * 4); 138 iocsr_writel(data, EIOINTC_REG_BOUNCE + i * 4); 139 } 140 } 141 142 return 0; 143 } 144 145 static void eiointc_irq_dispatch(struct irq_desc *desc) 146 { 147 int i; 148 u64 pending; 149 bool handled = false; 150 struct irq_chip *chip = irq_desc_get_chip(desc); 151 struct eiointc_priv *priv = irq_desc_get_handler_data(desc); 152 153 chained_irq_enter(chip, desc); 154 155 for (i = 0; i < VEC_REG_COUNT; i++) { 156 pending = iocsr_readq(EIOINTC_REG_ISR + (i << 3)); 157 iocsr_writeq(pending, EIOINTC_REG_ISR + (i << 3)); 158 while (pending) { 159 int bit = __ffs(pending); 160 int virq = irq_linear_revmap(priv->eiointc_domain, bit + VEC_COUNT_PER_REG * i); 161 162 generic_handle_irq(virq); 163 pending &= ~BIT(bit); 164 handled = true; 165 } 166 } 167 168 if (!handled) 169 spurious_interrupt(); 170 171 chained_irq_exit(chip, desc); 172 } 173 174 static void eiointc_ack_irq(struct irq_data *d) 175 { 176 } 177 178 static void eiointc_mask_irq(struct irq_data *d) 179 { 180 } 181 182 static void eiointc_unmask_irq(struct irq_data *d) 183 { 184 } 185 186 static struct irq_chip eiointc_irq_chip = { 187 .name = "EIOINTC", 188 .irq_ack = eiointc_ack_irq, 189 .irq_mask = eiointc_mask_irq, 190 .irq_unmask = eiointc_unmask_irq, 191 .irq_set_affinity = eiointc_set_irq_affinity, 192 }; 193 194 static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq, 195 unsigned int nr_irqs, void *arg) 196 { 197 int ret; 198 unsigned int i, type; 199 unsigned long hwirq = 0; 200 struct eiointc *priv = domain->host_data; 201 202 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type); 203 if (ret) 204 return ret; 205 206 for (i = 0; i < nr_irqs; i++) { 207 irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip, 208 priv, handle_edge_irq, NULL, NULL); 209 } 210 211 return 0; 212 } 213 214 static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq, 215 unsigned int nr_irqs) 216 { 217 int i; 218 219 for (i = 0; i < nr_irqs; i++) { 220 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 221 222 irq_set_handler(virq + i, NULL); 223 irq_domain_reset_irq_data(d); 224 } 225 } 226 227 static const struct irq_domain_ops eiointc_domain_ops = { 228 .translate = irq_domain_translate_onecell, 229 .alloc = eiointc_domain_alloc, 230 .free = eiointc_domain_free, 231 }; 232 233 static int eiointc_suspend(void) 234 { 235 return 0; 236 } 237 238 static void eiointc_resume(void) 239 { 240 int i; 241 struct irq_desc *desc; 242 243 /* init irq en bitmap */ 244 for (i = 0; i < VEC_COUNT / 32; i++) 245 eiointc_priv->eiointc_en[i] = 0xffffffff; 246 247 eiointc_router_init(0); 248 249 for (i = 0; i < NR_IRQS; i++) { 250 desc = irq_to_desc(i); 251 if (desc && desc->handle_irq && desc->handle_irq != handle_bad_irq) 252 eiointc_set_irq_affinity(&desc->irq_data, 253 desc->irq_data.common->affinity, 0); 254 } 255 } 256 257 static struct syscore_ops eiointc_syscore_ops = { 258 .suspend = eiointc_suspend, 259 .resume = eiointc_resume, 260 }; 261 > 262 struct fwnode_handle *eiointc_acpi_init(struct acpi_madt_eio_pic *acpi_eiointc) --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org