[PATCH 00/15] introduce exynosauto v9 ufs driver

[PATCH 00/15] introduce exynosauto v9 ufs driver

[Chanho Park]

In ExynosAuto(variant of the Exynos for automotive), the UFS Storage needs
to be accessed from multi-OS. To increase IO performance and reduce SW
complexity, we implemented UFS-IOV to support storage IO virtualization
feature on UFS.

IO virtualization increases IO performance and reduce SW complexity
with small area cost. And IO virtualization supports virtual machine
isolation for Security and Safety which are requested by Multi-OS system
such as automotive application.

Below figure is the conception of UFS-IOV architeture.

    +------+          +------+
    | OS#1 |          | OS#2 |
    +------+          +------+
       |                 |
 +------------+     +------------+
 |  Physical  |     |   Virtual  |
 |    Host    |     |    Host    |
 +------------+     +------------+
   |      |              | <-- UTP_CMD_SAP, UTP_TM_SAP
   |   +-------------------------+
   |   |    Function Arbitor     |
   |   +-------------------------+
 +-------------------------------+
 |           UTP Layer           |
 +-------------------------------+
 +-------------------------------+
 |           UIC Layer           |
 +-------------------------------+

There are two types of host controllers on the UFS host controller
that we designed.
The UFS device has a Function Arbitor that arranges commands of each host.
When each host transmits a command to the Arbitor, the Arbitor transmits it
to the UTP layer.
Physical Host(PH) support all UFSHCI functions(all SAPs) same as
conventional UFSHCI.
Virtual Host(VH) support only data transfer function(UTP_CMD_SAP and
UTP_TM_SAP).

In an environment where multiple OSs are used, the OS that has the
leadership of the system is called System OS(Dom0). This system OS uses
PH and controls error handling.

Since VH can only use less functions than PH, it is necessary to send a
request to PH for Detected Error Handling in VH. To interface among PH
and VHs, UFSHCI HW supports mailbox. PH can broadcast mail to other VH at
the same time with arguments and VH can mail to PH with arguments.
PH and VH generate interrupts when mails from PH or VH.

In this structure, the virtual host can't support some feature and need
to skip the some part of ufshcd code by using quirk.
This patchs add quirks so that the UIC command is ignored and the ufshcd
init process can be skipped for VH. Also, according to our UFS-IOV policy,

First two patches, I picked them up from Jonmin's patchset[1] and the third
patch has been dropped because we need to check it again.

[1]: https://lore.kernel.org/linux-scsi/20210527030901.88403-1-jjmin.jeong@samsung.com/

Patch 0003 ~ 0012, they are changes of exynos7 ufs driver to apply
exynosauto v9 variant and PH/VH capabilities.
Patch 0013 ~ 0015, they introduce exynosauto v9 ufs MHCI which includes
PH and VH.

Chanho Park (13):
  scsi: ufs: ufs-exynos: change pclk available max value
  scsi: ufs: ufs-exynos: simplify drv_data retrieval
  scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency
  scsi: ufs: ufs-exynos: add refclkout_stop control
  scsi: ufs: ufs-exynos: add setup_clocks callback
  scsi: ufs: ufs-exynos: correct timeout value setting registers
  scsi: ufs: ufs-exynos: support custom version of ufs_hba_variant_ops
  scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
  scsi: ufs: ufs-exynos: factor out priv data init
  scsi: ufs: ufs-exynos: add pre/post_hce_enable drv callbacks
  scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver
  scsi: ufs: ufs-exynos: multi-host configuration for exynosauto
  scsi: ufs: ufs-exynos: introduce exynosauto v9 virtual host

jongmin jeong (2):
  scsi: ufs: add quirk to handle broken UIC command
  scsi: ufs: add quirk to enable host controller without interface
    configuration

 drivers/scsi/ufs/ufs-exynos.c | 318 +++++++++++++++++++++++++++++++---
 drivers/scsi/ufs/ufs-exynos.h |  10 +-
 drivers/scsi/ufs/ufshcd.c     |   6 +
 drivers/scsi/ufs/ufshcd.h     |  12 ++
 4 files changed, 320 insertions(+), 26 deletions(-)

-- 
2.32.0

[PATCH 01/15] scsi: ufs: add quirk to handle broken UIC command

[Chanho Park]

From: jongmin jeong <jjmin.jeong@samsung.com>

samsung ExynosAuto9 SoC has two types of host controller interface to
support the virtualization of UFS Device.
One is the physical host(PH) that the same as conventaional UFSHCI,
and the other is the virtual host(VH) that support data transfer function
only.

In this structure, the virtual host does not support UIC command.
To support this, we add the quirk and return 0 when the UIC command
send function is called.

Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufshcd.c | 3 +++
 drivers/scsi/ufs/ufshcd.h | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b87ff68aa9aa..9702086e9860 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2350,6 +2350,9 @@ int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
 	int ret;
 	unsigned long flags;
 
+	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
+		return 0;
+
 	ufshcd_hold(hba, false);
 	mutex_lock(&hba->uic_cmd_mutex);
 	ufshcd_add_delay_before_dme_cmd(hba);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c98d540ac044..e67b1fcfe1a2 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -567,6 +567,12 @@ enum ufshcd_quirks {
 	 * This quirk allows only sg entries aligned with page size.
 	 */
 	UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE		= 1 << 14,
+
+	/*
+	 * This quirk needs to be enabled if the host controller does not
+	 * support UIC command
+	 */
+	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
 };
 
 enum ufshcd_caps {
-- 
2.32.0

[PATCH 02/15] scsi: ufs: add quirk to enable host controller without interface configuration

[Chanho Park]

From: jongmin jeong <jjmin.jeong@samsung.com>

samsung ExynosAuto SoC has two types of host controller interface to
support the virtualization of UFS Device.
One is the physical host(PH) that the same as conventaional UFSHCI,
and the other is the virtual host(VH) that support data transfer function only.

In this structure, the virtual host does not support like device management.
This patch skips the interface configuration part that cannot be performed
in the virtual host.

Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufshcd.c | 3 +++
 drivers/scsi/ufs/ufshcd.h | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 9702086e9860..3451b335f2b4 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -7988,6 +7988,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
 	if (ret)
 		goto out;
 
+	if (hba->quirks & UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION)
+		goto out;
+
 	/* Debug counters initialization */
 	ufshcd_clear_dbg_ufs_stats(hba);
 
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index e67b1fcfe1a2..fe523cbd68dd 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -573,6 +573,12 @@ enum ufshcd_quirks {
 	 * support UIC command
 	 */
 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
+
+	/*
+	 * This quirk needs to be enabled if the host controller cannot
+	 * support interface configuration.
+	 */
+	UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION	= 1 << 16,
 };
 
 enum ufshcd_caps {
-- 
2.32.0

[PATCH 03/15] scsi: ufs: ufs-exynos: change pclk available max value

[Chanho Park]

To support 167MHz PCLK, we need to adjust the maximum value.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 67505fe32ebf..475a5adf0f8b 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -99,7 +99,7 @@ struct exynos_ufs;
 #define PA_HIBERN8TIME_VAL	0x20
 
 #define PCLK_AVAIL_MIN	70000000
-#define PCLK_AVAIL_MAX	133000000
+#define PCLK_AVAIL_MAX	167000000
 
 struct exynos_ufs_uic_attr {
 	/* TX Attributes */
-- 
2.32.0

[PATCH 04/15] scsi: ufs: ufs-exynos: simplify drv_data retrieval

[Chanho Park]

The compatible field of exynos_ufs_drv_data is not necessary because
of_device_id already has it. Thus, we don't need it anymore and we can
get drv_data by device_get_match_data.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 10 +---------
 drivers/scsi/ufs/ufs-exynos.h |  3 +--
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index cf46d6f86e0e..db5892901cc0 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -893,17 +893,10 @@ static int exynos_ufs_post_link(struct ufs_hba *hba)
 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 {
 	struct device_node *np = dev->of_node;
-	struct exynos_ufs_drv_data *drv_data = &exynos_ufs_drvs;
 	struct exynos_ufs_uic_attr *attr;
 	int ret = 0;
 
-	while (drv_data->compatible) {
-		if (of_device_is_compatible(np, drv_data->compatible)) {
-			ufs->drv_data = drv_data;
-			break;
-		}
-		drv_data++;
-	}
+	ufs->drv_data = device_get_match_data(dev);
 
 	if (ufs->drv_data && ufs->drv_data->uic_attr) {
 		attr = ufs->drv_data->uic_attr;
@@ -1258,7 +1251,6 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
 };
 
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
-	.compatible		= "samsung,exynos7-ufs",
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
 				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 475a5adf0f8b..7bf2053f6e90 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -142,7 +142,6 @@ struct exynos_ufs_uic_attr {
 };
 
 struct exynos_ufs_drv_data {
-	char *compatible;
 	struct exynos_ufs_uic_attr *uic_attr;
 	unsigned int quirks;
 	unsigned int opts;
@@ -191,7 +190,7 @@ struct exynos_ufs {
 	struct ufs_pa_layer_attr dev_req_params;
 	struct ufs_phy_time_cfg t_cfg;
 	ktime_t entry_hibern8_t;
-	struct exynos_ufs_drv_data *drv_data;
+	const struct exynos_ufs_drv_data *drv_data;
 
 	u32 opts;
 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
-- 
2.32.0

[PATCH 05/15] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Chanho Park]

UFS_EMBD sharability register of fsys block provides "sharability"
setting of ufs-exynos. It can be set via syscon and regmap.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 5 +++++
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index db5892901cc0..da02ad3b036c 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 
@@ -906,6 +907,10 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 		goto out;
 	}
 
+	ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "sysreg");
+	if (IS_ERR(ufs->sysreg))
+		ufs->sysreg = NULL;
+
 	ufs->pclk_avail_min = PCLK_AVAIL_MIN;
 	ufs->pclk_avail_max = PCLK_AVAIL_MAX;
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 7bf2053f6e90..a46f30639f38 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -191,6 +191,7 @@ struct exynos_ufs {
 	struct ufs_phy_time_cfg t_cfg;
 	ktime_t entry_hibern8_t;
 	const struct exynos_ufs_drv_data *drv_data;
+	struct regmap *sysreg;
 
 	u32 opts;
 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
-- 
2.32.0

[PATCH 06/15] scsi: ufs: ufs-exynos: add refclkout_stop control

[Chanho Park]

This patch adds REFCLKOUT_STOP control to CLK_STOP_MASK. It can
en/disable reference clock out control for UFS device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index da02ad3b036c..78cc5bda0a1f 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -49,10 +49,11 @@
 #define HCI_ERR_EN_T_LAYER	0x84
 #define HCI_ERR_EN_DME_LAYER	0x88
 #define HCI_CLKSTOP_CTRL	0xB0
+#define REFCLKOUT_STOP		BIT(4)
 #define REFCLK_STOP		BIT(2)
 #define UNIPRO_MCLK_STOP	BIT(1)
 #define UNIPRO_PCLK_STOP	BIT(0)
-#define CLK_STOP_MASK		(REFCLK_STOP |\
+#define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
 				 UNIPRO_MCLK_STOP |\
 				 UNIPRO_PCLK_STOP)
 #define HCI_MISC		0xB4
-- 
2.32.0

[PATCH 07/15] scsi: ufs: ufs-exynos: add setup_clocks callback

[Chanho Park]

This patch adds setup_clocks callback to control/gate clocks by ufshcd.
To avoid calling before initialization, it needs to check whether ufs is
null or not and call it initially from pre_link callback.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 78cc5bda0a1f..530dab500d11 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -795,6 +795,27 @@ static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
 	}
 }
 
+static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
+				   enum ufs_notify_change_status status)
+{
+	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
+
+	if (!ufs)
+		return 0;
+
+	if (on) {
+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
+			exynos_ufs_disable_auto_ctrl_hcc(ufs);
+		exynos_ufs_ungate_clks(ufs);
+	} else {
+		exynos_ufs_gate_clks(ufs);
+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
+			exynos_ufs_enable_auto_ctrl_hcc(ufs);
+	}
+
+	return 0;
+}
+
 static int exynos_ufs_pre_link(struct ufs_hba *hba)
 {
 	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
@@ -813,6 +834,8 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
 	exynos_ufs_config_phy_time_attr(ufs);
 	exynos_ufs_config_phy_cap_attr(ufs);
 
+	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
+
 	if (ufs->drv_data->pre_link)
 		ufs->drv_data->pre_link(ufs);
 
@@ -1203,6 +1226,7 @@ static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.hce_enable_notify		= exynos_ufs_hce_enable_notify,
 	.link_startup_notify		= exynos_ufs_link_startup_notify,
 	.pwr_change_notify		= exynos_ufs_pwr_change_notify,
+	.setup_clocks			= exynos_ufs_setup_clocks,
 	.setup_xfer_req			= exynos_ufs_specify_nexus_t_xfer_req,
 	.setup_task_mgmt		= exynos_ufs_specify_nexus_t_tm_req,
 	.hibern8_notify			= exynos_ufs_hibern8_notify,
-- 
2.32.0

[PATCH 08/15] scsi: ufs: ufs-exynos: correct timeout value setting registers

[Chanho Park]

PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL
PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL
PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 530dab500d11..60edd420095f 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -644,9 +644,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
 	}
 
 	/* setting for three timeout values for traffic class #0 */
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064);
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 28224);
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
 
 	return 0;
 out:
-- 
2.32.0

[PATCH 09/15] scsi: ufs: ufs-exynos: support custom version of ufs_hba_variant_ops

[Chanho Park]

By default, ufs_hba_exynos_ops will be used but this patch supports to
use custom version of ufs_hba_variant_ops because some variants of
exynos-ufs will use only few callbacks.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 8 +++++++-
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 60edd420095f..90c0d7c85a13 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -1238,8 +1238,14 @@ static int exynos_ufs_probe(struct platform_device *pdev)
 {
 	int err;
 	struct device *dev = &pdev->dev;
+	const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
+	const struct exynos_ufs_drv_data *drv_data =
+		device_get_match_data(dev);
 
-	err = ufshcd_pltfrm_init(pdev, &ufs_hba_exynos_ops);
+	if (drv_data && drv_data->vops)
+		vops = drv_data->vops;
+
+	err = ufshcd_pltfrm_init(pdev, vops);
 	if (err)
 		dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index a46f30639f38..0938bd82763f 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -142,6 +142,7 @@ struct exynos_ufs_uic_attr {
 };
 
 struct exynos_ufs_drv_data {
+	const struct ufs_hba_variant_ops *vops;
 	struct exynos_ufs_uic_attr *uic_attr;
 	unsigned int quirks;
 	unsigned int opts;
-- 
2.32.0

[PATCH 10/15] scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option

[Chanho Park]

To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant,
this patch provides EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts
flag.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 6 ++++--
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 90c0d7c85a13..9a5a7a5ffc4b 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -831,8 +831,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
 
 	/* m-phy */
 	exynos_ufs_phy_init(ufs);
-	exynos_ufs_config_phy_time_attr(ufs);
-	exynos_ufs_config_phy_cap_attr(ufs);
+	if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
+		exynos_ufs_config_phy_time_attr(ufs);
+		exynos_ufs_config_phy_cap_attr(ufs);
+	}
 
 	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 0938bd82763f..8695270d38d9 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -200,6 +200,7 @@ struct exynos_ufs {
 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
+#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
 };
 
 #define for_each_ufs_rx_lane(ufs, i) \
-- 
2.32.0

[PATCH 11/15] scsi: ufs: ufs-exynos: factor out priv data init

[Chanho Park]

To be used this assignment code for other variant exynos-ufs driver,
this patch factors out the codes as inline code.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 9a5a7a5ffc4b..81b8b8d9915a 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -951,6 +951,18 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 	return ret;
 }
 
+static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
+					struct exynos_ufs *ufs)
+{
+	ufs->hba = hba;
+	ufs->opts = ufs->drv_data->opts;
+	ufs->rx_sel_idx = PA_MAXDATALANES;
+	if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
+		ufs->rx_sel_idx = 0;
+	hba->priv = (void *)ufs;
+	hba->quirks = ufs->drv_data->quirks;
+}
+
 static int exynos_ufs_init(struct ufs_hba *hba)
 {
 	struct device *dev = hba->dev;
@@ -1000,13 +1012,8 @@ static int exynos_ufs_init(struct ufs_hba *hba)
 	if (ret)
 		goto phy_off;
 
-	ufs->hba = hba;
-	ufs->opts = ufs->drv_data->opts;
-	ufs->rx_sel_idx = PA_MAXDATALANES;
-	if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
-		ufs->rx_sel_idx = 0;
-	hba->priv = (void *)ufs;
-	hba->quirks = ufs->drv_data->quirks;
+	exynos_ufs_priv_init(hba, ufs);
+
 	if (ufs->drv_data->drv_init) {
 		ret = ufs->drv_data->drv_init(dev, ufs);
 		if (ret) {
-- 
2.32.0

[PATCH 12/15] scsi: ufs: ufs-exynos: add pre/post_hce_enable drv callbacks

[Chanho Park]

This patch adds driver-specific pre/post_hce_enable callbacks to execute
extra initializations before and after hce_enable_notify callback.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 10 ++++++++++
 drivers/scsi/ufs/ufs-exynos.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 81b8b8d9915a..9669afe8f1f4 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -1141,6 +1141,12 @@ static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
 
 	switch (status) {
 	case PRE_CHANGE:
+		if (ufs->drv_data->pre_hce_enable) {
+			ret = ufs->drv_data->pre_hce_enable(ufs);
+			if (ret)
+				return ret;
+		}
+
 		ret = exynos_ufs_host_reset(hba);
 		if (ret)
 			return ret;
@@ -1150,6 +1156,10 @@ static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
 		exynos_ufs_calc_pwm_clk_div(ufs);
 		if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
 			exynos_ufs_enable_auto_ctrl_hcc(ufs);
+
+		if (ufs->drv_data->post_hce_enable)
+			ret = ufs->drv_data->post_hce_enable(ufs);
+
 		break;
 	}
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 8695270d38d9..9c44ca81020b 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -154,6 +154,8 @@ struct exynos_ufs_drv_data {
 				struct ufs_pa_layer_attr *pwr);
 	int (*post_pwr_change)(struct exynos_ufs *ufs,
 				struct ufs_pa_layer_attr *pwr);
+	int (*pre_hce_enable)(struct exynos_ufs *ufs);
+	int (*post_hce_enable)(struct exynos_ufs *ufs);
 };
 
 struct ufs_phy_time_cfg {
-- 
2.32.0

[PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Chanho Park]

This patch adds to support ufs variant for ExynosAuto v9 SoC. This
requires control UFS IP sharability register via syscon and regmap.
Regarding uic_attr, most of values can be shared with exynos7 except
tx_dif_p_nsec value.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 97 +++++++++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 9669afe8f1f4..82f915f7a447 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -15,6 +15,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #include "ufshcd.h"
 #include "ufshcd-pltfrm.h"
@@ -76,6 +77,12 @@
 				 UIC_TRANSPORT_NO_CONNECTION_RX |\
 				 UIC_TRANSPORT_BAD_TC)
 
+/* FSYS UFS Sharability */
+#define UFS_WR_SHARABLE		BIT(2)
+#define UFS_RD_SHARABLE		BIT(1)
+#define UFS_SHARABLE		(UFS_WR_SHARABLE | UFS_RD_SHARABLE)
+#define UFS_SHARABILITY_OFFSET	0x710
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -151,6 +158,80 @@ static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
 	return 0;
 }
 
+static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+	struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+
+	/* IO Coherency setting */
+	if (ufs->sysreg) {
+		return regmap_update_bits(ufs->sysreg, UFS_SHARABILITY_OFFSET,
+					  UFS_SHARABLE, UFS_SHARABLE);
+	}
+
+	attr->tx_dif_p_nsec = 3200000;
+
+	return 0;
+}
+
+static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+	int i;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
+	}
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
+
+	return 0;
+}
+
+static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					 struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	/* PACP_PWR_req and delivered to the remote DME */
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+
+	return 0;
+}
+
+
 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
 {
 	struct ufs_hba *hba = ufs->hba;
@@ -1305,6 +1386,20 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
 	.pa_dbg_option_suite		= 0x30103,
 };
 
+static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
+	.uic_attr		= &exynos7_uic_attr,
+	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+	.opts			= EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+	.drv_init		= exynosauto_ufs_drv_init,
+	.pre_link		= exynosauto_ufs_pre_link,
+	.pre_pwr_change		= exynosauto_ufs_pre_pwr_change,
+};
+
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
@@ -1330,6 +1425,8 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "samsung,exynos7-ufs",
 	  .data	      = &exynos_ufs_drvs },
+	{ .compatible = "samsung,exynosautov9-ufs",
+	  .data	      = &exynosauto_ufs_drvs },
 	{},
 };
 
-- 
2.32.0

[PATCH 14/15] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Chanho Park]

UFS controller of ExynosAuto v9 SoC supports multi-host interface for I/O
virtualization. In general, we're using para-virtualized driver to
support a block device by several virtual machines. However, it should
be relayed by backend driver. Multi-host functionality extends the host
controller by providing register interfaces that can be used by each
VM's ufs drivers respectively. By this, we can provide direct access to
the UFS device for multiple VMs. It's similar with SR-IOV of PCIe.

We divide this M-HCI as PH(Physical Host) and VHs(Virtual Host). The PH
supports all UFSHCI functions(all SAPs) same as conventional UFSHCI but
the VH only supports data transfer function. Thus, except UTP_CMD_SAP and
UTP_TMPSAP, the PH should handle all the physical features.

This patch provides an initial implementation of PH part. M-HCI can
support up to four interfaces but this patch initially supports only 1
PH and 1 VH. For this, we uses TASK_TAG[7:5] field so TASK_TAG[4:0] for
32 doorbel will be supported. After the PH is initiated, this will send
a ready message to VHs through a mailbox register. The message handler
is not fully implemented yet such as supporting reset / abort cases.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 44 +++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 82f915f7a447..30c12e97c665 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -83,6 +83,21 @@
 #define UFS_SHARABLE		(UFS_WR_SHARABLE | UFS_RD_SHARABLE)
 #define UFS_SHARABILITY_OFFSET	0x710
 
+/* Multi-host registers */
+#define MHCTRL					0xC4
+#define MHCTRL_EN_VH_MASK			(0xE)
+#define MHCTRL_EN_VH(vh)			(vh << 1)
+#define PH2VH_MBOX				0xD8
+
+#define MH_MSG_MASK				(0xFF)
+
+#define MH_MSG(id, msg)				((id << 8) | (msg & 0xFF))
+#define MH_MSG_PH_READY				0x1
+#define MH_MSG_VH_READY				0x2
+
+#define HCI_MH_ALLOWABLE_TRAN_OF_VH		0x30C
+#define HCI_MH_IID_IN_TASK_TAG			0X308
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -173,6 +188,20 @@ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
 	return 0;
 }
 
+static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	/* Enable Virtual Host #1 */
+	ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
+	/* Default VH Transfer permissions */
+	hci_writel(ufs, 0x03FFE1FE, HCI_MH_ALLOWABLE_TRAN_OF_VH);
+	/* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
+	hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
+
+	return 0;
+}
+
 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
 {
 	struct ufs_hba *hba = ufs->hba;
@@ -231,6 +260,19 @@ static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
+					  struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+	u32 enabled_vh;
+
+	enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
+
+	/* Send physical host ready message to virtual hosts */
+	ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
+
+	return 0;
+}
 
 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
 {
@@ -1396,8 +1438,10 @@ static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
 				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
 				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
 	.drv_init		= exynosauto_ufs_drv_init,
+	.post_hce_enable	= exynosauto_ufs_post_hce_enable,
 	.pre_link		= exynosauto_ufs_pre_link,
 	.pre_pwr_change		= exynosauto_ufs_pre_pwr_change,
+	.post_pwr_change	= exynosauto_ufs_post_pwr_change,
 };
 
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
-- 
2.32.0

[PATCH 15/15] scsi: ufs: ufs-exynos: introduce exynosauto v9 virtual host

[Chanho Park]

This patch introduces virtual host driver of exynosauto v9 ufs mHCI.
VH(Virtual Host) only supports data transfer functions. So, most of
physical features are broken. So, we need to set below quirks.
- UFSHCD_QUIRK_BROKEN_UIC_CMD
- UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION
Before initialization, the VH is necessary to wait until PH is ready.
It's implemented as polling at the moment.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 84 +++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 30c12e97c665..e0292711d2da 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -98,6 +98,8 @@
 #define HCI_MH_ALLOWABLE_TRAN_OF_VH		0x30C
 #define HCI_MH_IID_IN_TASK_TAG			0X308
 
+#define PH_READY_TIMEOUT_MS			(5 * MSEC_PER_SEC)
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -1362,6 +1364,68 @@ static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 	return 0;
 }
 
+static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
+						 enum ufs_notify_change_status status)
+{
+	if (status == POST_CHANGE) {
+		ufshcd_set_link_active(hba);
+		ufshcd_set_ufs_dev_active(hba);
+		hba->wlun_dev_clr_ua = true;
+	}
+
+	return 0;
+}
+
+static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
+{
+	u32 mbox;
+	ktime_t start, stop;
+
+	start = ktime_get();
+	stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
+
+	do {
+		mbox = ufshcd_readl(hba, PH2VH_MBOX);
+		if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
+			return 0;
+
+		usleep_range(40, 50);
+	} while (ktime_before(ktime_get(), stop));
+
+	return -ETIME;
+}
+
+static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
+{
+	struct device *dev = hba->dev;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct exynos_ufs *ufs;
+	int ret;
+
+	ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
+	if (!ufs)
+		return -ENOMEM;
+
+	/* exynos-specific hci */
+	ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
+	if (IS_ERR(ufs->reg_hci)) {
+		dev_err(dev, "cannot ioremap for hci vendor register\n");
+		return PTR_ERR(ufs->reg_hci);
+	}
+
+	ret = exynosauto_ufs_vh_wait_ph_ready(hba);
+	if (ret)
+		return ret;
+
+	ufs->drv_data = device_get_match_data(dev);
+	if (!ufs->drv_data)
+		return -ENODEV;
+
+	exynos_ufs_priv_init(hba, ufs);
+
+	return 0;
+}
+
 static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.name				= "exynos_ufs",
 	.init				= exynos_ufs_init,
@@ -1376,6 +1440,12 @@ static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.resume				= exynos_ufs_resume,
 };
 
+static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
+	.name				= "exynosauto_ufs_vh",
+	.init				= exynosauto_ufs_vh_init,
+	.link_startup_notify		= exynosauto_ufs_vh_link_startup_notify,
+};
+
 static int exynos_ufs_probe(struct platform_device *pdev)
 {
 	int err;
@@ -1444,6 +1514,18 @@ static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
 	.post_pwr_change	= exynosauto_ufs_post_pwr_change,
 };
 
+static struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
+	.vops			= &ufs_hba_exynosauto_vh_ops,
+	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCI_QUIRK_BROKEN_HCE |
+				  UFSHCD_QUIRK_BROKEN_UIC_CMD |
+				  UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION |
+				  UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+	.opts			= EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+};
+
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
@@ -1471,6 +1553,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynos_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs",
 	  .data	      = &exynosauto_ufs_drvs },
+	{ .compatible = "samsung,exynosautov9-ufs-vh",
+	  .data	      = &exynosauto_ufs_vh_drvs },
 	{},
 };
 
-- 
2.32.0

Re: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Krzysztof Kozlowski]

-On Fri, 9 Jul 2021 at 08:59, Chanho Park <chanho61.park@samsung.com> wrote:
>
> This patch adds to support ufs variant for ExynosAuto v9 SoC. This
> requires control UFS IP sharability register via syscon and regmap.
> Regarding uic_attr, most of values can be shared with exynos7 except
> tx_dif_p_nsec value.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/scsi/ufs/ufs-exynos.c | 97 +++++++++++++++++++++++++++++++++++
>  1 file changed, 97 insertions(+)
>
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index 9669afe8f1f4..82f915f7a447 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -15,6 +15,7 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
> +#include <linux/regmap.h>
>
>  #include "ufshcd.h"
>  #include "ufshcd-pltfrm.h"
> @@ -76,6 +77,12 @@
>                                  UIC_TRANSPORT_NO_CONNECTION_RX |\
>                                  UIC_TRANSPORT_BAD_TC)
>
> +/* FSYS UFS Sharability */

Sharability -> Shareability

> +#define UFS_WR_SHARABLE                BIT(2)
> +#define UFS_RD_SHARABLE                BIT(1)
> +#define UFS_SHARABLE           (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
> +#define UFS_SHARABILITY_OFFSET 0x710
> +
>  enum {
>         UNIPRO_L1_5 = 0,/* PHY Adapter */
>         UNIPRO_L2,      /* Data Link */
> @@ -151,6 +158,80 @@ static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
>         return 0;
>  }
>
> +static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
> +{
> +       struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
> +
> +       /* IO Coherency setting */
> +       if (ufs->sysreg) {
> +               return regmap_update_bits(ufs->sysreg, UFS_SHARABILITY_OFFSET,
> +                                         UFS_SHARABLE, UFS_SHARABLE);
> +       }
> +
> +       attr->tx_dif_p_nsec = 3200000;
> +
> +       return 0;
> +}
> +
> +static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
> +{
> +       struct ufs_hba *hba = ufs->hba;
> +       int i;
> +
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +       for_each_ufs_rx_lane(ufs, i) {
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
> +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
> +
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> +
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> +
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
> +       }
> +
> +       for_each_ufs_tx_lane(ufs, i) {
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
> +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
> +
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
> +
> +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
> +       }
> +
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
> +
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
> +
> +       return 0;
> +}
> +
> +static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> +                                        struct ufs_pa_layer_attr *pwr)
> +{
> +       struct ufs_hba *hba = ufs->hba;
> +
> +       /* PACP_PWR_req and delivered to the remote DME */
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
> +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
> +
> +       return 0;
> +}
> +

No need for double line.

> +
>  static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
>  {
>         struct ufs_hba *hba = ufs->hba;
> @@ -1305,6 +1386,20 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
>         .pa_dbg_option_suite            = 0x30103,
>  };
>
> +static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
> +       .uic_attr               = &exynos7_uic_attr,
> +       .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> +                                 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
> +                                 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> +                                 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
> +       .opts                   = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> +                                 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> +                                 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> +       .drv_init               = exynosauto_ufs_drv_init,
> +       .pre_link               = exynosauto_ufs_pre_link,
> +       .pre_pwr_change         = exynosauto_ufs_pre_pwr_change,
> +};
> +
>  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>         .uic_attr               = &exynos7_uic_attr,
>         .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> @@ -1330,6 +1425,8 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>  static const struct of_device_id exynos_ufs_of_match[] = {
>         { .compatible = "samsung,exynos7-ufs",
>           .data       = &exynos_ufs_drvs },
> +       { .compatible = "samsung,exynosautov9-ufs",
> +         .data       = &exynosauto_ufs_drvs },

This compatible is not documented. It seems that no one document
exynos7-ufs but that's not an excuse. :)

Best regards,
Krzysztof

RE: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Chanho Park]

> > +/* FSYS UFS Sharability */
> 
> Sharability -> Shareability

Typo. I'll correct it next patchset.

> 
> > +#define UFS_WR_SHARABLE                BIT(2)
> > +#define UFS_RD_SHARABLE                BIT(1)
> > +#define UFS_SHARABLE           (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
> > +#define UFS_SHARABILITY_OFFSET 0x710
> > +
> >  enum {
> >         UNIPRO_L1_5 = 0,/* PHY Adapter */
> >         UNIPRO_L2,      /* Data Link */
> > @@ -151,6 +158,80 @@ static int exynos7_ufs_drv_init(struct device *dev,
> struct exynos_ufs *ufs)
> >         return 0;
> >  }
> >
> > +static int exynosauto_ufs_drv_init(struct device *dev, struct
> > +exynos_ufs *ufs) {
> > +       struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
> > +
> > +       /* IO Coherency setting */
> > +       if (ufs->sysreg) {
> > +               return regmap_update_bits(ufs->sysreg,
> UFS_SHARABILITY_OFFSET,
> > +                                         UFS_SHARABLE, UFS_SHARABLE);
> > +       }
> > +
> > +       attr->tx_dif_p_nsec = 3200000;
> > +
> > +       return 0;
> > +}
> > +
> > +static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) {
> > +       struct ufs_hba *hba = ufs->hba;
> > +       int i;
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> > +       for_each_ufs_rx_lane(ufs, i) {
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
> > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
> > +       }
> > +
> > +       for_each_ufs_tx_lane(ufs, i) {
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
> > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
> > +       }
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
> > +
> > +       return 0;
> > +}
> > +
> > +static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> > +                                        struct ufs_pa_layer_attr
> > +*pwr) {
> > +       struct ufs_hba *hba = ufs->hba;
> > +
> > +       /* PACP_PWR_req and delivered to the remote DME */
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
> > +
> > +       return 0;
> > +}
> > +
> 
> No need for double line.

Will be fixed as well. :)

> 
> > +
> >  static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)  {
> >         struct ufs_hba *hba = ufs->hba; @@ -1305,6 +1386,20 @@ static
> > struct exynos_ufs_uic_attr exynos7_uic_attr = {
> >         .pa_dbg_option_suite            = 0x30103,
> >  };
> >
> > +static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
> > +       .uic_attr               = &exynos7_uic_attr,
> > +       .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > +                                 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
> > +                                 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> > +                                 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
> > +       .opts                   = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> > +                                 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> > +                                 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> > +       .drv_init               = exynosauto_ufs_drv_init,
> > +       .pre_link               = exynosauto_ufs_pre_link,
> > +       .pre_pwr_change         = exynosauto_ufs_pre_pwr_change,
> > +};
> > +
> >  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
> >         .uic_attr               = &exynos7_uic_attr,
> >         .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > @@ -1330,6 +1425,8 @@ static struct exynos_ufs_drv_data
> > exynos_ufs_drvs = {  static const struct of_device_id
> exynos_ufs_of_match[] = {
> >         { .compatible = "samsung,exynos7-ufs",
> >           .data       = &exynos_ufs_drvs },
> > +       { .compatible = "samsung,exynosautov9-ufs",
> > +         .data       = &exynosauto_ufs_drvs },
> 
> This compatible is not documented. It seems that no one document exynos7-
> ufs but that's not an excuse. :)

Hmm. Let me check whether I can add ufs-exynos.yaml.

Best Regards,
Chanho Park

RE: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 13 July 2021 16:28
> To: Chanho Park <chanho61.park@samsung.com>
> Cc: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>;
> Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> soc@vger.kernel.org; linux-scsi@vger.kernel.org
> Subject: Re: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs
> driver
> 
> -On Fri, 9 Jul 2021 at 08:59, Chanho Park <chanho61.park@samsung.com>
> wrote:
> >
> > This patch adds to support ufs variant for ExynosAuto v9 SoC. This
> > requires control UFS IP sharability register via syscon and regmap.
> > Regarding uic_attr, most of values can be shared with exynos7 except
> > tx_dif_p_nsec value.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> >  drivers/scsi/ufs/ufs-exynos.c | 97
> > +++++++++++++++++++++++++++++++++++
> >  1 file changed, 97 insertions(+)
> >
> > diff --git a/drivers/scsi/ufs/ufs-exynos.c
> > b/drivers/scsi/ufs/ufs-exynos.c index 9669afe8f1f4..82f915f7a447
> > 100644
> > --- a/drivers/scsi/ufs/ufs-exynos.c
> > +++ b/drivers/scsi/ufs/ufs-exynos.c
> > @@ -15,6 +15,7 @@
> >  #include <linux/mfd/syscon.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> >
> >  #include "ufshcd.h"
> >  #include "ufshcd-pltfrm.h"
> > @@ -76,6 +77,12 @@
> >                                  UIC_TRANSPORT_NO_CONNECTION_RX |\
> >                                  UIC_TRANSPORT_BAD_TC)
> >
> > +/* FSYS UFS Sharability */
> 
> Sharability -> Shareability
> 
> > +#define UFS_WR_SHARABLE                BIT(2)
> > +#define UFS_RD_SHARABLE                BIT(1)
> > +#define UFS_SHARABLE           (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
> > +#define UFS_SHARABILITY_OFFSET 0x710
> > +
> >  enum {
> >         UNIPRO_L1_5 = 0,/* PHY Adapter */
> >         UNIPRO_L2,      /* Data Link */
> > @@ -151,6 +158,80 @@ static int exynos7_ufs_drv_init(struct device *dev,
> struct exynos_ufs *ufs)
> >         return 0;
> >  }
> >
> > +static int exynosauto_ufs_drv_init(struct device *dev, struct
> > +exynos_ufs *ufs) {
> > +       struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
> > +
> > +       /* IO Coherency setting */
> > +       if (ufs->sysreg) {
> > +               return regmap_update_bits(ufs->sysreg,
> UFS_SHARABILITY_OFFSET,
> > +                                         UFS_SHARABLE, UFS_SHARABLE);
> > +       }
> > +
> > +       attr->tx_dif_p_nsec = 3200000;
> > +
> > +       return 0;
> > +}
> > +
> > +static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) {
> > +       struct ufs_hba *hba = ufs->hba;
> > +       int i;
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> > +       for_each_ufs_rx_lane(ufs, i) {
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
> > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
> > +       }
> > +
> > +       for_each_ufs_tx_lane(ufs, i) {
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
> > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
> > +
> > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
> > +       }
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
> 0x0);
> > +
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
> > +
> > +       return 0;
> > +}
> > +
> > +static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> > +                                        struct ufs_pa_layer_attr
> > +*pwr) {
> > +       struct ufs_hba *hba = ufs->hba;
> > +
> > +       /* PACP_PWR_req and delivered to the remote DME */
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
> 12000);
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
> 32000);
> > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
> 16000);
> > +
> > +       return 0;
> > +}
> > +
> 
> No need for double line.
> 
> > +
> >  static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)  {
> >         struct ufs_hba *hba = ufs->hba; @@ -1305,6 +1386,20 @@ static
> > struct exynos_ufs_uic_attr exynos7_uic_attr = {
> >         .pa_dbg_option_suite            = 0x30103,
> >  };
> >
> > +static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
> > +       .uic_attr               = &exynos7_uic_attr,
> > +       .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > +                                 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
> > +                                 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> > +                                 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
> > +       .opts                   = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> > +                                 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> > +                                 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> > +       .drv_init               = exynosauto_ufs_drv_init,
> > +       .pre_link               = exynosauto_ufs_pre_link,
> > +       .pre_pwr_change         = exynosauto_ufs_pre_pwr_change,
> > +};
> > +
> >  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
> >         .uic_attr               = &exynos7_uic_attr,
> >         .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > @@ -1330,6 +1425,8 @@ static struct exynos_ufs_drv_data
> > exynos_ufs_drvs = {  static const struct of_device_id
> exynos_ufs_of_match[] = {
> >         { .compatible = "samsung,exynos7-ufs",
> >           .data       = &exynos_ufs_drvs },
> > +       { .compatible = "samsung,exynosautov9-ufs",
> > +         .data       = &exynosauto_ufs_drvs },
> 
> This compatible is not documented. It seems that no one document
> exynos7-ufs but that's not an excuse. :)
> 
I was post along with UFS driver [1], had Rob's Reviewed-by as well, not sure why it is not merged. 
Let me ping Rob on this.
[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2176074.html

> Best regards,
> Krzysztof

RE: [PATCH 02/15] scsi: ufs: add quirk to enable host controller without interface configuration

[Alim Akhtar]

Hi Chanho

> -----Original Message-----
> From: Chanho Park <chanho61.park@samsung.com>
> Sent: 09 July 2021 12:27
> To: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>
> Cc: Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
> <chanho61.park@samsung.com>
> Subject: [PATCH 02/15] scsi: ufs: add quirk to enable host controller without
> interface configuration
> 
> From: jongmin jeong <jjmin.jeong@samsung.com>
> 
> samsung ExynosAuto SoC has two types of host controller interface to
> support the virtualization of UFS Device.
> One is the physical host(PH) that the same as conventaional UFSHCI, and the
> other is the virtual host(VH) that support data transfer function only.
> 
> In this structure, the virtual host does not support like device management.
> This patch skips the interface configuration part that cannot be performed in
> the virtual host.
> 
> Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/scsi/ufs/ufshcd.c | 3 +++
>  drivers/scsi/ufs/ufshcd.h | 6 ++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
> 9702086e9860..3451b335f2b4 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -7988,6 +7988,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba,
> bool async)
>  	if (ret)
>  		goto out;
> 
> +	if (hba->quirks &
> UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION)
> +		goto out;
> +
>  	/* Debug counters initialization */
>  	ufshcd_clear_dbg_ufs_stats(hba);
> 
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index
> e67b1fcfe1a2..fe523cbd68dd 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -573,6 +573,12 @@ enum ufshcd_quirks {
>  	 * support UIC command
>  	 */
>  	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller cannot
> +	 * support interface configuration.
> +	 */
> +	UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION	= 1 << 16,
May be UFSHCD_QUIRK_SKIP_PH_CONFIGURATION

>  };
> 
>  enum ufshcd_caps {
> --
> 2.32.0

RE: [PATCH 03/15] scsi: ufs: ufs-exynos: change pclk available max value

[Alim Akhtar]

Hi Chanho

> -----Original Message-----
> From: Chanho Park <chanho61.park@samsung.com>
> Sent: 09 July 2021 12:27
> To: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>
> Cc: Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
> <chanho61.park@samsung.com>
> Subject: [PATCH 03/15] scsi: ufs: ufs-exynos: change pclk available max value
> 
> To support 167MHz PCLK, we need to adjust the maximum value.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/scsi/ufs/ufs-exynos.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index 67505fe32ebf..475a5adf0f8b 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -99,7 +99,7 @@ struct exynos_ufs;
>  #define PA_HIBERN8TIME_VAL	0x20
> 
>  #define PCLK_AVAIL_MIN	70000000
> -#define PCLK_AVAIL_MAX	133000000
> +#define PCLK_AVAIL_MAX	167000000
> 
>  struct exynos_ufs_uic_attr {
>  	/* TX Attributes */
> --
> 2.32.0

RE: [PATCH 04/15] scsi: ufs: ufs-exynos: simplify drv_data retrieval

[Alim Akhtar]

Hi Chanho

> -----Original Message-----
> From: Chanho Park <chanho61.park@samsung.com>
> Sent: 09 July 2021 12:27
> To: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>
> Cc: Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
> <chanho61.park@samsung.com>
> Subject: [PATCH 04/15] scsi: ufs: ufs-exynos: simplify drv_data retrieval
> 
> The compatible field of exynos_ufs_drv_data is not necessary because
> of_device_id already has it. Thus, we don't need it anymore and we can get
> drv_data by device_get_match_data.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
This patch can independently go in as this is clean-up and simplification of the existing driver.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/scsi/ufs/ufs-exynos.c | 10 +---------  drivers/scsi/ufs/ufs-exynos.h |
> 3 +--
>  2 files changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index cf46d6f86e0e..db5892901cc0 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -893,17 +893,10 @@ static int exynos_ufs_post_link(struct ufs_hba
> *hba)  static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs
> *ufs)  {
>  	struct device_node *np = dev->of_node;
> -	struct exynos_ufs_drv_data *drv_data = &exynos_ufs_drvs;
>  	struct exynos_ufs_uic_attr *attr;
>  	int ret = 0;
> 
> -	while (drv_data->compatible) {
> -		if (of_device_is_compatible(np, drv_data->compatible)) {
> -			ufs->drv_data = drv_data;
> -			break;
> -		}
> -		drv_data++;
> -	}
> +	ufs->drv_data = device_get_match_data(dev);
> 
>  	if (ufs->drv_data && ufs->drv_data->uic_attr) {
>  		attr = ufs->drv_data->uic_attr;
> @@ -1258,7 +1251,6 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr
> = {  };
> 
>  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
> -	.compatible		= "samsung,exynos7-ufs",
>  	.uic_attr		= &exynos7_uic_attr,
>  	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
>  				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index 475a5adf0f8b..7bf2053f6e90 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -142,7 +142,6 @@ struct exynos_ufs_uic_attr {  };
> 
>  struct exynos_ufs_drv_data {
> -	char *compatible;
>  	struct exynos_ufs_uic_attr *uic_attr;
>  	unsigned int quirks;
>  	unsigned int opts;
> @@ -191,7 +190,7 @@ struct exynos_ufs {
>  	struct ufs_pa_layer_attr dev_req_params;
>  	struct ufs_phy_time_cfg t_cfg;
>  	ktime_t entry_hibern8_t;
> -	struct exynos_ufs_drv_data *drv_data;
> +	const struct exynos_ufs_drv_data *drv_data;
> 
>  	u32 opts;
>  #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
> --
> 2.32.0

RE: [PATCH 06/15] scsi: ufs: ufs-exynos: add refclkout_stop control

[Alim Akhtar]

Hi Chanho

> -----Original Message-----
> From: Chanho Park <chanho61.park@samsung.com>
> Sent: 09 July 2021 12:27
> To: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>
> Cc: Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
> <chanho61.park@samsung.com>
> Subject: [PATCH 06/15] scsi: ufs: ufs-exynos: add refclkout_stop control
> 
> This patch adds REFCLKOUT_STOP control to CLK_STOP_MASK. It can
> en/disable reference clock out control for UFS device.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/scsi/ufs/ufs-exynos.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index da02ad3b036c..78cc5bda0a1f 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -49,10 +49,11 @@
>  #define HCI_ERR_EN_T_LAYER	0x84
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
> +#define REFCLKOUT_STOP		BIT(4)
>  #define REFCLK_STOP		BIT(2)
>  #define UNIPRO_MCLK_STOP	BIT(1)
>  #define UNIPRO_PCLK_STOP	BIT(0)
> -#define CLK_STOP_MASK		(REFCLK_STOP |\
> +#define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
>  				 UNIPRO_MCLK_STOP |\
>  				 UNIPRO_PCLK_STOP)
>  #define HCI_MISC		0xB4
> --
> 2.32.0

RE: [PATCH 02/15] scsi: ufs: add quirk to enable host controller without interface configuration

[Chanho Park]

> > +	/*
> > +	 * This quirk needs to be enabled if the host controller cannot
> > +	 * support interface configuration.
> > +	 */
> > +	UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION	= 1 << 16,
> May be UFSHCD_QUIRK_SKIP_PH_CONFIGURATION

This can explain more specific meaning. I'll apply your review v2 patchset.
Thanks.

Best Regards,
Chanho Park

Re: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Rob Herring]

On Tue, Jul 13, 2021 at 8:58 PM Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzk@kernel.org>
> > Sent: 13 July 2021 16:28
> > To: Chanho Park <chanho61.park@samsung.com>
> > Cc: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley
> > <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com>;
> > Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
> > Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman
> > <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>;
> > Christoph Hellwig <hch@infradead.org>; Bart Van Assche
> > <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>;
> > Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung-
> > soc@vger.kernel.org; linux-scsi@vger.kernel.org
> > Subject: Re: [PATCH 13/15] scsi: ufs: ufs-exynos: support exynosauto v9 ufs
> > driver
> >
> > -On Fri, 9 Jul 2021 at 08:59, Chanho Park <chanho61.park@samsung.com>
> > wrote:
> > >
> > > This patch adds to support ufs variant for ExynosAuto v9 SoC. This
> > > requires control UFS IP sharability register via syscon and regmap.
> > > Regarding uic_attr, most of values can be shared with exynos7 except
> > > tx_dif_p_nsec value.
> > >
> > > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > > ---
> > >  drivers/scsi/ufs/ufs-exynos.c | 97
> > > +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 97 insertions(+)
> > >
> > > diff --git a/drivers/scsi/ufs/ufs-exynos.c
> > > b/drivers/scsi/ufs/ufs-exynos.c index 9669afe8f1f4..82f915f7a447
> > > 100644
> > > --- a/drivers/scsi/ufs/ufs-exynos.c
> > > +++ b/drivers/scsi/ufs/ufs-exynos.c
> > > @@ -15,6 +15,7 @@
> > >  #include <linux/mfd/syscon.h>
> > >  #include <linux/phy/phy.h>
> > >  #include <linux/platform_device.h>
> > > +#include <linux/regmap.h>
> > >
> > >  #include "ufshcd.h"
> > >  #include "ufshcd-pltfrm.h"
> > > @@ -76,6 +77,12 @@
> > >                                  UIC_TRANSPORT_NO_CONNECTION_RX |\
> > >                                  UIC_TRANSPORT_BAD_TC)
> > >
> > > +/* FSYS UFS Sharability */
> >
> > Sharability -> Shareability
> >
> > > +#define UFS_WR_SHARABLE                BIT(2)
> > > +#define UFS_RD_SHARABLE                BIT(1)
> > > +#define UFS_SHARABLE           (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
> > > +#define UFS_SHARABILITY_OFFSET 0x710
> > > +
> > >  enum {
> > >         UNIPRO_L1_5 = 0,/* PHY Adapter */
> > >         UNIPRO_L2,      /* Data Link */
> > > @@ -151,6 +158,80 @@ static int exynos7_ufs_drv_init(struct device *dev,
> > struct exynos_ufs *ufs)
> > >         return 0;
> > >  }
> > >
> > > +static int exynosauto_ufs_drv_init(struct device *dev, struct
> > > +exynos_ufs *ufs) {
> > > +       struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
> > > +
> > > +       /* IO Coherency setting */
> > > +       if (ufs->sysreg) {
> > > +               return regmap_update_bits(ufs->sysreg,
> > UFS_SHARABILITY_OFFSET,
> > > +                                         UFS_SHARABLE, UFS_SHARABLE);
> > > +       }
> > > +
> > > +       attr->tx_dif_p_nsec = 3200000;
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) {
> > > +       struct ufs_hba *hba = ufs->hba;
> > > +       int i;
> > > +
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> > > +       for_each_ufs_rx_lane(ufs, i) {
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
> > > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
> > > +
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > > +
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
> > > +
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
> > > +       }
> > > +
> > > +       for_each_ufs_tx_lane(ufs, i) {
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
> > > +                              DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
> > > +
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
> > > +
> > > +               ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
> > > +       }
> > > +
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> > > +
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
> > 0x0);
> > > +
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> > > +                                        struct ufs_pa_layer_attr
> > > +*pwr) {
> > > +       struct ufs_hba *hba = ufs->hba;
> > > +
> > > +       /* PACP_PWR_req and delivered to the remote DME */
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
> > 12000);
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
> > 32000);
> > > +       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
> > 16000);
> > > +
> > > +       return 0;
> > > +}
> > > +
> >
> > No need for double line.
> >
> > > +
> > >  static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)  {
> > >         struct ufs_hba *hba = ufs->hba; @@ -1305,6 +1386,20 @@ static
> > > struct exynos_ufs_uic_attr exynos7_uic_attr = {
> > >         .pa_dbg_option_suite            = 0x30103,
> > >  };
> > >
> > > +static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
> > > +       .uic_attr               = &exynos7_uic_attr,
> > > +       .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > > +                                 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
> > > +                                 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> > > +                                 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
> > > +       .opts                   = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> > > +                                 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> > > +                                 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> > > +       .drv_init               = exynosauto_ufs_drv_init,
> > > +       .pre_link               = exynosauto_ufs_pre_link,
> > > +       .pre_pwr_change         = exynosauto_ufs_pre_pwr_change,
> > > +};
> > > +
> > >  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
> > >         .uic_attr               = &exynos7_uic_attr,
> > >         .quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> > > @@ -1330,6 +1425,8 @@ static struct exynos_ufs_drv_data
> > > exynos_ufs_drvs = {  static const struct of_device_id
> > exynos_ufs_of_match[] = {
> > >         { .compatible = "samsung,exynos7-ufs",
> > >           .data       = &exynos_ufs_drvs },
> > > +       { .compatible = "samsung,exynosautov9-ufs",
> > > +         .data       = &exynosauto_ufs_drvs },
> >
> > This compatible is not documented. It seems that no one document
> > exynos7-ufs but that's not an excuse. :)
> >
> I was post along with UFS driver [1], had Rob's Reviewed-by as well, not sure why it is not merged.
> Let me ping Rob on this.
> [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2176074.html

The binding should have been applied with the driver. If you want me
to apply, resend it without my Reviewed-by tag.

Rob

Re: [PATCH 14/15] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Bean Huo]

On Fri, 2021-07-09 at 15:57 +0900, Chanho Park wrote:
> We divide this M-HCI as PH(Physical Host) and VHs(Virtual Host). The
> PH
> 
> supports all UFSHCI functions(all SAPs) same as conventional UFSHCI
> but
> 
> the VH only supports data transfer function. Thus, except UTP_CMD_SAP
> and
> 
> UTP_TMPSAP, the PH should handle all the physical features.

Hi Chanho park,

You mentioned this in your coverletter:

"There are two types of host controllers on the UFS host controller
that we designed. The UFS device has a Function Arbitor that arranges
commands of each host. When each host transmits a command to the
Arbitor, the Arbitor transmits it to the UTP layer".

where does this "Function Arbitor" exit? From your comments, seems it
exists on the UFS device side? right? If this is true, where is related
code in your patch?? Maybe you only submited partial of your real
driver parch for this controller??

Bean

RE: [PATCH 14/15] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Chanho Park]

> > We divide this M-HCI as PH(Physical Host) and VHs(Virtual Host). The
> > PH
> >
> > supports all UFSHCI functions(all SAPs) same as conventional UFSHCI
> > but
> >
> > the VH only supports data transfer function. Thus, except UTP_CMD_SAP
> > and
> >
> > UTP_TMPSAP, the PH should handle all the physical features.
> 
> Hi Chanho park,
> 
> You mentioned this in your coverletter:
> 
> "There are two types of host controllers on the UFS host controller that
> we designed. The UFS device has a Function Arbitor that arranges commands
> of each host. When each host transmits a command to the Arbitor, the
> Arbitor transmits it to the UTP layer".
> 
> where does this "Function Arbitor" exit? From your comments, seems it
> exists on the UFS device side? right? If this is true, where is related
> code in your patch??

The "Function Arbiter" is in our ufs controller as H/W and it is responsible to arrange UTP_CMD/UTP_TM among PH and VHs. When we set MHCTL register, the controller will enable the multi-host capability and the arbiter will be automatically enabled as well.

+static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	/* Enable Virtual Host #1 */
+	ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
+	/* Default VH Transfer permissions */
+	hci_writel(ufs, 0x03FFE1FE, HCI_MH_ALLOWABLE_TRAN_OF_VH);
+	/* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
+	hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
+
+	return 0;
+}

> Maybe you only submited partial of your real driver
> parch for this controller??

Yes. The series is the initial version but it contains most of multi-host capabilities. Most of things can be handled by our UFS controller so we can make driver code simpler as much as possible. Only #1 VH can be supported in this patch at the moment but I have a plan to support more VHs later.

Best Regards,
Chanho Park