From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB57FC07E9C for ; Mon, 12 Jul 2021 19:22:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADDA1610FA for ; Mon, 12 Jul 2021 19:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236341AbhGLTZA (ORCPT ); Mon, 12 Jul 2021 15:25:00 -0400 Received: from mail-io1-f48.google.com ([209.85.166.48]:38403 "EHLO mail-io1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233793AbhGLTY7 (ORCPT ); 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Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id j24sm3350224ioo.16.2021.07.12.12.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: (nullmailer pid 2333729 invoked by uid 1000); Mon, 12 Jul 2021 19:22:07 -0000 Date: Mon, 12 Jul 2021 13:22:07 -0600 From: Rob Herring To: Anup Patel Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bin Meng Subject: Re: [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Message-ID: <20210712192207.GA2322460@robh.at.kernel.org> References: <20210618123851.1344518-1-anup.patel@wdc.com> <20210618123851.1344518-7-anup.patel@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210618123851.1344518-7-anup.patel@wdc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: > We add DT bindings documentation for the ACLINT MSWI and SSWI > devices found on RISC-V SOCs. > > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > --- > .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > new file mode 100644 > index 000000000000..b74025542866 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V ACLINT Software Interrupt Devices > + > +maintainers: > + - Anup Patel > + > +description: > + RISC-V SOCs include an implementation of the M-level software interrupt > + (MSWI) device and the S-level software interrupt (SSWI) device defined > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. > + > + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT > + specification located at > + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > + > + The ACLINT MSWI and SSWI devices directly connect to the M-level and > + S-level software interrupt lines of various HARTs (or CPUs) respectively > + so the RISC-V per-HART (or per-CPU) local interrupt controller is the > + parent interrupt controller for the ACLINT MSWI and SSWI devices. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - riscv,aclint-mswi > + - riscv,aclint-sswi > + > + description: > + Should be ",-aclint-mswi" and "riscv,aclint-mswi" OR > + ",-aclint-sswi" and "riscv,aclint-sswi". The schema doesn't match the description. There's no actual vendor implementation yet? You could do: items: - {} - const: riscv,aclint-mswi But then your example will fail. > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 0 > + > + interrupts-extended: > + minItems: 1 You need maxItems too. I guess this based on number of cores, so just pick a 'should be enough' value. > + > + interrupt-controller: true > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-controller > + - "#interrupt-cells" > + > +examples: > + - | > + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): > + > + interrupt-controller@2000000 { > + compatible = "riscv,aclint-mswi"; > + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; > + reg = <0x2000000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > + > + - | > + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): > + > + interrupt-controller@2100000 { > + compatible = "riscv,aclint-sswi"; > + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; Same here. > + reg = <0x2100000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > +... > -- > 2.25.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA367C07E99 for ; Mon, 12 Jul 2021 19:22:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A391E610FA for ; Mon, 12 Jul 2021 19:22:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A391E610FA Authentication-Results: mail.kernel.org; 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Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id j24sm3350224ioo.16.2021.07.12.12.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: (nullmailer pid 2333729 invoked by uid 1000); Mon, 12 Jul 2021 19:22:07 -0000 Date: Mon, 12 Jul 2021 13:22:07 -0600 From: Rob Herring To: Anup Patel Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bin Meng Subject: Re: [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Message-ID: <20210712192207.GA2322460@robh.at.kernel.org> References: <20210618123851.1344518-1-anup.patel@wdc.com> <20210618123851.1344518-7-anup.patel@wdc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210618123851.1344518-7-anup.patel@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210712_122215_290787_147F561D X-CRM114-Status: GOOD ( 23.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: > We add DT bindings documentation for the ACLINT MSWI and SSWI > devices found on RISC-V SOCs. > > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > --- > .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > new file mode 100644 > index 000000000000..b74025542866 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V ACLINT Software Interrupt Devices > + > +maintainers: > + - Anup Patel > + > +description: > + RISC-V SOCs include an implementation of the M-level software interrupt > + (MSWI) device and the S-level software interrupt (SSWI) device defined > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. > + > + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT > + specification located at > + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > + > + The ACLINT MSWI and SSWI devices directly connect to the M-level and > + S-level software interrupt lines of various HARTs (or CPUs) respectively > + so the RISC-V per-HART (or per-CPU) local interrupt controller is the > + parent interrupt controller for the ACLINT MSWI and SSWI devices. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - riscv,aclint-mswi > + - riscv,aclint-sswi > + > + description: > + Should be ",-aclint-mswi" and "riscv,aclint-mswi" OR > + ",-aclint-sswi" and "riscv,aclint-sswi". The schema doesn't match the description. There's no actual vendor implementation yet? You could do: items: - {} - const: riscv,aclint-mswi But then your example will fail. > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 0 > + > + interrupts-extended: > + minItems: 1 You need maxItems too. I guess this based on number of cores, so just pick a 'should be enough' value. > + > + interrupt-controller: true > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-controller > + - "#interrupt-cells" > + > +examples: > + - | > + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): > + > + interrupt-controller@2000000 { > + compatible = "riscv,aclint-mswi"; > + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; > + reg = <0x2000000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > + > + - | > + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): > + > + interrupt-controller@2100000 { > + compatible = "riscv,aclint-sswi"; > + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; Same here. > + reg = <0x2100000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > +... > -- > 2.25.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv