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From: Yang Weijiang <weijiang.yang@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Yang Weijiang <weijiang.yang@intel.com>,
	pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com,
	wei.w.wang@intel.com, like.xu.linux@gmail.com,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state
Date: Tue, 13 Jul 2021 17:47:13 +0800	[thread overview]
Message-ID: <20210713094713.GB13824@intel.com> (raw)
In-Reply-To: <CALMp9eQLHfXQwPCfqtc_y34sKGkZsCxEFL+BGx8wHgz7A8cOPA@mail.gmail.com>

On Mon, Jul 12, 2021 at 10:23:02AM -0700, Jim Mattson wrote:
> On Mon, Jul 12, 2021 at 2:36 AM Yang Weijiang <weijiang.yang@intel.com> wrote:
> >
> > On Fri, Jul 09, 2021 at 03:54:53PM -0700, Jim Mattson wrote:
> > > On Fri, Jul 9, 2021 at 2:51 AM Yang Weijiang <weijiang.yang@intel.com> wrote:
> > > >
> > > > If host is using MSR_ARCH_LBR_CTL then save it before vm-entry
> > > > and reload it after vm-exit.
> > >
> > > I don't see anything being done here "before VM-entry" or "after
> > > VM-exit." This code seems to be invoked on vcpu_load and vcpu_put.
> > >
> > > In any case, I don't see why this one MSR is special. It seems that if
> > > the host is using the architectural LBR MSRs, then *all* of the host
> > > architectural LBR MSRs have to be saved on vcpu_load and restored on
> > > vcpu_put. Shouldn't  kvm_load_guest_fpu() and kvm_put_guest_fpu() do
> > > that via the calls to kvm_save_current_fpu(vcpu->arch.user_fpu) and
> > > restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state)?
> > I looked back on the discussion thread:
> > https://patchwork.kernel.org/project/kvm/patch/20210303135756.1546253-8-like.xu@linux.intel.com/
> > not sure why this code is added, but IMO, although fpu save/restore in outer loop
> > covers this LBR MSR, but the operation points are far away from vm-entry/exit
> > point, i.e., the guest MSR setting could leak to host side for a signicant
> > long of time, it may cause host side profiling accuracy. if we save/restore it
> > manually, it'll mitigate the issue signifcantly.
> 
> I'll be interested to see how you distinguish the intermingled branch
> streams, if you allow the host to record LBRs while the LBR MSRs
> contain guest values!
I'll check if an inner simplified xsave/restore to guest/host LBR MSRs is meaningful,
the worst case is to drop this patch since it's not correct to only enable host lbr ctl
while still leaves guest LBR data in the MSRs. Thanks for the reminder!


  reply	other threads:[~2021-07-13  9:33 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-09 10:04 [PATCH v5 00/13] Introduce Architectural LBR for vPMU Yang Weijiang
2021-07-09 10:04 ` [PATCH v5 01/13] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 02/13] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 03/13] KVM: x86: Add arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-07-09 18:24   ` Jim Mattson
2021-07-12  8:55     ` Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 04/13] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-07-09 20:35   ` Jim Mattson
2021-07-12  9:17     ` Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 05/13] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-07-09 21:55   ` Jim Mattson
2021-07-12  9:36     ` Yang Weijiang
2021-07-12 10:10       ` Like Xu
2021-07-13  9:05         ` Yang Weijiang
2021-07-10  0:42   ` kernel test robot
2021-07-10  0:42     ` kernel test robot
2021-07-09 10:05 ` [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state Yang Weijiang
2021-07-09 22:54   ` Jim Mattson
2021-07-09 23:41     ` Jim Mattson
2021-07-12  9:53       ` Yang Weijiang
2021-07-12 10:19         ` Like Xu
2021-07-12 17:20           ` Jim Mattson
2021-07-12 17:45             ` Jim Mattson
2021-07-13  9:49               ` Like Xu
2021-07-13 17:00                 ` Jim Mattson
2021-07-14 13:33                   ` Like Xu
2021-07-14 16:15                     ` Jim Mattson
2021-07-13  9:53             ` Yang Weijiang
2021-07-12  9:50     ` Yang Weijiang
2021-07-12 17:23       ` Jim Mattson
2021-07-13  9:47         ` Yang Weijiang [this message]
2021-07-13 10:16           ` Like Xu
2021-07-13 17:12             ` Jim Mattson
2021-07-14 13:55               ` Like Xu
2021-07-09 10:05 ` [PATCH v5 07/13] KVM: x86/pmu: Refactor code to support guest Arch LBR Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 08/13] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 09/13] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 10/13] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 11/13] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 12/13] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 13/13] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang

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