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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI v4 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
Date: Tue, 13 Jul 2021 12:36:31 -0700	[thread overview]
Message-ID: <20210713193635.3390052-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210713193635.3390052-1-matthew.d.roper@intel.com>

Switch JSL/EHL to use a revid->stepping table as we're trying to do on
all platforms going forward.

v2:
 - Use COMMON_STEP().  (Anusha)

Bspec: 29153
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 9 ++++-----
 drivers/gpu/drm/i915/intel_step.c             | 8 ++++++++
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 882bfd499e55..dfc31b682848 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2674,7 +2674,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->dpll.ref_clks.nssc == 38400;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 478c3c8602c1..0cab641de40f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1050,7 +1050,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
+	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4f705f06c73..b3ce2b73a143 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_GT_STEP(p, since, until) \
 	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
 
-#define EHL_REVID_A0            0x0
-#define EHL_REVID_B0            0x1
-
-#define IS_JSL_EHL_REVID(p, since, until) \
-	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 9ce032993a99..9de17bdfe62f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
 	[7] = { COMMON_STEP(D0) },
 };
 
+static const struct intel_step_info jsl_ehl_revids[] = {
+	[0] = { COMMON_STEP(A0) },
+	[1] = { COMMON_STEP(B0) },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -104,6 +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_JSL_EHL(i915)) {
+		revids = jsl_ehl_revids;
+		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
 		revids = icl_revids;
 		size = ARRAY_SIZE(icl_revids);
-- 
2.25.4

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  parent reply	other threads:[~2021-07-13 19:36 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 19:36 [Intel-gfx] [CI v4 00/12] Minor revid/stepping and workaround cleanup Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 01/12] drm/i915/step: s/<platform>_revid_tbl/<platform>_revids Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 02/12] drm/i915: Make pre-production detection use direct revid comparison Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 03/12] drm/i915/skl: Use revid->stepping tables Matt Roper
2021-07-13 20:03   ` Lucas De Marchi
2021-07-13 19:36 ` [Intel-gfx] [CI v4 04/12] drm/i915/kbl: Drop pre-production revision from stepping table Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 05/12] drm/i915/bxt: Use revid->stepping tables Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 06/12] drm/i915/glk: " Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 07/12] drm/i915/icl: " Matt Roper
2021-07-13 19:36 ` Matt Roper [this message]
2021-07-13 19:36 ` [Intel-gfx] [CI v4 09/12] drm/i915/rkl: " Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 10/12] drm/i915/dg1: " Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 11/12] drm/i915/cnl: Drop all workarounds Matt Roper
2021-07-13 19:36 ` [Intel-gfx] [CI v4 12/12] drm/i915/icl: Drop workarounds that only apply to pre-production steppings Matt Roper
2021-07-13 22:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Minor revid/stepping and workaround cleanup (rev5) Patchwork
2021-07-13 22:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-14  8:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-15  1:10   ` Matt Roper

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