[PATCH 0/6] uniphier: Add PCIe host controller and Akebi96 board support

[PATCH 0/6] uniphier: Add PCIe host controller and Akebi96 board support

[Kunihiko Hayashi]

This series adds PCI-express host controller support for UniPhier SoCs.
This also adds clock, reset, and phy support to enable the controller.

The controller is based on DW PCIe IP, however, the controller doesn't
have unroll version of iATU, so this series doesn't apply common DW
functions yet.

And this series includes Akebi96 board (96boards) support that has
UniPhier LD20 SoC and PCIe interface. The controller is available for
LD20 and PXs3 SoCs, and the devicetree already supports it.

Kunihiko Hayashi (6):
  clk: uniphier: Add PCIe clock entry
  reset: uniphier: Add PCIe reset entry
  phy: socionext: Add UniPhier PCIe PHY driver
  pci: uniphier: Add UniPhier PCIe controller driver
  configs: uniphier: Enable CONFIG_SYS_PCI_64BIT
  ARM: dts: uniphier: Add support for Akebi96

 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/uniphier-ld20-akebi96.dts    | 189 +++++++++++++
 drivers/Kconfig                           |   2 +
 drivers/Makefile                          |   1 +
 drivers/clk/uniphier/clk-uniphier-sys.c   |   3 +
 drivers/pci/Kconfig                       |  10 +
 drivers/pci/Makefile                      |   1 +
 drivers/pci/pcie_uniphier.c               | 424 ++++++++++++++++++++++++++++++
 drivers/phy/socionext/Kconfig             |  12 +
 drivers/phy/socionext/Makefile            |   6 +
 drivers/phy/socionext/phy-uniphier-pcie.c |  59 +++++
 drivers/reset/reset-uniphier.c            |   3 +
 include/configs/uniphier.h                |   2 +
 13 files changed, 713 insertions(+)
 create mode 100644 arch/arm/dts/uniphier-ld20-akebi96.dts
 create mode 100644 drivers/pci/pcie_uniphier.c
 create mode 100644 drivers/phy/socionext/Kconfig
 create mode 100644 drivers/phy/socionext/Makefile
 create mode 100644 drivers/phy/socionext/phy-uniphier-pcie.c

-- 
2.7.4

[PATCH 1/6] clk: uniphier: Add PCIe clock entry

[Kunihiko Hayashi]

Add clock control for PCIe controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index c627a4b..ff5d364 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -29,6 +29,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19),	/* usb30-phy (PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20),	/* usb31-phy (PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2),	/* pcie (Pro5) */
 	{ /* sentinel */ }
 #endif
 };
@@ -43,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),	/* usb30 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13),	/* usb30-phy1 (LD20) */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4),	/* pcie */
 	{ /* sentinel */ }
 #endif
 };
@@ -62,6 +64,7 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20),	/* usb30-phy2 */
 	UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17),	/* usb31-phy0 */
 	UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19),	/* usb31-phy1 */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 3),	/* pcie */
 	{ /* sentinel */ }
 #endif
 };
-- 
2.7.4

[PATCH 2/6] reset: uniphier: Add PCIe reset entry

[Kunihiko Hayashi]

Add reset control for PCIe controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/reset/reset-uniphier.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 2694d13..c5af995 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -50,6 +50,7 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
 	UNIPHIER_RESETX(12, 0x2000, 6),		/* GIO */
 	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
 	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
+	UNIPHIER_RESETX(24, 0x2008, 2),		/* PCIE */
 	UNIPHIER_RESET_END,
 };
 
@@ -79,6 +80,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
 	UNIPHIER_RESETX(17, 0x200c, 13),	/* USB30-PHY1 */
 	UNIPHIER_RESETX(18, 0x200c, 14),	/* USB30-PHY2 */
 	UNIPHIER_RESETX(19, 0x200c, 15),	/* USB30-PHY3 */
+	UNIPHIER_RESETX(24, 0x200c, 4),		/* PCIE */
 	UNIPHIER_RESET_END,
 };
 
@@ -95,6 +97,7 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
 	UNIPHIER_RESETX(18, 0x200c, 20),	/* USB30-PHY2 */
 	UNIPHIER_RESETX(20, 0x200c, 17),	/* USB31-PHY0 */
 	UNIPHIER_RESETX(21, 0x200c, 19),	/* USB31-PHY1 */
+	UNIPHIER_RESETX(24, 0x200c, 3),		/* PCIE */
 	UNIPHIER_RESET_END,
 };
 
-- 
2.7.4

[PATCH 3/6] phy: socionext: Add UniPhier PCIe PHY driver

[Kunihiko Hayashi]

Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/Kconfig                           |  2 ++
 drivers/Makefile                          |  1 +
 drivers/phy/socionext/Kconfig             | 12 +++++++
 drivers/phy/socionext/Makefile            |  6 ++++
 drivers/phy/socionext/phy-uniphier-pcie.c | 59 +++++++++++++++++++++++++++++++
 5 files changed, 80 insertions(+)
 create mode 100644 drivers/phy/socionext/Kconfig
 create mode 100644 drivers/phy/socionext/Makefile
 create mode 100644 drivers/phy/socionext/phy-uniphier-pcie.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index b1ada1c..c9c812b 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -80,6 +80,8 @@ source "drivers/phy/allwinner/Kconfig"
 
 source "drivers/phy/marvell/Kconfig"
 
+source "drivers/phy/socionext/Kconfig"
+
 source "drivers/pinctrl/Kconfig"
 
 source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 3510dab..4081289 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -96,6 +96,7 @@ obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/
 obj-y += phy/rockchip/
+obj-y += phy/socionext/
 obj-y += rtc/
 obj-y += scsi/
 obj-y += sound/
diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig
new file mode 100644
index 0000000..bcd579e
--- /dev/null
+++ b/drivers/phy/socionext/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# PHY drivers for Socionext platforms.
+#
+
+config PHY_UNIPHIER_PCIE
+	bool "UniPhier PCIe PHY driver"
+	depends on PHY && ARCH_UNIPHIER
+	imply REGMAP
+	help
+	  Enable this to support PHY implemented in PCIe controller
+	  on UniPhier SoCs.
diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile
new file mode 100644
index 0000000..5484360
--- /dev/null
+++ b/drivers/phy/socionext/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the phy drivers.
+#
+
+obj-$(CONFIG_PHY_UNIPHIER_PCIE)	+= phy-uniphier-pcie.o
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
new file mode 100644
index 0000000..d352c4c
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * phy_uniphier_pcie.c - Socionext UniPhier PCIe PHY driver
+ * Copyright 2019-2021 Socionext, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <regmap.h>
+#include <syscon.h>
+
+/* SG */
+#define SG_USBPCIESEL		0x590
+#define SG_USBPCIESEL_PCIE	BIT(0)
+
+struct uniphier_pciephy_priv {
+	int dummy;
+};
+
+static int uniphier_pciephy_init(struct phy *phy)
+{
+	return 0;
+}
+
+static int uniphier_pciephy_probe(struct udevice *dev)
+{
+	struct regmap *regmap;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev,
+						 "socionext,syscon");
+	if (!IS_ERR(regmap))
+		regmap_update_bits(regmap, SG_USBPCIESEL,
+				   SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
+
+	return 0;
+}
+
+static struct phy_ops uniphier_pciephy_ops = {
+	.init = uniphier_pciephy_init,
+};
+
+static const struct udevice_id uniphier_pciephy_ids[] = {
+	{ .compatible = "socionext,uniphier-pro5-pcie-phy" },
+	{ .compatible = "socionext,uniphier-ld20-pcie-phy" },
+	{ .compatible = "socionext,uniphier-pxs3-pcie-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(uniphier_pcie_phy) = {
+	.name		= "uniphier-pcie-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= uniphier_pciephy_ids,
+	.ops		= &uniphier_pciephy_ops,
+	.probe		= uniphier_pciephy_probe,
+	.priv_auto      = sizeof(struct uniphier_pciephy_priv),
+};
-- 
2.7.4

[PATCH 4/6] pci: uniphier: Add UniPhier PCIe controller driver

[Kunihiko Hayashi]

Add PCIe driver for UniPhier SoCs. This PCIe controller is based on
Synopsys DesignWare Core IP.

This version doesn't apply common DW functions because supported
controller doesn't have unroll version of iATU.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/pci/Kconfig         |  10 ++
 drivers/pci/Makefile        |   1 +
 drivers/pci/pcie_uniphier.c | 424 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/pci/pcie_uniphier.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b2b7b25..6b35455 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -328,4 +328,14 @@ config PCI_BRCMSTB
 	  on Broadcom set-top-box (STB) SoCs.
 	  This driver currently supports only BCM2711 SoC and RC mode
 	  of the controller.
+
+config PCIE_UNIPHIER
+	bool "Socionext UniPhier PCIe driver"
+	depends on DM_PCI
+	depends on ARCH_UNIPHIER
+	select PHY_UNIPHIER_PCIE
+	help
+	  Say Y here if you want to enable PCIe controller support on
+	  UniPhier SoCs.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c742bb2..73dee64 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
 obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
+obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
diff --git a/drivers/pci/pcie_uniphier.c b/drivers/pci/pcie_uniphier.c
new file mode 100644
index 0000000..f2edea9
--- /dev/null
+++ b/drivers/pci/pcie_uniphier.c
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pcie_uniphier.c - Socionext UniPhier PCIe driver
+ * Copyright 2019-2021 Socionext, Inc.
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <pci.h>
+#include <reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DBI registers */
+#define PCIE_LINK_STATUS_REG		0x0080
+#define PCIE_LINK_STATUS_WIDTH_MASK	GENMASK(25, 20)
+#define PCIE_LINK_STATUS_SPEED_MASK	GENMASK(19, 16)
+
+#define PCIE_MISC_CONTROL_1_OFF		0x08BC
+#define PCIE_DBI_RO_WR_EN		BIT(0)
+
+/* DBI iATU registers */
+#define PCIE_ATU_VIEWPORT		0x0900
+#define PCIE_ATU_REGION_INBOUND		BIT(31)
+#define PCIE_ATU_REGION_OUTBOUND	0
+#define PCIE_ATU_REGION_INDEX_MASK	GENMASK(3, 0)
+
+#define PCIE_ATU_CR1			0x0904
+#define PCIE_ATU_TYPE_MEM		0
+#define PCIE_ATU_TYPE_IO		2
+#define PCIE_ATU_TYPE_CFG0		4
+#define PCIE_ATU_TYPE_CFG1		5
+
+#define PCIE_ATU_CR2			0x0908
+#define PCIE_ATU_ENABLE			BIT(31)
+#define PCIE_ATU_MATCH_MODE		BIT(30)
+#define PCIE_ATU_BAR_NUM_MASK		GENMASK(10, 8)
+
+#define PCIE_ATU_LOWER_BASE		0x090C
+#define PCIE_ATU_UPPER_BASE		0x0910
+#define PCIE_ATU_LIMIT			0x0914
+#define PCIE_ATU_LOWER_TARGET		0x0918
+#define PCIE_ATU_BUS(x)			FIELD_PREP(GENMASK(31, 24), x)
+#define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
+#define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
+#define PCIE_ATU_UPPER_TARGET		0x091C
+
+/* Link Glue registers */
+#define PCL_PINCTRL0			0x002c
+#define PCL_PERST_PLDN_REGEN		BIT(12)
+#define PCL_PERST_NOE_REGEN		BIT(11)
+#define PCL_PERST_OUT_REGEN		BIT(8)
+#define PCL_PERST_PLDN_REGVAL		BIT(4)
+#define PCL_PERST_NOE_REGVAL		BIT(3)
+#define PCL_PERST_OUT_REGVAL		BIT(0)
+
+#define PCL_MODE			0x8000
+#define PCL_MODE_REGEN			BIT(8)
+#define PCL_MODE_REGVAL			BIT(0)
+
+#define PCL_APP_READY_CTRL		0x8008
+#define PCL_APP_LTSSM_ENABLE		BIT(0)
+
+#define PCL_APP_PM0			0x8078
+#define PCL_SYS_AUX_PWR_DET		BIT(8)
+
+#define PCL_STATUS_LINK			0x8140
+#define PCL_RDLH_LINK_UP		BIT(1)
+#define PCL_XMLH_LINK_UP		BIT(0)
+
+#define LINK_UP_TIMEOUT_MS		100
+
+struct uniphier_pcie_priv {
+	void *base;
+	void *dbi_base;
+	void *cfg_base;
+	fdt_size_t cfg_size;
+	struct fdt_resource link_res;
+	struct fdt_resource dbi_res;
+	struct fdt_resource cfg_res;
+
+	struct clk clk;
+	struct reset_ctl rst;
+	struct phy phy;
+
+	struct pci_region io;
+	struct pci_region mem;
+};
+
+static int pcie_dw_get_link_speed(struct uniphier_pcie_priv *priv)
+{
+	u32 val = readl(priv->dbi_base + PCIE_LINK_STATUS_REG);
+
+	return FIELD_GET(PCIE_LINK_STATUS_SPEED_MASK, val);
+}
+
+static int pcie_dw_get_link_width(struct uniphier_pcie_priv *priv)
+{
+	u32 val = readl(priv->dbi_base + PCIE_LINK_STATUS_REG);
+
+	return FIELD_GET(PCIE_LINK_STATUS_WIDTH_MASK, val);
+}
+
+static void pcie_dw_prog_outbound_atu(struct uniphier_pcie_priv *priv,
+				      int index, int type, u64 cpu_addr,
+				      u64 pci_addr, u32 size)
+{
+	writel(PCIE_ATU_REGION_OUTBOUND
+	       | FIELD_PREP(PCIE_ATU_REGION_INDEX_MASK, index),
+	       priv->dbi_base + PCIE_ATU_VIEWPORT);
+	writel(lower_32_bits(cpu_addr),
+	       priv->dbi_base + PCIE_ATU_LOWER_BASE);
+	writel(upper_32_bits(cpu_addr),
+	       priv->dbi_base + PCIE_ATU_UPPER_BASE);
+	writel(lower_32_bits(cpu_addr + size - 1),
+	       priv->dbi_base + PCIE_ATU_LIMIT);
+	writel(lower_32_bits(pci_addr),
+	       priv->dbi_base + PCIE_ATU_LOWER_TARGET);
+	writel(upper_32_bits(pci_addr),
+	       priv->dbi_base + PCIE_ATU_UPPER_TARGET);
+
+	writel(type, priv->dbi_base + PCIE_ATU_CR1);
+	writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
+}
+
+static int uniphier_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+	/* accept only device {0,1} on first bus */
+	if ((PCI_BUS(bdf) != first_busno) || (PCI_DEV(bdf) > 1))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int uniphier_pcie_conf_address(const struct udevice *dev, pci_dev_t bdf,
+				      uint offset, void **paddr)
+{
+	struct uniphier_pcie_priv *priv = dev_get_priv(dev);
+	u32 busdev;
+	int seq = dev_seq(dev);
+	int ret;
+
+	ret = uniphier_pcie_addr_valid(bdf, seq);
+	if (ret)
+		return ret;
+
+	if ((PCI_BUS(bdf) == seq) && !PCI_DEV(bdf)) {
+		*paddr = (void *)(priv->dbi_base + offset);
+		return 0;
+	}
+
+	busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - seq)
+		| PCIE_ATU_DEV(PCI_DEV(bdf))
+		| PCIE_ATU_FUNC(PCI_FUNC(bdf));
+
+	pcie_dw_prog_outbound_atu(priv, 0,
+				  PCIE_ATU_TYPE_CFG0, (u64)priv->cfg_base,
+				  busdev, priv->cfg_size);
+	*paddr = (void *)(priv->cfg_base + offset);
+
+	return 0;
+}
+
+static int uniphier_pcie_read_config(const struct udevice *dev, pci_dev_t bdf,
+				     uint offset, ulong *valp,
+				     enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(dev, uniphier_pcie_conf_address,
+					    bdf, offset, valp, size);
+}
+
+static int uniphier_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
+				      uint offset, ulong val,
+				      enum pci_size_t size)
+{
+	return pci_generic_mmap_write_config(dev, uniphier_pcie_conf_address,
+					     bdf, offset, val, size);
+}
+
+static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
+				       bool enable)
+{
+	u32 val;
+
+	val = readl(priv->base + PCL_APP_READY_CTRL);
+	if (enable)
+		val |= PCL_APP_LTSSM_ENABLE;
+	else
+		val &= ~PCL_APP_LTSSM_ENABLE;
+	writel(val, priv->base + PCL_APP_READY_CTRL);
+}
+
+static int uniphier_pcie_link_up(struct uniphier_pcie_priv *priv)
+{
+	u32 val, mask;
+
+	val = readl(priv->base + PCL_STATUS_LINK);
+	mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
+
+	return (val & mask) == mask;
+}
+
+static int uniphier_pcie_wait_link(struct uniphier_pcie_priv *priv)
+{
+	unsigned long timeout;
+
+	timeout = get_timer(0) + LINK_UP_TIMEOUT_MS;
+
+	while (get_timer(0) < timeout) {
+		if (uniphier_pcie_link_up(priv))
+			return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int uniphier_pcie_establish_link(struct uniphier_pcie_priv *priv)
+{
+	if (uniphier_pcie_link_up(priv))
+		return 0;
+
+	uniphier_pcie_ltssm_enable(priv, true);
+
+	return uniphier_pcie_wait_link(priv);
+}
+
+static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
+{
+	u32 val;
+
+	/* set RC mode */
+	val = readl(priv->base + PCL_MODE);
+	val |= PCL_MODE_REGEN;
+	val &= ~PCL_MODE_REGVAL;
+	writel(val, priv->base + PCL_MODE);
+
+	/* use auxiliary power detection */
+	val = readl(priv->base + PCL_APP_PM0);
+	val |= PCL_SYS_AUX_PWR_DET;
+	writel(val, priv->base + PCL_APP_PM0);
+
+	/* assert PERST# */
+	val = readl(priv->base + PCL_PINCTRL0);
+	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
+		 | PCL_PERST_PLDN_REGVAL);
+	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
+		| PCL_PERST_PLDN_REGEN;
+	writel(val, priv->base + PCL_PINCTRL0);
+
+	uniphier_pcie_ltssm_enable(priv, false);
+
+	mdelay(100);
+
+	/* deassert PERST# */
+	val = readl(priv->base + PCL_PINCTRL0);
+	val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
+	writel(val, priv->base + PCL_PINCTRL0);
+}
+
+static void uniphier_pcie_setup_rc(struct uniphier_pcie_priv *priv,
+				   struct pci_controller *hose)
+{
+	/* Store the IO and MEM windows settings for future use by the ATU */
+	priv->io.phys_start  = hose->regions[0].phys_start; /* IO base */
+	priv->io.bus_start   = hose->regions[0].bus_start;  /* IO_bus_addr */
+	priv->io.size	     = hose->regions[0].size;	    /* IO size */
+	priv->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+	priv->mem.bus_start  = hose->regions[1].bus_start;  /* MEM_bus_addr */
+	priv->mem.size	     = hose->regions[1].size;	    /* MEM size */
+
+	/* outbound: IO */
+	pcie_dw_prog_outbound_atu(priv, 0,
+				  PCIE_ATU_TYPE_IO, priv->io.phys_start,
+				  priv->io.bus_start, priv->io.size);
+
+	/* outbound: MEM */
+	pcie_dw_prog_outbound_atu(priv, 1,
+				  PCIE_ATU_TYPE_MEM, priv->mem.phys_start,
+				  priv->mem.bus_start, priv->mem.size);
+}
+
+static int uniphier_pcie_probe(struct udevice *dev)
+{
+	struct uniphier_pcie_priv *priv = dev_get_priv(dev);
+	struct udevice *ctlr = pci_get_controller(dev);
+	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+	int ret;
+
+	priv->base = map_physmem(priv->link_res.start,
+				 fdt_resource_size(&priv->link_res),
+				 MAP_NOCACHE);
+	priv->dbi_base = map_physmem(priv->dbi_res.start,
+				     fdt_resource_size(&priv->dbi_res),
+				     MAP_NOCACHE);
+	priv->cfg_size = fdt_resource_size(&priv->cfg_res);
+	priv->cfg_base = map_physmem(priv->cfg_res.start,
+				     priv->cfg_size, MAP_NOCACHE);
+
+	ret = clk_enable(&priv->clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable clk: %d\n", ret);
+		return ret;
+	}
+	ret = reset_deassert(&priv->rst);
+	if (ret) {
+		dev_err(dev, "Failed to deassert reset: %d\n", ret);
+		goto out_clk_release;
+	}
+
+	ret = generic_phy_init(&priv->phy);
+	if (ret) {
+		dev_err(dev, "Failed to initialize phy: %d\n", ret);
+		goto out_reset_release;
+	}
+
+	ret = generic_phy_power_on(&priv->phy);
+	if (ret) {
+		dev_err(dev, "Failed to power on phy: %d\n", ret);
+		goto out_phy_exit;
+	}
+
+	uniphier_pcie_init_rc(priv);
+
+	/* set DBI to read only */
+	writel(0, priv->dbi_base + PCIE_MISC_CONTROL_1_OFF);
+
+	uniphier_pcie_setup_rc(priv, hose);
+
+	if (uniphier_pcie_establish_link(priv)) {
+		printf("PCIE-%d: Link down\n", dev_seq(dev));
+	} else {
+		printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
+		       dev_seq(dev), pcie_dw_get_link_speed(priv),
+		       pcie_dw_get_link_width(priv), hose->first_busno);
+	}
+
+	return 0;
+
+out_phy_exit:
+	generic_phy_exit(&priv->phy);
+out_reset_release:
+	reset_release_all(&priv->rst, 1);
+out_clk_release:
+	clk_release_all(&priv->clk, 1);
+
+	return ret;
+}
+
+static int uniphier_pcie_of_to_plat(struct udevice *dev)
+{
+	struct uniphier_pcie_priv *priv = dev_get_priv(dev);
+	const void *fdt = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+	int ret;
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "link", &priv->link_res);
+	if (ret) {
+		dev_err(dev, "Failed to get link regs: %d\n", ret);
+		return ret;
+	}
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "dbi", &priv->dbi_res);
+	if (ret) {
+		dev_err(dev, "Failed to get dbi regs: %d\n", ret);
+		return ret;
+	}
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "config", &priv->cfg_res);
+	if (ret) {
+		dev_err(dev, "Failed to get config regs: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret) {
+		dev_err(dev, "Failed to get clocks property: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_index(dev, 0, &priv->rst);
+	if (ret) {
+		dev_err(dev, "Failed to get resets property: %d\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_get_by_index(dev, 0, &priv->phy);
+	if (ret) {
+		dev_err(dev, "Failed to get phy property: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dm_pci_ops uniphier_pcie_ops = {
+	.read_config	= uniphier_pcie_read_config,
+	.write_config	= uniphier_pcie_write_config,
+};
+
+static const struct udevice_id uniphier_pcie_ids[] = {
+	{ .compatible = "socionext,uniphier-pcie", },
+	{ /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pcie_uniphier) = {
+	.name     = "uniphier-pcie",
+	.id       = UCLASS_PCI,
+	.of_match = uniphier_pcie_ids,
+	.probe    = uniphier_pcie_probe,
+	.ops      = &uniphier_pcie_ops,
+	.of_to_plat = uniphier_pcie_of_to_plat,
+	.priv_auto = sizeof(struct uniphier_pcie_priv),
+};
-- 
2.7.4

[PATCH 5/6] configs: uniphier: Enable CONFIG_SYS_PCI_64BIT

[Kunihiko Hayashi]

Enable CONFIG_SYS_PCI_64BIT to allow 64bit access to PCI space.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 include/configs/uniphier.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index bad4e41..12028e5 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -210,4 +210,6 @@
 
 #define CONFIG_SPL_PAD_TO			0x20000
 
+#define CONFIG_SYS_PCI_64BIT
+
 #endif /* __CONFIG_UNIPHIER_H__ */
-- 
2.7.4

[PATCH 6/6] ARM: dts: uniphier: Add support for Akebi96

[Kunihiko Hayashi]

Add the device tree for Akebi96. Akebi96 is a 96boards certified
development board based on UniPhier LD20.
( https://www.96boards.org/product/akebi96/ )

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm/dts/Makefile                  |   1 +
 arch/arm/dts/uniphier-ld20-akebi96.dts | 189 +++++++++++++++++++++++++++++++++
 2 files changed, 190 insertions(+)
 create mode 100644 arch/arm/dts/uniphier-ld20-akebi96.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9fb3868..ff50727 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -250,6 +250,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
 	uniphier-ld11-global.dtb \
 	uniphier-ld11-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
+	uniphier-ld20-akebi96.dtb \
 	uniphier-ld20-global.dtb \
 	uniphier-ld20-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
diff --git a/arch/arm/dts/uniphier-ld20-akebi96.dts b/arch/arm/dts/uniphier-ld20-akebi96.dts
new file mode 100644
index 0000000..aa159a1
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld20-akebi96.dts
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for Akebi96 Development Board
+//
+// Derived from uniphier-ld20-global.dts.
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Copyright (C) 2019-2020 Linaro Ltd.
+
+/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include "uniphier-ld20.dtsi"
+
+/ {
+	model = "Akebi96";
+	compatible = "socionext,uniphier-ld20-akebi96",
+		     "socionext,uniphier-ld20";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		ethernet0 = &eth;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+
+	framebuffer@c0000000 {
+		compatible = "simple-framebuffer";
+		reg = <0 0xc0000000 0 0x02000000>;
+		width = <1920>;
+		height = <1080>;
+		stride = <7680>;
+		format = "a8r8g8b8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		memory@c0000000 {
+			reg = <0 0xc0000000 0 0x02000000>;
+			no-map;
+		};
+	};
+
+	sound {
+		compatible = "audio-graph-card";
+		label = "UniPhier LD20";
+		dais = <&spdif_port0
+			&comp_spdif_port0>;
+	};
+
+	spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+
+		port@0 {
+			spdif_tx: endpoint {
+				remote-endpoint = <&spdif_hiecout1>;
+			};
+		};
+	};
+
+	comp-spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+
+		port@0 {
+			comp_spdif_tx: endpoint {
+				remote-endpoint = <&comp_spdif_hiecout1>;
+			};
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&spi3 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	usb-over-spi@0 {
+		compatible = "maxim,max3421-udc";
+		reg = <0>;
+		spi-max-frequency = <12500000>;
+		interrupt-parent = <&gpio>;
+		interrupt-names = "udc";
+		interrupts = <0 2>;
+	};
+};
+
+&serial0 {
+	/* Onboard USB-UART */
+	status = "okay";
+};
+
+&serial2 {
+	/* LS connector UART1 */
+	status = "okay";
+};
+
+&serial3 {
+	/* LS connector UART0 */
+	status = "okay";
+};
+
+&spdif_hiecout1 {
+	remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+	remote-endpoint = <&comp_spdif_tx>;
+};
+
+&i2c0 {
+	/* LS connector I2C0 */
+	status = "okay";
+};
+
+&i2c1 {
+	/* LS connector I2C1 */
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	phy-handle = <&ethphy>;
+};
+
+&mdio {
+	ethphy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&usb {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&gpio {
+	/* IRQs for Max3421 */
+	xirq0 {
+		gpio-hog;
+		gpios = <UNIPHIER_GPIO_IRQ(0) 1>;
+		input;
+	};
+	xirq10 {
+		gpio-hog;
+		gpios = <UNIPHIER_GPIO_IRQ(10) 1>;
+		input;
+	};
+};
+
+&pinctrl_aout1 {
+	groups = "aout1b";
+};
+
+&pinctrl_uart3 {
+	groups = "uart3", "uart3_ctsrts";
+};
-- 
2.7.4

Re: [PATCH 1/6] clk: uniphier: Add PCIe clock entry

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:06PM +0900, Kunihiko Hayashi wrote:

> Add clock control for PCIe controller on each SoC.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 2/6] reset: uniphier: Add PCIe reset entry

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:07PM +0900, Kunihiko Hayashi wrote:

> Add reset control for PCIe controller on each SoC.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 3/6] phy: socionext: Add UniPhier PCIe PHY driver

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:08PM +0900, Kunihiko Hayashi wrote:

> Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 4/6] pci: uniphier: Add UniPhier PCIe controller driver

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:09PM +0900, Kunihiko Hayashi wrote:

> Add PCIe driver for UniPhier SoCs. This PCIe controller is based on
> Synopsys DesignWare Core IP.
> 
> This version doesn't apply common DW functions because supported
> controller doesn't have unroll version of iATU.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 5/6] configs: uniphier: Enable CONFIG_SYS_PCI_64BIT

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:10PM +0900, Kunihiko Hayashi wrote:

> Enable CONFIG_SYS_PCI_64BIT to allow 64bit access to PCI space.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 6/6] ARM: dts: uniphier: Add support for Akebi96

[Tom Rini]

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On Tue, Jul 06, 2021 at 07:01:11PM +0900, Kunihiko Hayashi wrote:

> Add the device tree for Akebi96. Akebi96 is a 96boards certified
> development board based on UniPhier LD20.
> ( https://www.96boards.org/product/akebi96/ )
> 
> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom

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