From: Mark Brown <broonie@kernel.org>
To: Apurva Nandan <a-nandan@ti.com>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
Pratyush Yadav <p.yadav@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling
Date: Thu, 15 Jul 2021 17:41:42 +0100 [thread overview]
Message-ID: <20210715164142.GB27092@sirena.org.uk> (raw)
In-Reply-To: <1cebc261-e0aa-572a-8083-1e3ec0d09195@ti.com>
[-- Attachment #1: Type: text/plain, Size: 1453 bytes --]
On Thu, Jul 15, 2021 at 09:57:51PM +0530, Apurva Nandan wrote:
> Now, whether the poll instruction should have an address phase or not
> depends on the connected flash chip, which the controller wouldn't be
> aware of as it only takes in a spimem op from the flash cores for execution.
...
> More to this, not just address phase but any kind of variation in the
> read register operation would result in polling failure.
That seems like something that should be fixed since it means that no
controller will be able to support a feature like this - it needs to get
enough information passed to it to allow it to poll correctly.
> Any SPI operation that is going underneath the visibility of flash core
> can can problems. I agree offloading the status polling process to
> controller HW is beneficial but on the other hand it restricts the flash
> on having a fixed type of polling operation. This would reduce the
> number of flash devices it will support (out of the box).
> What should be the right way out for this situation?
One idea would be to have something that takes both the operation itself
and the operation that's used to poll for status (with expected result),
the controller can then check the poll operation and either tell the
core it's not supported or go ahead and do the polling. Or simpler just
a separate poll operation which is fully specified enough.
Not actually looked at the code to see how tasteful that is though...
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
next prev parent reply other threads:[~2021-07-15 16:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 12:57 [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations Apurva Nandan
2021-07-13 12:57 ` [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling Apurva Nandan
2021-07-13 18:25 ` Mark Brown
2021-07-14 13:22 ` Nandan, Apurva
2021-07-14 16:28 ` Mark Brown
2021-07-14 17:51 ` Apurva Nandan
2021-07-15 16:27 ` Apurva Nandan
2021-07-15 16:41 ` Mark Brown [this message]
2021-07-15 18:36 ` Pratyush Yadav
2021-07-16 18:04 ` Mark Brown
2021-07-13 12:57 ` [PATCH 2/2] spi: cadence-quadspi: Fix check condition for DTR ops Apurva Nandan
2021-07-13 18:39 ` Mark Brown
2021-07-14 12:54 ` [EXTERNAL] " Nandan, Apurva
2021-07-16 18:31 ` (subset) [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210715164142.GB27092@sirena.org.uk \
--to=broonie@kernel.org \
--cc=a-nandan@ti.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=p.yadav@ti.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.