From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, INCLUDES_PULL_REQUEST,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EC36C636CA for ; Fri, 16 Jul 2021 13:04:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24B3B613F3 for ; Fri, 16 Jul 2021 13:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232706AbhGPNHC (ORCPT ); Fri, 16 Jul 2021 09:07:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232804AbhGPNG4 (ORCPT ); Fri, 16 Jul 2021 09:06:56 -0400 Received: from ustc.edu.cn (email6.ustc.edu.cn [IPv6:2001:da8:d800::8]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BFD90C06175F for ; Fri, 16 Jul 2021 06:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mail.ustc.edu.cn; s=dkim; h=Received:Date:From:To:Cc:Subject: Message-ID:In-Reply-To:References:MIME-Version:Content-Type: Content-Transfer-Encoding; bh=PWw4hK0cXSC8fe2icAs8ZJRU7ppP5otO7G /VcmZBdKY=; b=nxA3M2ZjRaxl7wkglFuEBxfK84S1MxWl4R5ZpGwc5VpzuPELqn IjMOWkTl6uc5Cyw9RJZNFLmi6hpJD6r6uOfyigB3bds9L0ftcJkmURbWBlQxedBL YpPGYzACK+H1J2c0ZtdrKQp7yHdaIOTq+Rpwsks5KPPBkxAg9x9877QlU= Received: from xhacker (unknown [101.86.20.15]) by newmailweb.ustc.edu.cn (Coremail) with SMTP id LkAmygDHM+izg_Fg9Y57AA--.56756S2; Fri, 16 Jul 2021 21:03:47 +0800 (CST) Date: Fri, 16 Jul 2021 20:57:57 +0800 From: Jisheng Zhang To: Alex Ghiti Cc: Palmer Dabbelt , Linus Torvalds , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Jisheng Zhang , Geert Uytterhoeven , Arnd Bergmann Subject: Re: [GIT PULL] RISC-V Patches for the 5.14 Merge Window, Part 1 Message-ID: <20210716205758.05620241@xhacker> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: LkAmygDHM+izg_Fg9Y57AA--.56756S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JrW8Zw1fAr45GryrXFy7Jrb_yoW7uF4Dpr n3tFW3GrW5XF1kJr4Ut34UZFWjqry8Ja1UXr18JFy8Ars0yryjgr1jgr1v9ryUJrWrJr1U Gr1rJry7Zr1UJrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyFb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I 8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI 64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8Jw Am72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41l42xK82IYc2Ij64vIr41l4I8I3I0E 4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGV WUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_ Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rV W3JVWrJr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8 JrUvcSsGvfC2KfnxnUUI43ZEXa7IU5IksPUUUUU== X-CM-SenderInfo: xmv2xttqjtqzxdloh3xvwfhvlgxou0/ Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 15 Jul 2021 09:11:14 +0200 Alex Ghiti wrote: > Hi Palmer, >=20 > Le 11/07/2021 =C3=A0 20:45, Palmer Dabbelt a =C3=A9crit=C2=A0: > > On Fri, 09 Jul 2021 12:58:10 PDT (-0700), alex@ghiti.fr wrote: =20 > >> > >> > >> Le 9/07/2021 =C3=A0 16:53, Palmer Dabbelt a =C3=A9crit=C2=A0: =20 > >>> The following changes since commit=20 > >>> 8a4102a0cf07cc76a18f373f6b49485258cc6af4: > >>> > >>> =C2=A0=C2=A0 riscv: mm: Fix W+X mappings at boot (2021-06-01 21:15:09= -0700) > >>> > >>> are available in the Git repository at: > >>> > >>> =C2=A0=C2=A0 git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linu= x.git=20 > >>> tags/riscv-for-linus-5.14-mw0 > >>> > >>> for you to fetch changes up to 1958e5aef5098e28b7d6e6a2972649901ebeca= ce: > >>> > >>> =C2=A0=C2=A0 riscv: xip: Fix duplicate included asm/pgtable.h (2021-0= 7-06=20 > >>> 16:17:40 -0700) > >>> > >>> ---------------------------------------------------------------- > >>> RISC-V Patches for the 5.14 Merge Window, Part 1 > >>> > >>> In addition to We have a handful of new features for 5.14: > >>> > >>> * Support for transparent huge pages. > >>> * Support for generic PCI resources mapping. > >>> * Support for the mem=3D kernel parameter. > >>> * Support for KFENCE. > >>> * A handful of fixes to avoid W+X mappings in the kernel. > >>> * Support for VMAP_STACK based overflow detection. > >>> * An optimized copy_{to,from}_user. > >>> ---------------------------------------------------------------- > >>> There are some Kconfig merge conflicts.=C2=A0 They should be pretty > >>> straight-forward, but we do have a symbol out of order -- I thought I= =20 > >>> had a > >>> script to check for that, but I guess it doesn't work.=C2=A0 I just s= ent=20 > >>> out a patch > >>> to fix it up. > >>> > >>> diff --cc arch/riscv/Kconfig > >>> index 3590eb76000e,469a70bd8da6..d36f3c5029fd > >>> --- a/arch/riscv/Kconfig > >>> +++ b/arch/riscv/Kconfig > >>> @@@ -60,12 -61,11 +61,12 @@@ config RISC > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select GENERIC_TIME_= VSYSCALL if MMU && 64BIT > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HANDLE_DOMAIN= _IRQ > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_AUD= ITSYSCALL > >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL > >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL_REL= ATIVE > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL if = !XIP_KERNEL > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL_REL= ATIVE if !XIP_KERNEL > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KAS= AN if MMU && 64BIT > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KAS= AN_VMALLOC if MMU && 64BIT > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KFENCE if MMU= && 64BIT > >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGDB > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGDB if !XIP_K= ERNEL > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGD= B_QXFER_PKT > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_MMA= P_RND_BITS if MMU > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_SEC= COMP_FILTER > >>> @@@ -81,11 -80,9 +82,14 @@@ > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_GCC_PLUG= INS > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_GENERIC_= VDSO if MMU && 64BIT > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_IRQ_TIME= _ACCOUNTING > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES_ON_FTRACE > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KRETPROBES > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES if !XIP_KER= NEL > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES_ON_FTRACE i= f !XIP_KERNEL > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KRETPROBES if !XIP_= KERNEL > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_MOVE_PMD > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_MOVE_PUD > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PCI > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PERF_EVE= NTS > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PERF_REGS > >>> @@@ -108,7 -104,7 +112,8 @@@ > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select SYSCTL_EXCEPT= ION_TRACE > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select THREAD_INFO_I= N_TASK > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select UACCESS_MEMCP= Y if !MMU > >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_TRANSPARENT_H= UGEPAGE if 64BIT && MMU > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ZONE_DMA32 if 64BIT > >>> > >>> =C2=A0=C2=A0 config ARCH_MMAP_RND_BITS_MIN > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default 18 if 64BIT > >>> ---------------------------------------------------------------- > >>> Akira Tsukamoto (1): > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: __asm_copy_to-from_user: = Optimize unaligned memory=20 > >>> access and pipeline stall > >>> > >>> Alexandre Ghiti (6): > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: Remove CONFIG_PHYS_RAM_BA= SE_FIXED > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: Simplify xip and !xip ker= nel address conversion macros =20 > >> > >> @Palmer: As said in the thread of this patchset multiple times, those 2 > >> patches should not be merged as it assumes that the base DRAM address = is > >> always 0x8000_0000 for all rv64 platforms: I don't think it is true,=20 > >> is it? =20 > >=20 > > Sorry, I remember saying something about that but must have missed the= =20 > > resposeses.=C2=A0 Do you have a pointer to the discussion?=C2=A0 If thi= s break=20 > > stuff I'm happy to revert it, which can be done post-rc1.=C2=A0 I just = need=20 > > to see what's actually broken first, because IIUC this was de-facto how= =20 > > things worked already. > > =20 >=20 > Really sorry about my response delay. >=20 > The thing is that removing CONFIG_PHYS_RAM_BASE_FIXED defines=20 > CONFIG_PHYS_RAM_BASE to 0x8000_0000 for all rv64 chips, but I believe=20 > this is implementation specific: for now, this base address was passed=20 > into the device tree, and here it makes this value static. >=20 > This issue with my patch was originally pointed by Jisheng, Geert and Arn= d. >=20 > If this is not a problem and you have a pointer to a document that=20 > specifies this, I would be very happy to have the link :) >=20 > Thanks and again sorry about my response delay, >=20 Hi Alex, Since the PR has been merged into linux-5.14-rc1, directly reverting seems not a good idea. IMHO, it's better to send patch(es) against current 5.14-r= c1 tree. what do you think? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, INCLUDES_PULL_REQUEST,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52D47C07E95 for ; Fri, 16 Jul 2021 13:04:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E632C613F2 for ; Fri, 16 Jul 2021 13:04:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E632C613F2 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=mail.ustc.edu.cn Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=togSk0DeJ8Wzf5Rzffep5jpnv8FgkAYaxPjHkIbX4KM=; b=R54wZqmJBIR06O zAzrAFWB1JT36hZl1mkpddRqlPX5foEmJnRFJj53Abo3C8EM3xU3H+sUdmpQeaE4GJEQ3aNRhdhln BDN4+Ix0aG+wMSe/JPiaxLOIJF89DfZgiwgxBtkpReOU65POhFfJpZZOtD01Nt7swGWOc/Vz5BE34 bkjepJ+Yh18396Y/ZdynjmKVQo1Dv4UzOzUufjQKoS+qdEGFauFvGvMwScrMO+1TeFn3A/RF4wygH CAfYRehKKkacD3/ZbXxcVBjBqNym5e/iygVb2HaaV5i1wP9xzIXEnhzWn9jp0d/wSChypCMGGTYKD brlo89FyypFbrsr+KueA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m4NVc-004QHn-IW; Fri, 16 Jul 2021 13:04:04 +0000 Received: from email6.ustc.edu.cn ([2001:da8:d800::8] helo=ustc.edu.cn) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m4NVY-004QHH-70 for linux-riscv@lists.infradead.org; Fri, 16 Jul 2021 13:04:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mail.ustc.edu.cn; s=dkim; h=Received:Date:From:To:Cc:Subject: Message-ID:In-Reply-To:References:MIME-Version:Content-Type: Content-Transfer-Encoding; bh=PWw4hK0cXSC8fe2icAs8ZJRU7ppP5otO7G /VcmZBdKY=; b=nxA3M2ZjRaxl7wkglFuEBxfK84S1MxWl4R5ZpGwc5VpzuPELqn IjMOWkTl6uc5Cyw9RJZNFLmi6hpJD6r6uOfyigB3bds9L0ftcJkmURbWBlQxedBL YpPGYzACK+H1J2c0ZtdrKQp7yHdaIOTq+Rpwsks5KPPBkxAg9x9877QlU= Received: from xhacker (unknown [101.86.20.15]) by newmailweb.ustc.edu.cn (Coremail) with SMTP id LkAmygDHM+izg_Fg9Y57AA--.56756S2; Fri, 16 Jul 2021 21:03:47 +0800 (CST) Date: Fri, 16 Jul 2021 20:57:57 +0800 From: Jisheng Zhang To: Alex Ghiti Cc: Palmer Dabbelt , Linus Torvalds , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Jisheng Zhang , Geert Uytterhoeven , Arnd Bergmann Subject: Re: [GIT PULL] RISC-V Patches for the 5.14 Merge Window, Part 1 Message-ID: <20210716205758.05620241@xhacker> In-Reply-To: References: MIME-Version: 1.0 X-CM-TRANSID: LkAmygDHM+izg_Fg9Y57AA--.56756S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JrW8Zw1fAr45GryrXFy7Jrb_yoW7uF4Dpr n3tFW3GrW5XF1kJr4Ut34UZFWjqry8Ja1UXr18JFy8Ars0yryjgr1jgr1v9ryUJrWrJr1U Gr1rJry7Zr1UJrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyFb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I 8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI 64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8Jw Am72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41l42xK82IYc2Ij64vIr41l4I8I3I0E 4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGV WUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_ Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rV W3JVWrJr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8 JrUvcSsGvfC2KfnxnUUI43ZEXa7IU5IksPUUUUU== X-CM-SenderInfo: xmv2xttqjtqzxdloh3xvwfhvlgxou0/ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210716_060400_971984_8E8E0950 X-CRM114-Status: GOOD ( 27.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVGh1LCAxNSBKdWwgMjAyMSAwOToxMToxNCArMDIwMApBbGV4IEdoaXRpIDxhbGV4QGdoaXRp LmZyPiB3cm90ZToKCj4gSGkgUGFsbWVyLAo+IAo+IExlIDExLzA3LzIwMjEgw6AgMjA6NDUsIFBh bG1lciBEYWJiZWx0IGEgw6ljcml0wqA6Cj4gPiBPbiBGcmksIDA5IEp1bCAyMDIxIDEyOjU4OjEw IFBEVCAoLTA3MDApLCBhbGV4QGdoaXRpLmZyIHdyb3RlOiAgCj4gPj4KPiA+Pgo+ID4+IExlIDkv MDcvMjAyMSDDoCAxNjo1MywgUGFsbWVyIERhYmJlbHQgYSDDqWNyaXTCoDogIAo+ID4+PiBUaGUg Zm9sbG93aW5nIGNoYW5nZXMgc2luY2UgY29tbWl0IAo+ID4+PiA4YTQxMDJhMGNmMDdjYzc2YTE4 ZjM3M2Y2YjQ5NDg1MjU4Y2M2YWY0Ogo+ID4+Pgo+ID4+PiDCoMKgIHJpc2N2OiBtbTogRml4IFcr WCBtYXBwaW5ncyBhdCBib290ICgyMDIxLTA2LTAxIDIxOjE1OjA5IC0wNzAwKQo+ID4+Pgo+ID4+ PiBhcmUgYXZhaWxhYmxlIGluIHRoZSBHaXQgcmVwb3NpdG9yeSBhdDoKPiA+Pj4KPiA+Pj4gwqDC oCBnaXQ6Ly9naXQua2VybmVsLm9yZy9wdWIvc2NtL2xpbnV4L2tlcm5lbC9naXQvcmlzY3YvbGlu dXguZ2l0IAo+ID4+PiB0YWdzL3Jpc2N2LWZvci1saW51cy01LjE0LW13MAo+ID4+Pgo+ID4+PiBm b3IgeW91IHRvIGZldGNoIGNoYW5nZXMgdXAgdG8gMTk1OGU1YWVmNTA5OGUyOGI3ZDZlNmEyOTcy NjQ5OTAxZWJlY2FjZToKPiA+Pj4KPiA+Pj4gwqDCoCByaXNjdjogeGlwOiBGaXggZHVwbGljYXRl IGluY2x1ZGVkIGFzbS9wZ3RhYmxlLmggKDIwMjEtMDctMDYgCj4gPj4+IDE2OjE3OjQwIC0wNzAw KQo+ID4+Pgo+ID4+PiAtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4gPj4+IFJJU0MtViBQYXRjaGVzIGZvciB0aGUgNS4xNCBN ZXJnZSBXaW5kb3csIFBhcnQgMQo+ID4+Pgo+ID4+PiBJbiBhZGRpdGlvbiB0byBXZSBoYXZlIGEg aGFuZGZ1bCBvZiBuZXcgZmVhdHVyZXMgZm9yIDUuMTQ6Cj4gPj4+Cj4gPj4+ICogU3VwcG9ydCBm b3IgdHJhbnNwYXJlbnQgaHVnZSBwYWdlcy4KPiA+Pj4gKiBTdXBwb3J0IGZvciBnZW5lcmljIFBD SSByZXNvdXJjZXMgbWFwcGluZy4KPiA+Pj4gKiBTdXBwb3J0IGZvciB0aGUgbWVtPSBrZXJuZWwg cGFyYW1ldGVyLgo+ID4+PiAqIFN1cHBvcnQgZm9yIEtGRU5DRS4KPiA+Pj4gKiBBIGhhbmRmdWwg b2YgZml4ZXMgdG8gYXZvaWQgVytYIG1hcHBpbmdzIGluIHRoZSBrZXJuZWwuCj4gPj4+ICogU3Vw cG9ydCBmb3IgVk1BUF9TVEFDSyBiYXNlZCBvdmVyZmxvdyBkZXRlY3Rpb24uCj4gPj4+ICogQW4g b3B0aW1pemVkIGNvcHlfe3RvLGZyb219X3VzZXIuCj4gPj4+IC0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiA+Pj4gVGhlcmUg YXJlIHNvbWUgS2NvbmZpZyBtZXJnZSBjb25mbGljdHMuwqAgVGhleSBzaG91bGQgYmUgcHJldHR5 Cj4gPj4+IHN0cmFpZ2h0LWZvcndhcmQsIGJ1dCB3ZSBkbyBoYXZlIGEgc3ltYm9sIG91dCBvZiBv cmRlciAtLSBJIHRob3VnaHQgSSAKPiA+Pj4gaGFkIGEKPiA+Pj4gc2NyaXB0IHRvIGNoZWNrIGZv ciB0aGF0LCBidXQgSSBndWVzcyBpdCBkb2Vzbid0IHdvcmsuwqAgSSBqdXN0IHNlbnQgCj4gPj4+ IG91dCBhIHBhdGNoCj4gPj4+IHRvIGZpeCBpdCB1cC4KPiA+Pj4KPiA+Pj4gZGlmZiAtLWNjIGFy Y2gvcmlzY3YvS2NvbmZpZwo+ID4+PiBpbmRleCAzNTkwZWI3NjAwMGUsNDY5YTcwYmQ4ZGE2Li5k MzZmM2M1MDI5ZmQKPiA+Pj4gLS0tIGEvYXJjaC9yaXNjdi9LY29uZmlnCj4gPj4+ICsrKyBiL2Fy Y2gvcmlzY3YvS2NvbmZpZwo+ID4+PiBAQEAgLTYwLDEyIC02MSwxMSArNjEsMTIgQEBAIGNvbmZp ZyBSSVNDCj4gPj4+IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEdFTkVSSUNfVElNRV9WU1lTQ0FM TCBpZiBNTVUgJiYgNjRCSVQKPiA+Pj4gwqDCoMKgwqDCoMKgwqDCoCBzZWxlY3QgSEFORExFX0RP TUFJTl9JUlEKPiA+Pj4gwqDCoMKgwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9BUkNIX0FVRElUU1lT Q0FMTAo+ID4+PiAtwqDCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTAo+ID4+ PiAtwqDCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTF9SRUxBVElWRQo+ID4+ PiArwqDCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTCBpZiAhWElQX0tFUk5F TAo+ID4+PiArwqDCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTF9SRUxBVElW RSBpZiAhWElQX0tFUk5FTAo+ID4+PiDCoMKgwqDCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX0FSQ0hf S0FTQU4gaWYgTU1VICYmIDY0QklUCj4gPj4+IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVf QVJDSF9LQVNBTl9WTUFMTE9DIGlmIE1NVSAmJiA2NEJJVAo+ID4+PiDCoCArwqDCoMKgwqDCoCBz ZWxlY3QgSEFWRV9BUkNIX0tGRU5DRSBpZiBNTVUgJiYgNjRCSVQKPiA+Pj4gLcKgwqDCoMKgwqDC oCBzZWxlY3QgSEFWRV9BUkNIX0tHREIKPiA+Pj4gK8KgwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9B UkNIX0tHREIgaWYgIVhJUF9LRVJORUwKPiA+Pj4gwqDCoMKgwqDCoMKgwqDCoCBzZWxlY3QgSEFW RV9BUkNIX0tHREJfUVhGRVJfUEtUCj4gPj4+IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVf QVJDSF9NTUFQX1JORF9CSVRTIGlmIE1NVQo+ID4+PiDCoMKgwqDCoMKgwqDCoMKgIHNlbGVjdCBI QVZFX0FSQ0hfU0VDQ09NUF9GSUxURVIKPiA+Pj4gQEBAIC04MSwxMSAtODAsOSArODIsMTQgQEBA Cj4gPj4+IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVfR0NDX1BMVUdJTlMKPiA+Pj4gwqDC oMKgwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9HRU5FUklDX1ZEU08gaWYgTU1VICYmIDY0QklUCj4g Pj4+IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVfSVJRX1RJTUVfQUNDT1VOVElORwo+ID4+ PiDCoCArwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9LUFJPQkVTCj4gPj4+IMKgICvCoMKgwqDCoMKg IHNlbGVjdCBIQVZFX0tQUk9CRVNfT05fRlRSQUNFCj4gPj4+IMKgICvCoMKgwqDCoMKgIHNlbGVj dCBIQVZFX0tSRVRQUk9CRVMKPiA+Pj4gK8KgwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9LUFJPQkVT IGlmICFYSVBfS0VSTkVMCj4gPj4+ICvCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVfS1BST0JFU19P Tl9GVFJBQ0UgaWYgIVhJUF9LRVJORUwKPiA+Pj4gK8KgwqDCoMKgwqDCoCBzZWxlY3QgSEFWRV9L UkVUUFJPQkVTIGlmICFYSVBfS0VSTkVMCj4gPj4+IMKgICvCoMKgwqDCoMKgIHNlbGVjdCBIQVZF X01PVkVfUE1ECj4gPj4+IMKgICvCoMKgwqDCoMKgIHNlbGVjdCBIQVZFX01PVkVfUFVECj4gPj4+ IMKgwqDCoMKgwqDCoMKgwqAgc2VsZWN0IEhBVkVfUENJCj4gPj4+IMKgwqDCoMKgwqDCoMKgwqAg c2VsZWN0IEhBVkVfUEVSRl9FVkVOVFMKPiA+Pj4gwqDCoMKgwqDCoMKgwqDCoCBzZWxlY3QgSEFW RV9QRVJGX1JFR1MKPiA+Pj4gQEBAIC0xMDgsNyAtMTA0LDcgKzExMiw4IEBAQAo+ID4+PiDCoMKg wqDCoMKgwqDCoMKgIHNlbGVjdCBTWVNDVExfRVhDRVBUSU9OX1RSQUNFCj4gPj4+IMKgwqDCoMKg wqDCoMKgwqAgc2VsZWN0IFRIUkVBRF9JTkZPX0lOX1RBU0sKPiA+Pj4gwqDCoMKgwqDCoMKgwqDC oCBzZWxlY3QgVUFDQ0VTU19NRU1DUFkgaWYgIU1NVQo+ID4+PiDCoCArwqDCoMKgwqDCoCBzZWxl Y3QgSEFWRV9BUkNIX1RSQU5TUEFSRU5UX0hVR0VQQUdFIGlmIDY0QklUICYmIE1NVQo+ID4+PiAr wqDCoMKgwqDCoMKgIHNlbGVjdCBaT05FX0RNQTMyIGlmIDY0QklUCj4gPj4+Cj4gPj4+IMKgwqAg Y29uZmlnIEFSQ0hfTU1BUF9STkRfQklUU19NSU4KPiA+Pj4gwqDCoMKgwqDCoMKgwqDCoCBkZWZh dWx0IDE4IGlmIDY0QklUCj4gPj4+IC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiA+Pj4gQWtpcmEgVHN1a2Ftb3RvICgxKToK PiA+Pj4gwqDCoMKgwqDCoMKgIHJpc2N2OiBfX2FzbV9jb3B5X3RvLWZyb21fdXNlcjogT3B0aW1p emUgdW5hbGlnbmVkIG1lbW9yeSAKPiA+Pj4gYWNjZXNzIGFuZCBwaXBlbGluZSBzdGFsbAo+ID4+ Pgo+ID4+PiBBbGV4YW5kcmUgR2hpdGkgKDYpOgo+ID4+PiDCoMKgwqDCoMKgwqAgcmlzY3Y6IFJl bW92ZSBDT05GSUdfUEhZU19SQU1fQkFTRV9GSVhFRAo+ID4+PiDCoMKgwqDCoMKgwqAgcmlzY3Y6 IFNpbXBsaWZ5IHhpcCBhbmQgIXhpcCBrZXJuZWwgYWRkcmVzcyBjb252ZXJzaW9uIG1hY3JvcyAg Cj4gPj4KPiA+PiBAUGFsbWVyOiBBcyBzYWlkIGluIHRoZSB0aHJlYWQgb2YgdGhpcyBwYXRjaHNl dCBtdWx0aXBsZSB0aW1lcywgdGhvc2UgMgo+ID4+IHBhdGNoZXMgc2hvdWxkIG5vdCBiZSBtZXJn ZWQgYXMgaXQgYXNzdW1lcyB0aGF0IHRoZSBiYXNlIERSQU0gYWRkcmVzcyBpcwo+ID4+IGFsd2F5 cyAweDgwMDBfMDAwMCBmb3IgYWxsIHJ2NjQgcGxhdGZvcm1zOiBJIGRvbid0IHRoaW5rIGl0IGlz IHRydWUsIAo+ID4+IGlzIGl0PyAgCj4gPiAKPiA+IFNvcnJ5LCBJIHJlbWVtYmVyIHNheWluZyBz b21ldGhpbmcgYWJvdXQgdGhhdCBidXQgbXVzdCBoYXZlIG1pc3NlZCB0aGUgCj4gPiByZXNwb3Nl c2VzLsKgIERvIHlvdSBoYXZlIGEgcG9pbnRlciB0byB0aGUgZGlzY3Vzc2lvbj/CoCBJZiB0aGlz IGJyZWFrIAo+ID4gc3R1ZmYgSSdtIGhhcHB5IHRvIHJldmVydCBpdCwgd2hpY2ggY2FuIGJlIGRv bmUgcG9zdC1yYzEuwqAgSSBqdXN0IG5lZWQgCj4gPiB0byBzZWUgd2hhdCdzIGFjdHVhbGx5IGJy b2tlbiBmaXJzdCwgYmVjYXVzZSBJSVVDIHRoaXMgd2FzIGRlLWZhY3RvIGhvdyAKPiA+IHRoaW5n cyB3b3JrZWQgYWxyZWFkeS4KPiA+ICAgCj4gCj4gUmVhbGx5IHNvcnJ5IGFib3V0IG15IHJlc3Bv bnNlIGRlbGF5Lgo+IAo+IFRoZSB0aGluZyBpcyB0aGF0IHJlbW92aW5nIENPTkZJR19QSFlTX1JB TV9CQVNFX0ZJWEVEIGRlZmluZXMgCj4gQ09ORklHX1BIWVNfUkFNX0JBU0UgdG8gMHg4MDAwXzAw MDAgZm9yIGFsbCBydjY0IGNoaXBzLCBidXQgSSBiZWxpZXZlIAo+IHRoaXMgaXMgaW1wbGVtZW50 YXRpb24gc3BlY2lmaWM6IGZvciBub3csIHRoaXMgYmFzZSBhZGRyZXNzIHdhcyBwYXNzZWQgCj4g aW50byB0aGUgZGV2aWNlIHRyZWUsIGFuZCBoZXJlIGl0IG1ha2VzIHRoaXMgdmFsdWUgc3RhdGlj Lgo+IAo+IFRoaXMgaXNzdWUgd2l0aCBteSBwYXRjaCB3YXMgb3JpZ2luYWxseSBwb2ludGVkIGJ5 IEppc2hlbmcsIEdlZXJ0IGFuZCBBcm5kLgo+IAo+IElmIHRoaXMgaXMgbm90IGEgcHJvYmxlbSBh bmQgeW91IGhhdmUgYSBwb2ludGVyIHRvIGEgZG9jdW1lbnQgdGhhdCAKPiBzcGVjaWZpZXMgdGhp cywgSSB3b3VsZCBiZSB2ZXJ5IGhhcHB5IHRvIGhhdmUgdGhlIGxpbmsgOikKPiAKPiBUaGFua3Mg YW5kIGFnYWluIHNvcnJ5IGFib3V0IG15IHJlc3BvbnNlIGRlbGF5LAo+IAoKSGkgQWxleCwKClNp bmNlIHRoZSBQUiBoYXMgYmVlbiBtZXJnZWQgaW50byBsaW51eC01LjE0LXJjMSwgZGlyZWN0bHkg cmV2ZXJ0aW5nIHNlZW1zCm5vdCBhIGdvb2QgaWRlYS4gSU1ITywgaXQncyBiZXR0ZXIgdG8gc2Vu ZCBwYXRjaChlcykgYWdhaW5zdCBjdXJyZW50IDUuMTQtcmMxCnRyZWUuIHdoYXQgZG8geW91IHRo aW5rPwoKVGhhbmtzCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVh ZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1y aXNjdgo=