From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD98C636C9 for ; Wed, 21 Jul 2021 14:40:23 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id B4976608FE for ; Wed, 21 Jul 2021 14:40:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B4976608FE Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 954B6410F6; Wed, 21 Jul 2021 16:39:57 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2049.outbound.protection.outlook.com [40.107.237.49]) by mails.dpdk.org (Postfix) with ESMTP id 4AFE540DF8 for ; Wed, 21 Jul 2021 16:39:56 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HKyfPgZq+sx2Z4KL31TOMDM8dYdyLkLdCmsh6oU7s0lcS8T7NJn4p3N1BpEb6/BQ1VZc6sozHHMb1hfE3k6HCTO6btxze6F1QNJruAWuRY8ZEwGAvgQ05qr8oOE9m7iqlM0MrvdSfyJfazSl6DKT1kql0T9xjXyv1LoMOBONuKOlxEjqtevIJlprlJTSIi+ndxaO3Aa7eANnWaS2XiURcE81vXxVUY85vIBJCjeTTYN6yZPgbxXFrAhHO8dvKuuA8Lwonx/ALSRXFvv0/6YP/t0EK9eP8JQNRXfTSpqQdv8LBG1oI0L+6ELkyIb/2ODJLAMszj0mgUD/vCu/QgYNKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V4ILCgNy2Guy8F2M2xD6oU9UDJUEw57m8p9RuwHeahg=; b=dLO0Jvy4oHkVO1s1zcAkloQKX8XZlLF04kwh9w/bgPyLOI7JSwgp2zm91WDyBNa1qT3E4Y8XBEOVLo0UJwjDXKn6R0U0CKN3Igk6nWkbd61aTBLX/HMCb3ZKedoIXlqJ2Ude14rTRnNzTkEhLuCbgwcreG6CCEJKEVxqZAXIpNJe/hu5VFRS8s7U/x9IcHemJyhxS6glYwmYOA3xzjY7ImAABD5g1sxIqo5QMEdA6BzjF3qziOUuEkTUp42IClrDDiZGH9tZaS8rwuVIp96rj5vY1iUysjav1pPB4iR9TgM+o3jtjOJhNNMkYkaRUBWI4ABykpelOd7LpO2rss7Brw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V4ILCgNy2Guy8F2M2xD6oU9UDJUEw57m8p9RuwHeahg=; b=WnoNpyxA5YRe5H1cqy6xStHzYMSyescCEPrxVehU4qCV4YZ2iDTUfjFs7Jfz+XR5Kz0VOyfXkY6HHOjb3jXbTicZ0ZSRJrhTZdMiOGr5SI7dh538S9N/A1TSIgbrfUQxyK98eV2lHp+i0c5m/oUUjejXFiGQLF2EEUYcz1prcjWg3HJDqnFRdMfn9ElkUGaOESzz0SE10hn0BuO5P1bgZ9QTfiRwP1Uj8v3uBp4KOjCwA0j6xLZEQyYDtoDO83lnVd7dEMrtxhuXyk5Z/fzTQAkQ/SyATEP3kSJTHDsoSCBnezpfN3BIescKYTAzCOH6BA/9XpKZwyB9XDoU/QUymA== Received: from BN6PR16CA0048.namprd16.prod.outlook.com (2603:10b6:405:14::34) by MN2PR12MB4077.namprd12.prod.outlook.com (2603:10b6:208:1da::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.24; Wed, 21 Jul 2021 14:39:55 +0000 Received: from BN8NAM11FT056.eop-nam11.prod.protection.outlook.com (2603:10b6:405:14:cafe::41) by BN6PR16CA0048.outlook.office365.com (2603:10b6:405:14::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.24 via Frontend Transport; Wed, 21 Jul 2021 14:39:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT056.mail.protection.outlook.com (10.13.177.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4352.24 via Frontend Transport; Wed, 21 Jul 2021 14:39:54 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 21 Jul 2021 14:39:52 +0000 From: Xueming Li To: Viacheslav Ovsiienko CC: , , Matan Azrad Date: Wed, 21 Jul 2021 22:37:42 +0800 Message-ID: <20210721143743.24626-16-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721143743.24626-1-xuemingl@nvidia.com> References: <20210616040935.311733-1-xuemingl@nvidia.com> <20210721143743.24626-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b22d11bc-1b70-430e-a18d-08d94c556807 X-MS-TrafficTypeDiagnostic: MN2PR12MB4077: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:883; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3M5XoBO16DtOS9Moe6oawNQe0hKRSl4bE0ZyGxhmmW3iSPItSNabT3cyw80wXWWiNfGOlWfNzJU+d8lNEK8nAS6tTwi3L8L9LOYP8qSZCYPOTfmawDW/P6vFA68U5RQHESfR8ve2iiLCWTWYRfaRTJvR/mLe87YQzzUqGK8KMM0yASHJsphKlmSRCb/nb/MreeLeKbVTLwxKWWb/gaYcwGoPCsvCErxrnu2nGb5nvBvDjiGgYGMKTi9eV6EJE3eoMUT8rRSZOBDw7xZCTva70LuVTOpuiDcn5BIqjDLzIx2n/PaRQeLM2V1La/6WvdZwY6LAlOyhY/ro2Mhgw+MxhLEJSlyqvDDErRv3OURhbM+P+6XQjv//Iu8bsAx4vmNlHUNMVGsrvY10PFAYWwHzWrU0L2+kdwwNXMO+ofOIWFTwGq9MJJJrqnkr4YUbrUgnZAvG3ivUybhdzPdEHhqkeMkwqi7EbW0qbVR4jesOx/1QkBtIpe4Z62bGUuUXpUuBuvA8nO+2P3VrE415YV5vHdbpR6fRAtnMRCfG/y/ErMi0m+0x/LHBj2SjQizM3G9GI/pSdigtBk7i3SJ4STafF/TLFZkgSweO0czaBGR+Kdd0hip1uwtlnWGemd6DDdzkb6JIZa6pxDfUNhe+BklihfdR4ZCEJXxqm7MMwzoPdJdLCYugpUZ+RON/DxocZ5LDWm//hhY9Djo9p7RaCGAv8A== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(396003)(39860400002)(136003)(376002)(46966006)(36840700001)(6636002)(1076003)(7636003)(186003)(16526019)(4326008)(7696005)(107886003)(478600001)(2906002)(8676002)(5660300002)(55016002)(26005)(6862004)(82310400003)(36860700001)(426003)(70586007)(86362001)(336012)(6666004)(8936002)(36756003)(6286002)(37006003)(54906003)(356005)(2616005)(82740400003)(316002)(36906005)(47076005)(70206006)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2021 14:39:54.9318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b22d11bc-1b70-430e-a18d-08d94c556807 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4077 Subject: [dpdk-dev] [PATCH v4 15/16] crypto/mlx5: migrate to common driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To support auxiliary bus, upgrades driver to use mlx5 common driver structure. Signed-off-by: Xueming Li --- drivers/crypto/mlx5/mlx5_crypto.c | 61 ++++++++----------------------- drivers/crypto/mlx5/mlx5_crypto.h | 1 - 2 files changed, 16 insertions(+), 46 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index fc05bb7d46..ea734f4d5c 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -6,12 +6,11 @@ #include #include #include -#include +#include #include #include #include -#include #include #include @@ -977,23 +976,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, } } -/** - * DPDK callback to register a PCI device. - * - * This function spawns crypto device out of a given PCI device. - * - * @param[in] pci_drv - * PCI driver structure (mlx5_crypto_driver). - * @param[in] pci_dev - * PCI device information. - * - * @return - * 0 on success, 1 to skip this driver, a negative errno value otherwise - * and rte_errno is set. - */ static int -mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, - struct rte_pci_device *pci_dev) +mlx5_crypto_dev_probe(struct rte_device *dev) { struct ibv_device *ibv; struct rte_cryptodev *crypto_dev; @@ -1005,28 +989,21 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, struct rte_cryptodev_pmd_init_params init_params = { .name = "", .private_data_size = sizeof(struct mlx5_crypto_priv), - .socket_id = pci_dev->device.numa_node, + .socket_id = dev->numa_node, .max_nb_queue_pairs = RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, }; uint16_t rdmw_wqe_size; int ret; - RTE_SET_USED(pci_drv); if (rte_eal_process_type() != RTE_PROC_PRIMARY) { DRV_LOG(ERR, "Non-primary process type is not supported."); rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_os_get_ibv_device(&pci_dev->addr); - if (ibv == NULL) { - DRV_LOG(ERR, "No matching IB device for PCI slot " - PCI_PRI_FMT ".", pci_dev->addr.domain, - pci_dev->addr.bus, pci_dev->addr.devid, - pci_dev->addr.function); + ibv = mlx5_os_get_ibv_dev(dev); + if (ibv == NULL) return -rte_errno; - } - DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name); ctx = mlx5_glue->dv_open_device(ibv); if (ctx == NULL) { DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); @@ -1041,7 +1018,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -ENOTSUP; } - ret = mlx5_crypto_parse_devargs(pci_dev->device.devargs, &devarg_prms); + ret = mlx5_crypto_parse_devargs(dev->devargs, &devarg_prms); if (ret) { DRV_LOG(ERR, "Failed to parse devargs."); return -rte_errno; @@ -1052,7 +1029,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, DRV_LOG(ERR, "Failed to configure login."); return -rte_errno; } - crypto_dev = rte_cryptodev_pmd_create(ibv->name, &pci_dev->device, + crypto_dev = rte_cryptodev_pmd_create(ibv->name, dev, &init_params); if (crypto_dev == NULL) { DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); @@ -1069,7 +1046,6 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, priv = crypto_dev->data->dev_private; priv->ctx = ctx; priv->login_obj = login; - priv->pci_dev = pci_dev; priv->crypto_dev = crypto_dev; if (mlx5_crypto_hw_global_prepare(priv) != 0) { rte_cryptodev_pmd_destroy(priv->crypto_dev); @@ -1112,13 +1088,13 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, } static int -mlx5_crypto_pci_remove(struct rte_pci_device *pdev) +mlx5_crypto_dev_remove(struct rte_device *dev) { struct mlx5_crypto_priv *priv = NULL; pthread_mutex_lock(&priv_list_lock); TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) - if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0) + if (priv->crypto_dev->device == dev) break; if (priv) TAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next); @@ -1146,24 +1122,19 @@ static const struct rte_pci_id mlx5_crypto_pci_id_map[] = { } }; -static struct mlx5_pci_driver mlx5_crypto_driver = { - .driver_class = MLX5_CLASS_CRYPTO, - .pci_driver = { - .driver = { - .name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME), - }, - .id_table = mlx5_crypto_pci_id_map, - .probe = mlx5_crypto_pci_probe, - .remove = mlx5_crypto_pci_remove, - .drv_flags = 0, - }, +static struct mlx5_class_driver mlx5_crypto_driver = { + .drv_class = MLX5_CLASS_CRYPTO, + .name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME), + .id_table = mlx5_crypto_pci_id_map, + .probe = mlx5_crypto_dev_probe, + .remove = mlx5_crypto_dev_remove, }; RTE_INIT(rte_mlx5_crypto_init) { mlx5_common_init(); if (mlx5_glue != NULL) - mlx5_pci_driver_register(&mlx5_crypto_driver); + mlx5_class_driver_register(&mlx5_crypto_driver); } RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv, diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index e751c9c202..d49b0001f0 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -20,7 +20,6 @@ struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; struct ibv_context *ctx; /* Device context. */ - struct rte_pci_device *pci_dev; struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ volatile uint64_t *uar_addr; -- 2.25.1