From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36D63C6377B for ; Wed, 21 Jul 2021 23:14:17 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 185DB6121E for ; Wed, 21 Jul 2021 23:14:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 185DB6121E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ausil.us Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 51AE381E8F; Thu, 22 Jul 2021 01:14:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ausil.us Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 30A7E80FB4; Thu, 22 Jul 2021 01:14:10 +0200 (CEST) Received: from us-smtp-delivery-44.mimecast.com (us-smtp-delivery-44.mimecast.com [207.211.30.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EF69380FB4 for ; Thu, 22 Jul 2021 01:14:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ausil.us Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=dennis@ausil.us Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-123-iY8LCtdsOBaPRcJwgThEeg-1; Wed, 21 Jul 2021 19:13:59 -0400 X-MC-Unique: iY8LCtdsOBaPRcJwgThEeg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 59ED264AD2; Wed, 21 Jul 2021 23:13:56 +0000 (UTC) Received: from dreyauc.ausil.us.com (unknown [10.22.16.16]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B6F1060583; Wed, 21 Jul 2021 23:13:46 +0000 (UTC) From: Dennis Gilmore To: u-boot@lists.denx.de Cc: dgilmore@redhat.com, Simon Glass , Philipp Tomsich , Kever Yang , Aditya Prayoga , Akash Gajjar , Jagan Teki , Fabio Estevam , Andre Przywara , Patrick Delaunay , Peter Robinson , Tim Harvey , Heiko Schocher , Lokesh Vutla , Dave Gerlach , Neil Armstrong , Hugh Cole-Baker , Jonas Smedegaard Subject: [PATCH] rk3399: Add basic support for helios64 Date: Wed, 21 Jul 2021 18:13:37 -0500 Message-Id: <20210721231339.297097-1-dennis@ausil.us> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dennis@ausil.us X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: ausil.us Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Dennis Gilmore This is a stripped down version of the vendor U-Boot patch by Aditya Prayoga found in the armbian repository. This patch is enough to have the 1G ethernet port, the micro SD card, eMMC, PCIe and UART. It sets uart2 as the default outiput device. the defconfig file has been cleaned up a lot from the vendor version. The device tree file is from the for-next branch of linux-rockchip and targeted for 5.15 needed for SPI, stdout-path, and tsadc enablement Signed-off-by: Dennis Gilmore --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3399-kobol-helios64-u-boot.dtsi | 23 + arch/arm/dts/rk3399-kobol-helios64.dts | 534 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 17 + board/kobol/helios64-rk3399/Kconfig | 17 + board/kobol/helios64-rk3399/MAINTAINERS | 7 + board/kobol/helios64-rk3399/Makefile | 5 + board/kobol/helios64-rk3399/helios64.c | 262 +++++++++ board/kobol/helios64-rk3399/sys_otp.c | 253 +++++++++ board/kobol/helios64-rk3399/sys_otp.h | 15 + board/pine64/rockpro64_rk3399/Kconfig | 2 + configs/helios64-rk3399_defconfig | 114 ++++ include/configs/helios64-rk3399.h | 56 ++ 13 files changed, 1306 insertions(+) create mode 100644 arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-kobol-helios64.dts create mode 100644 board/kobol/helios64-rk3399/Kconfig create mode 100644 board/kobol/helios64-rk3399/MAINTAINERS create mode 100644 board/kobol/helios64-rk3399/Makefile create mode 100644 board/kobol/helios64-rk3399/helios64.c create mode 100644 board/kobol/helios64-rk3399/sys_otp.c create mode 100644 board/kobol/helios64-rk3399/sys_otp.h create mode 100644 configs/helios64-rk3399_defconfig create mode 100644 include/configs/helios64-rk3399.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..2788d7dd7b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) +=3D \ =09rk3399-ficus.dtb \ =09rk3399-firefly.dtb \ =09rk3399-gru-bob.dtb \ +=09rk3399-kobol-helios64.dtb \ =09rk3399-khadas-edge.dtb \ =09rk3399-khadas-edge-captain.dtb \ =09rk3399-khadas-edge-v.dtb \ diff --git a/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi b/arch/arm/dts/= rk3399-kobol-helios64-u-boot.dtsi new file mode 100644 index 0000000000..f534c14b13 --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Aditya Prayoga (aditya@kobol.io) + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { +=09chosen { +=09=09u-boot,spl-boot-order =3D "same-as-spl", &spiflash, &sdmmc, &sdhci; +=09}; + +=09config { +=09=09u-boot,spl-payload-offset =3D <0x60000>; /* @ 384KB */ +=09}; +}; + +&spi1 { +=09spiflash: flash@0 { +=09=09u-boot,dm-pre-reloc; +=09}; +}; diff --git a/arch/arm/dts/rk3399-kobol-helios64.dts b/arch/arm/dts/rk3399-k= obol-helios64.dts new file mode 100644 index 0000000000..63c7681843 --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64.dts @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Aditya Prayoga + */ + +/* + * The Kobol Helios64 is a board designed to operate as a NAS and optional= ly + * ships with an enclosing that can host five 2.5" hard disks. + * + * See https://wiki.kobol.io/helios64/intro/ for further details. + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { +=09model =3D "Kobol Helios64"; +=09compatible =3D "kobol,helios64", "rockchip,rk3399"; + +=09aliases { +=09=09mmc0 =3D &sdmmc; +=09=09mmc1 =3D &sdhci; +=09=09spi1 =3D &spi1; +=09=09spi2 =3D &spi2; +=09=09spi5 =3D &spi5; +=09}; + +=09avdd_0v9_s0: avdd-0v9-s0 { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "avdd_0v9_s0"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <900000>; +=09=09regulator-max-microvolt =3D <900000>; +=09=09vin-supply =3D <&vcc1v8_sys_s3>; +=09}; + +=09avdd_1v8_s0: avdd-1v8-s0 { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "avdd_1v8_s0"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <1800000>; +=09=09regulator-max-microvolt =3D <1800000>; +=09=09vin-supply =3D <&vcc3v3_sys_s3>; +=09}; + +=09chosen { +=09=09stdout-path =3D "serial2:1500000n8"; +=09}; + +=09clkin_gmac: external-gmac-clock { +=09=09compatible =3D "fixed-clock"; +=09=09clock-frequency =3D <125000000>; +=09=09clock-output-names =3D "clkin_gmac"; +=09=09#clock-cells =3D <0>; +=09}; + +=09fan1 { +=09=09/* fan connected to P7 */ +=09=09compatible =3D "pwm-fan"; +=09=09pwms =3D <&pwm0 0 40000 0>; +=09=09cooling-levels =3D <0 80 170 255>; +=09}; + +=09fan2 { +=09=09/* fan connected to P6 */ +=09=09compatible =3D "pwm-fan"; +=09=09pwms =3D <&pwm1 0 40000 0>; +=09=09cooling-levels =3D <0 80 170 255>; +=09}; + +=09leds { +=09=09compatible =3D "gpio-leds"; +=09=09pinctrl-names =3D "default"; +=09=09pinctrl-0 =3D <&sys_grn_led_on &sys_red_led_on>; + +=09=09led-0 { +=09=09=09label =3D "helios64:green:status"; +=09=09=09gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +=09=09=09default-state =3D "on"; +=09=09}; + +=09=09led-1 { +=09=09=09label =3D "helios64:red:fault"; +=09=09=09gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +=09=09=09default-state =3D "keep"; +=09=09}; +=09}; + +=09pcie_power: pcie-power { +=09=09compatible =3D "regulator-fixed"; +=09=09enable-active-high; +=09=09gpio =3D <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +=09=09pinctrl-0 =3D <&pcie_pwr>; +=09=09pinctrl-names =3D "default"; +=09=09regulator-boot-on; +=09=09regulator-name =3D "pcie_power"; +=09=09startup-delay-us =3D <10000>; +=09=09vin-supply =3D <&vcc5v0_perdev>; +=09}; + +=09vcc1v8_sys_s0: vcc1v8-sys-s0 { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc1v8_sys_s0"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <1800000>; +=09=09regulator-max-microvolt =3D <1800000>; +=09=09vin-supply =3D <&vcc1v8_sys_s3>; +=09}; + +=09vcc3v0_sd: vcc3v0-sd { +=09=09compatible =3D "regulator-fixed"; +=09=09enable-active-high; +=09=09gpio =3D <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +=09=09regulator-name =3D "vcc3v0_sd"; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <3000000>; +=09=09regulator-max-microvolt =3D <3000000>; +=09=09pinctrl-names =3D "default"; +=09=09pinctrl-0 =3D <&sdmmc0_pwr_h>; +=09=09vin-supply =3D <&vcc3v3_sys_s3>; +=09}; + +=09vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc3v3_sys_s3"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <3300000>; +=09=09regulator-max-microvolt =3D <3300000>; +=09=09vin-supply =3D <&vcc5v0_sys>; + +=09=09regulator-state-mem { +=09=09=09regulator-on-in-suspend; +=09=09}; +=09}; + +=09vcc5v0_perdev: vcc5v0-perdev { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc5v0_perdev"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <5000000>; +=09=09regulator-max-microvolt =3D <5000000>; +=09=09vin-supply =3D <&vcc12v_dcin_bkup>; +=09}; + +=09vcc5v0_sys: vcc5v0-sys { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc5v0_sys"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <5000000>; +=09=09regulator-max-microvolt =3D <5000000>; +=09=09vin-supply =3D <&vcc12v_dcin_bkup>; + +=09=09regulator-state-mem { +=09=09=09regulator-on-in-suspend; +=09=09}; +=09}; + +=09vcc5v0_usb: vcc5v0-usb { +=09=09compatible =3D "regulator-fixed"; +=09=09enable-active-high; +=09=09gpio =3D <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; +=09=09pinctrl-names =3D "default"; +=09=09pinctrl-0 =3D <&vcc5v0_usb_en>; +=09=09regulator-name =3D "vcc5v0_usb"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <5000000>; +=09=09regulator-max-microvolt =3D <5000000>; +=09=09vin-supply =3D <&vcc5v0_perdev>; +=09}; + +=09vcc12v_dcin: vcc12v-dcin { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc12v_dcin"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <12000000>; +=09=09regulator-max-microvolt =3D <12000000>; +=09}; + +=09vcc12v_dcin_bkup: vcc12v-dcin-bkup { +=09=09compatible =3D "regulator-fixed"; +=09=09regulator-name =3D "vcc12v_dcin_bkup"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <12000000>; +=09=09regulator-max-microvolt =3D <12000000>; +=09=09vin-supply =3D <&vcc12v_dcin>; +=09}; +}; + +/* + * The system doesn't run stable with cpu freq enabled, so disallow the lo= wer + * frequencies until this problem is properly understood and resolved. + */ +&cluster0_opp { +=09/delete-node/ opp00; +=09/delete-node/ opp01; +=09/delete-node/ opp02; +=09/delete-node/ opp03; +=09/delete-node/ opp04; +}; + +&cluster1_opp { +=09/delete-node/ opp00; +=09/delete-node/ opp01; +=09/delete-node/ opp02; +=09/delete-node/ opp03; +=09/delete-node/ opp04; +=09/delete-node/ opp05; +=09/delete-node/ opp06; +}; + +&cpu_b0 { +=09cpu-supply =3D <&vdd_cpu_b>; +}; + +&cpu_b1 { +=09cpu-supply =3D <&vdd_cpu_b>; +}; + +&cpu_l0 { +=09cpu-supply =3D <&vdd_cpu_l>; +}; + +&cpu_l1 { +=09cpu-supply =3D <&vdd_cpu_l>; +}; + +&cpu_l2 { +=09cpu-supply =3D <&vdd_cpu_l>; +}; + +&cpu_l3 { +=09cpu-supply =3D <&vdd_cpu_l>; +}; + +&emmc_phy { +=09status =3D "okay"; +}; + +&gmac { +=09assigned-clock-parents =3D <&clkin_gmac>; +=09assigned-clocks =3D <&cru SCLK_RMII_SRC>; +=09clock_in_out =3D "input"; +=09phy-mode =3D "rgmii"; +=09phy-supply =3D <&vcc_lan>; +=09pinctrl-names =3D "default"; +=09pinctrl-0 =3D <&rgmii_pins &gphy_reset>; +=09rx_delay =3D <0x20>; +=09tx_delay =3D <0x28>; +=09snps,reset-active-low; +=09snps,reset-delays-us =3D <0 10000 50000>; +=09snps,reset-gpio =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +=09status =3D "okay"; +}; + +&i2c0 { +=09clock-frequency =3D <400000>; +=09i2c-scl-rising-time-ns =3D <168>; +=09i2c-scl-falling-time-ns =3D <4>; +=09status =3D "okay"; + +=09rk808: pmic@1b { +=09=09compatible =3D "rockchip,rk808"; +=09=09reg =3D <0x1b>; +=09=09interrupt-parent =3D <&gpio0>; +=09=09interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; +=09=09clock-output-names =3D "xin32k", "rk808-clkout2"; +=09=09pinctrl-names =3D "default"; +=09=09pinctrl-0 =3D <&pmic_int_l>; +=09=09vcc1-supply =3D <&vcc5v0_sys>; +=09=09vcc2-supply =3D <&vcc5v0_sys>; +=09=09vcc3-supply =3D <&vcc5v0_sys>; +=09=09vcc4-supply =3D <&vcc5v0_sys>; +=09=09vcc6-supply =3D <&vcc5v0_sys>; +=09=09vcc7-supply =3D <&vcc5v0_sys>; +=09=09vcc8-supply =3D <&vcc3v3_sys_s3>; +=09=09vcc9-supply =3D <&vcc5v0_sys>; +=09=09vcc10-supply =3D <&vcc5v0_sys>; +=09=09vcc11-supply =3D <&vcc5v0_sys>; +=09=09vcc12-supply =3D <&vcc3v3_sys_s3>; +=09=09vddio-supply =3D <&vcc3v0_s3>; +=09=09wakeup-source; +=09=09#clock-cells =3D <1>; + +=09=09regulators { +=09=09=09vdd_cpu_l: DCDC_REG2 { +=09=09=09=09regulator-name =3D "vdd_cpu_l"; +=09=09=09=09regulator-always-on; +=09=09=09=09regulator-boot-on; +=09=09=09=09regulator-min-microvolt =3D <750000>; +=09=09=09=09regulator-max-microvolt =3D <1350000>; +=09=09=09=09regulator-ramp-delay =3D <6001>; + +=09=09=09=09regulator-state-mem { +=09=09=09=09=09regulator-off-in-suspend; +=09=09=09=09}; +=09=09=09}; + +=09=09=09vcc1v8_sys_s3: DCDC_REG4 { +=09=09=09=09regulator-name =3D "vcc1v8_sys_s3"; +=09=09=09=09regulator-always-on; +=09=09=09=09regulator-boot-on; +=09=09=09=09regulator-min-microvolt =3D <1800000>; +=09=09=09=09regulator-max-microvolt =3D <1800000>; + +=09=09=09=09regulator-state-mem { +=09=09=09=09=09regulator-on-in-suspend; +=09=09=09=09=09regulator-suspend-microvolt =3D <1800000>; +=09=09=09=09}; +=09=09=09}; + +=09=09=09vcc_sdio_s0: LDO_REG4 { +=09=09=09=09regulator-name =3D "vcc_sdio_s0"; +=09=09=09=09regulator-always-on; +=09=09=09=09regulator-boot-on; +=09=09=09=09regulator-min-microvolt =3D <1800000>; +=09=09=09=09regulator-max-microvolt =3D <3000000>; + +=09=09=09=09regulator-state-mem { +=09=09=09=09=09regulator-on-in-suspend; +=09=09=09=09=09regulator-suspend-microvolt =3D <3000000>; +=09=09=09=09}; +=09=09=09}; + +=09=09=09vcc3v0_s3: LDO_REG8 { +=09=09=09=09regulator-name =3D "vcc3v0_s3"; +=09=09=09=09regulator-always-on; +=09=09=09=09regulator-boot-on; +=09=09=09=09regulator-min-microvolt =3D <3000000>; +=09=09=09=09regulator-max-microvolt =3D <3000000>; + +=09=09=09=09regulator-state-mem { +=09=09=09=09=09regulator-on-in-suspend; +=09=09=09=09=09regulator-suspend-microvolt =3D <3000000>; +=09=09=09=09}; +=09=09=09}; +=09=09}; +=09}; + +=09vdd_cpu_b: regulator@40 { +=09=09compatible =3D "silergy,syr827"; +=09=09reg =3D <0x40>; +=09=09fcs,suspend-voltage-selector =3D <1>; +=09=09regulator-name =3D "vdd_cpu_b"; +=09=09regulator-always-on; +=09=09regulator-boot-on; +=09=09regulator-min-microvolt =3D <712500>; +=09=09regulator-max-microvolt =3D <1500000>; +=09=09regulator-ramp-delay =3D <1000>; +=09=09vin-supply =3D <&vcc5v0_sys>; + +=09=09regulator-state-mem { +=09=09=09regulator-off-in-suspend; +=09=09}; +=09}; +}; + +&i2c2 { +=09clock-frequency =3D <400000>; +=09i2c-scl-rising-time-ns =3D <160>; +=09i2c-scl-falling-time-ns =3D <30>; +=09status =3D "okay"; + +=09temp@4c { +=09=09compatible =3D "national,lm75"; +=09=09reg =3D <0x4c>; +=09}; +}; + +&io_domains { +=09audio-supply =3D <&vcc1v8_sys_s0>; +=09bt656-supply =3D <&vcc1v8_sys_s0>; +=09gpio1830-supply =3D <&vcc3v0_s3>; +=09sdmmc-supply =3D <&vcc_sdio_s0>; +=09status =3D "okay"; +}; + +&pcie_phy { +=09status =3D "okay"; +}; + +&pcie0 { +=09num-lanes =3D <2>; +=09status =3D "okay"; + +=09vpcie12v-supply =3D <&vcc12v_dcin>; +=09vpcie3v3-supply =3D <&pcie_power>; +=09vpcie1v8-supply =3D <&avdd_1v8_s0>; +=09vpcie0v9-supply =3D <&avdd_0v9_s0>; +}; + +&pinctrl { +=09gmac { +=09=09gphy_reset: gphy-reset { +=09=09=09rockchip,pins =3D <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; +=09=09}; +=09}; + +=09leds { +=09=09sys_grn_led_on: sys-grn-led-on { +=09=09=09rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; +=09=09}; + +=09=09sys_red_led_on: sys-red-led-on { +=09=09=09rockchip,pins =3D <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; +=09=09}; +=09}; + +=09pcie { +=09=09pcie_pwr: pcie-pwr { +=09=09=09rockchip,pins =3D +=09=09=09=09<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; +=09=09}; +=09}; + +=09pmic { +=09=09pmic_int_l: pmic-int-l { +=09=09=09rockchip,pins =3D <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +=09=09}; +=09}; + +=09power { +=09=09vcc5v0_usb_en: vcc5v0-usb-en { +=09=09=09rockchip,pins =3D <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +=09=09}; +=09}; + +=09vcc3v0-sd { +=09=09sdmmc0_pwr_h: sdmmc0-pwr-h { +=09=09=09rockchip,pins =3D <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; +=09=09}; +=09}; +}; + +&pmu_io_domains { +=09pmu1830-supply =3D <&vcc3v0_s3>; +=09status =3D "okay"; +}; + +&pwm0 { +=09/* pwm-fan on P7 */ +=09status =3D "okay"; +}; + +&pwm1 { +=09/* pwm-fan on P6 */ +=09status =3D "okay"; +}; + +&sdhci { +=09bus-width =3D <8>; +=09mmc-hs200-1_8v; +=09non-removable; +=09vqmmc-supply =3D <&vcc1v8_sys_s0>; +=09status =3D "okay"; +}; + +&sdmmc { +=09bus-width =3D <4>; +=09cap-sd-highspeed; +=09cd-gpios =3D <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; +=09disable-wp; +=09pinctrl-names =3D "default"; +=09pinctrl-0 =3D <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +=09vmmc-supply =3D <&vcc3v0_sd>; +=09vqmmc-supply =3D <&vcc_sdio_s0>; +=09status =3D "okay"; +}; + +&spi1 { +=09status =3D "okay"; + +=09spiflash: flash@0 { +=09=09compatible =3D "jedec,spi-nor"; +=09=09reg =3D <0x0>; +=09=09spi-max-frequency =3D <25000000>; +=09=09status =3D "okay"; +=09=09m25p,fast-read; +=09}; +}; + +/* UEXT connector */ +&spi2 { +=09status =3D "okay"; +}; + +&spi5 { +=09status =3D "okay"; +}; + +&tcphy1 { +=09/* phy for &usbdrd_dwc3_1 */ +=09status =3D "okay"; +}; + +&tsadc { +=09/* tshut mode 0:CRU 1:GPIO */ +=09rockchip,hw-tshut-mode =3D <1>; +=09/* tshut polarity 0:LOW 1:HIGH */ +=09rockchip,hw-tshut-polarity =3D <1>; +=09status =3D "okay"; +}; + +&u2phy1 { +=09status =3D "okay"; + +=09otg-port { +=09=09/* phy for &usbdrd_dwc3_1 */ +=09=09phy-supply =3D <&vcc5v0_usb>; +=09=09status =3D "okay"; +=09}; +}; + +&uart2 { +=09status =3D "okay"; +}; + +&usbdrd3_1 { +=09status =3D "okay"; + +=09usb@fe900000 { +=09=09dr_mode =3D "host"; +=09=09status =3D "okay"; +=09}; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip= /rk3399/Kconfig index 17628f9171..f699355dd6 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,22 @@ config TARGET_PINEBOOK_PRO_RK3399 =09 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, =09 1920*1080 screen and all the usual laptop features. =20 +config TARGET_HELIOS64_RK3399 +=09bool "Kobol Innovations Helios64" +=09select BOARD_LATE_INIT +=09help +=09 Helios64 is a Network Attached Storage board based on Rockchip RK3399= . + +=09 Key features of the Helios64 include: +=09 * on-board PCIe to 5 Ports SATA Controller JMB585 +=09 * on-board USB 3.0 hub (3x USB 3.0 host) +=09 * USB Type-C (Support DisplayPort Alt Mode) +=09 * on-board 1 Gigabit Ethernet +=09 * on-board 2.5 Gigabit Ethernet (Realtek RTL8156) +=09 * on-board eMMC +=09 * on-board LPDDR4 +=09 * SPI, I2C, UART, GPIO + config TARGET_PUMA_RK3399 =09bool "Theobroma Systems RK3399-Q7 (Puma)" =09help @@ -153,6 +169,7 @@ endif # BOOTCOUNT_LIMIT =20 source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" +source "board/kobol/helios64-rk3399/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" diff --git a/board/kobol/helios64-rk3399/Kconfig b/board/kobol/helios64-rk3= 399/Kconfig new file mode 100644 index 0000000000..bccedfc52e --- /dev/null +++ b/board/kobol/helios64-rk3399/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ + +if TARGET_HELIOS64_RK3399 + +config SYS_BOARD +=09default "helios64-rk3399" + +config SYS_VENDOR +=09default "kobol" + +config SYS_CONFIG_NAME +=09default "helios64-rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy +=09def_bool y + +endif diff --git a/board/kobol/helios64-rk3399/MAINTAINERS b/board/kobol/helios64= -rk3399/MAINTAINERS new file mode 100644 index 0000000000..1af7dd37c1 --- /dev/null +++ b/board/kobol/helios64-rk3399/MAINTAINERS @@ -0,0 +1,7 @@ +HELIOS64 BOARD +M:=09Aditya Prayoga +M:=09Dennis Gilmore +S:=09Maintained +F:=09board/kobol/helios64-rk3399/ +F:=09include/configs/helios64-rk3399.h +F:=09configs/helios64_defconfig diff --git a/board/kobol/helios64-rk3399/Makefile b/board/kobol/helios64-rk= 3399/Makefile new file mode 100644 index 0000000000..ab34245a6d --- /dev/null +++ b/board/kobol/helios64-rk3399/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Aditya Prayoga + +obj-y=09:=3D helios64.o sys_otp.o diff --git a/board/kobol/helios64-rk3399/helios64.c b/board/kobol/helios64-= rk3399/helios64.c new file mode 100644 index 0000000000..1fe948eec4 --- /dev/null +++ b/board/kobol/helios64-rk3399/helios64.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Aditya Prayoga (aditya@kobol.io) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sys_otp.h" + +#ifndef CONFIG_TPL_BUILD +int board_early_init_f(void) +{ +#ifdef CONFIG_SPL_BUILD +#define GPIO0_BASE 0xff720000 +#define GRF_BASE=09=090xff770000 +=09struct rk3399_grf_regs * const grf =3D (void *)GRF_BASE; +=09struct rockchip_gpio_regs * const gpio =3D (void *)GPIO0_BASE; + +=09/* Turn ON status LED. At this stage, FDT & DM is not initialized yet *= / +=09spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); +#endif +=09return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ +=09read_otp_data(); +=09return 0; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +#define GRF_IO_VSEL_BT565_SHIFT=09=090 +#define GRF_IO_VSEL_AUDIO_SHIFT=09=091 +#define GRF_IO_VSEL_SDMMC_SHIFT=09=092 +#define GRF_IO_VSEL_GPIO1830_SHIFT=093 + +#define PMUGRF_CON0_VSEL_SHIFT=09=098 +#define PMUGRF_CON0_PMU1830_VOL_SHIFT 9 +static void setup_iodomain(void) +{ +=09struct rk3399_grf_regs *grf =3D +=09=09syscon_get_first_range(ROCKCHIP_SYSCON_GRF); +=09struct rk3399_pmugrf_regs *pmugrf =3D +=09=09syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + +=09/* BT565 is in 1.8v domain */ +=09rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + +=09/* AUDIO is in 1.8v domain */ +=09rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_AUDIO_SHIFT); + +=09/* SDMMC is in 3.0v domain */ +=09rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_SDMMC_SHIFT); + +=09/* GPIO1830 is in 3.0v domain */ +=09rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_GPIO1830_SHIFT); + +=09/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ +=09rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +=09rk_setreg(&pmugrf->soc_con0, 0 << PMUGRF_CON0_PMU1830_VOL_SHIFT); +} + +/* + * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. + * + * If bootsource is uSD-card we can assume that we want to use the + * SD-Card instead of the eMMC as first boot_target for distroboot. + * We only want to swap the defaults and not any custom environment a + * user has set. We exit early if a changed boot_targets environment + * is detected. + */ +static int setup_boottargets(void) +{ +=09const char *boot_device =3D +=09=09ofnode_read_chosen_string("u-boot,spl-boot-device"); +=09char *env_default, *env; + +=09if (!boot_device) { +=09=09debug("%s: /chosen/u-boot,spl-boot-device not set\n", +=09=09 __func__); +=09=09return -1; +=09} +=09debug("%s: booted from %s\n", __func__, boot_device); + +=09env_default =3D env_get_default("boot_targets"); +=09env =3D env_get("boot_targets"); +=09if (!env) { +=09=09debug("%s: boot_targets does not exist\n", __func__); +=09=09return -1; +=09} +=09debug("%s: boot_targets current: %s - default: %s\n", +=09=09__func__, env, env_default); + +=09if (strcmp(env_default, env) !=3D 0) { +=09=09debug("%s: boot_targets not default, don't change it\n", +=09=09=09__func__); +=09=09return 0; +=09} + +=09/* +=09 * Only run, if booting from mmc1 (i.e. /mmc@fe320000) and +=09 * only consider cases where the default boot-order first +=09 * tries to boot from mmc0 (eMMC) and then from mmc1 +=09 * (i.e. external SD). +=09 * +=09 * In other words: the SD card will be moved to earlier in the +=09 * order, if U-Boot was also loaded from the SD-card. +=09 */ +=09if (!strcmp(boot_device, "/mmc@fe320000")) { +=09=09char *mmc0, *mmc1; + +=09=09debug("%s: booted from SD-Card\n", __func__); +=09=09mmc0 =3D strstr(env, "mmc0"); +=09=09mmc1 =3D strstr(env, "mmc1"); + +=09=09if (!mmc0 || !mmc1) { +=09=09=09debug("%s: only one mmc boot_target found\n", __func__); +=09=09=09return -1; +=09=09} + +=09=09/* +=09=09 * If mmc0 comes first in the boot order, we need to change +=09=09 * the strings to make mmc1 first. +=09=09 */ +=09=09if (mmc0 < mmc1) { +=09=09=09mmc0[3] =3D '1'; +=09=09=09mmc1[3] =3D '0'; +=09=09=09debug("%s: set boot_targets to: %s\n", __func__, env); +=09=09=09env_set("boot_targets", env); +=09=09} +=09} + +=09return 0; +} + +static void setup_leds(void) +{ +=09struct udevice *dev; + +=09led_get_by_label("helios64:green:status", &dev); +=09led_set_state(dev, LEDST_OFF); +=09mdelay(250); +=09led_set_state(dev, LEDST_ON); +} + +int misc_init_r(void) +{ +=09const u32 cpuid_offset =3D 0x7; +=09const u32 cpuid_length =3D 0x10; +=09u8 cpuid[cpuid_length]; +=09int ret; + +=09setup_iodomain(); +=09set_board_info(); + +=09ret =3D rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); +=09if (ret) +=09=09return ret; + +=09ret =3D rockchip_cpuid_set(cpuid, cpuid_length); +=09if (ret) +=09=09return ret; + +=09if (mac_read_from_otp()) +=09=09ret =3D rockchip_setup_macaddr(); + +=09setup_boottargets(); +=09setup_leds(); + +=09return ret; +} +#endif + +#ifdef CONFIG_LAST_STAGE_INIT +static void auto_power_enable(void) +{ +=09struct gpio_desc *enable, *clock; + +=09if (gpio_hog_lookup_name("AUTO_ON_EN_D", &enable)) { +=09=09debug("Fail to get AUTO_ON_EN_D\n"); +=09=09return; +=09} + +=09if (gpio_hog_lookup_name("AUTO_ON_EN_CLK", &clock)) { +=09=09debug("Fail to get AUTO_ON_EN_CLK\n"); +=09=09return; +=09} + +=09dm_gpio_set_value(enable, 1); +=09dm_gpio_set_value(clock, 1); +=09mdelay(10); +=09dm_gpio_set_value(clock, 0); +} + +int last_stage_init(void) +{ +=09auto_power_enable(); + +#ifdef CONFIG_PCI +=09scsi_scan(true); +#endif + +=09return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +int checkboard(void) +{ +=09int major, minor; + +=09printf("Revision: "); + +=09if (!get_revision(&major, &minor)) +=09=09printf("%i.%i - %s\n", major, minor, get_variant()); +=09else +=09=09printf("UNKNOWN\n"); + +=09return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ +=09char *env; + +=09env =3D env_get("board_rev"); +=09if (env) +=09=09fdt_setprop_string(blob, fdt_path_offset(blob, "/"), +=09=09=09"kobol,board-rev", env); + +=09env =3D env_get("cpuid#"); +=09if (env) +=09=09fdt_setprop_string(blob, fdt_path_offset(blob, "/"), +=09=09=09"kobol,cpu-id", env); + +=09return 0; +} +#endif diff --git a/board/kobol/helios64-rk3399/sys_otp.c b/board/kobol/helios64-r= k3399/sys_otp.c new file mode 100644 index 0000000000..13f3401e41 --- /dev/null +++ b/board/kobol/helios64-rk3399/sys_otp.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Aditya Prayoga (aditya@kobol.io) + */ + +#include +#include +#include +#include +#include +#include + +#include "sys_otp.h" + +#define OTP_DEVICE_BUS 0 +#define OTP_DEVICE_CS 0 +#define MAX_NUM_PORTS=092 + +enum board_variant { +=09BOARD_VARIANT_INVALID =3D 0, +=09BOARD_VARIANT_ENG_SAMPLE, +=09BOARD_VARIANT_4G_PROD_NO_ECC, +=09BOARD_VARIANT_MAX +}; + +struct __attribute__ ((__packed__)) otp_data_t { +=09u8 magic[8]; +=09u8 part_num[16]; +=09u8 variant; +=09u8 revision; +=09u8 serial_num[6]; +=09u8 mfg_year[2]; +=09u8 mfg_month; +=09u8 mfg_day; +=09u8 mac_addr[MAX_NUM_PORTS][6]; +=09u8 reserved[204]; +=09u32 checksum; +} otp; + +static struct spi_slave *slave; +static int has_been_read =3D 0; +static int data_valid =3D 0; + +static inline int is_data_valid(void) +{ +=09return data_valid; +} + +static inline int is_valid_header(void) +{ +=09if ((otp.magic[0] =3D=3D 'H') || (otp.magic[1] =3D=3D '6') || +=09=09(otp.magic[2] =3D=3D '4') || (otp.magic[3] =3D=3D 'N') || +=09=09(otp.magic[4] =3D=3D 'P') || (otp.magic[5] =3D=3D 'V') || +=09=09(otp.magic[6] =3D=3D '1') || (otp.magic[7] =3D=3D 0)) + +=09=09return 1; + +=09return 0; +} + +static int init_system_otp(int bus, int cs) +{ +=09int ret; +=09char name[30], *str; +=09struct udevice *dev; + +=09snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); +=09str =3D strdup(name); +=09if (!str) +=09=09return -ENOMEM; +=09ret =3D spi_get_bus_and_cs(bus, cs, 25000000, CONFIG_DEFAULT_SPI_MODE, = "spi_generic_drv", +=09=09=09=09 str, &dev, &slave); +=09return ret; +} + +#ifdef DEBUG +/** + * show_otp_data - display the contents of the OTP register + */ +static void show_otp_data(void) +{ +=09u32 i; +=09u32 crc; + +=09const char* var_str[BOARD_VARIANT_MAX] =3D { +=09=09=09"Invalid variant", +=09=09=09"Engineering Sample", +=09=09=09"Production - 4GB non ECC" +=09}; + +=09printf("\n"); +=09printf("Register dump: (%lu bytes)\n", sizeof(otp)); +=09for (i =3D 0; i < sizeof(otp); i++) { +=09=09if ((i % 16) =3D=3D 0) +=09=09=09printf("%02X: ", i); +=09=09printf("%02X ", ((u8 *)&otp)[i]); +=09=09if (((i % 16) =3D=3D 15) || (i =3D=3D sizeof(otp) - 1)) +=09=09=09printf("\n"); +=09} + +=09if (!is_valid_header()) +=09=09return; + +=09printf("Part Number: %s\n", otp.part_num); +=09printf("Variant: %s\n", var_str[otp.variant]); +=09printf("Revision: %x.%x\n", (otp.revision & 0xf0) >> 4, otp.revision & = 0x0f); +=09printf("Serial Number: %012llx\n", *((uint64_t*) otp.serial_num) & +=09=090xFFFFFFFFFFFF); +=09printf("Manufacturing Date: %02X-%02X-%04X (DD-MM-YYYY)\n", otp.mfg_day= , +=09=09otp.mfg_month, *(u16*) otp.mfg_year); + +=09printf("1GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", +=09=09otp.mac_addr[0][0], otp.mac_addr[0][1], otp.mac_addr[0][2], +=09=09otp.mac_addr[0][3], otp.mac_addr[0][4], otp.mac_addr[0][5]); + +=09printf("2.5GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", +=09=09otp.mac_addr[1][0], otp.mac_addr[1][1], otp.mac_addr[1][2], +=09=09otp.mac_addr[1][3], otp.mac_addr[1][4], otp.mac_addr[1][5]); + +=09crc =3D crc32(0, (void *)&otp, sizeof(otp) - 4); + +=09if (crc =3D=3D le32_to_cpu(otp.checksum)) +=09=09printf("CRC: %08x\n\n", le32_to_cpu(otp.checksum)); +=09else +=09=09printf("CRC: %08x (should be %08x)\n\n", +=09=09=09 le32_to_cpu(otp.checksum), crc); + +} +#endif + +int read_otp_data(void) +{ +=09int ret; +=09u8 dout[5]; + +=09if (has_been_read) { +=09=09if (is_data_valid()) +=09=09=09return 0; +=09=09else +=09=09=09goto data_invalid; +=09} + +=09ret =3D init_system_otp(OTP_DEVICE_BUS, OTP_DEVICE_CS); +=09if (ret) +=09=09return ret; + +=09ret =3D spi_claim_bus(slave); +=09if (ret) { +=09=09debug("SPI: Failed to claim SPI bus: %d\n", ret); +=09=09return ret; +=09} + +=09dout[0] =3D 0x48; +=09dout[1] =3D 0x00; +=09dout[2] =3D 0x10; /* Security Register #1 */ +=09dout[3] =3D 0x00; +=09dout[4] =3D 0x00; /* Dummy Byte */ + +=09ret =3D spi_write_then_read(slave, dout, sizeof(dout), NULL, (u8 *)&otp= , +=09=09=09sizeof(otp)); + +=09spi_release_bus(slave); +#ifdef DEBUG +=09show_otp_data(); +#endif + +=09has_been_read =3D (ret =3D=3D 0) ? 1 : 0; +=09if (!is_valid_header()) +=09=09goto data_invalid; + +=09if (crc32(0, (void *)&otp, sizeof(otp) - 4) =3D=3D +=09=09le32_to_cpu(otp.checksum)) +=09=09data_valid =3D 1; + +=09if (!is_data_valid()) +=09=09goto data_invalid; + +=09return 0; + +data_invalid: +=09printf("Invalid board ID data!\n"); +=09return -1; +} + +int get_revision(int *major, int *minor) +{ +=09if (!is_data_valid()) +=09=09return -1; + +=09*major =3D (otp.revision & 0xf0) >> 4; +=09*minor =3D otp.revision & 0x0f; + +=09return 0; +} + +const char *get_variant(void) +{ +=09const char* var_str[BOARD_VARIANT_MAX] =3D { +=09=09"Unknown", +=09=09"Engineering Sample", +=09=09"4GB non ECC" +=09}; + +=09if ((otp.variant < BOARD_VARIANT_ENG_SAMPLE) || +=09=09(otp.variant >=3D BOARD_VARIANT_MAX)) +=09=09return var_str[0]; + +=09return var_str[otp.variant]; +} + +void set_board_info(void) +{ +=09char env_str[13]; + +=09if (!is_data_valid()) +=09=09return; + +=09snprintf(env_str, sizeof(env_str), "%i.%i", (otp.revision & 0xf0) >> 4,= otp.revision & 0x0f); +=09env_set("board_rev", env_str); + +=09sprintf(env_str, "%012llx", *((uint64_t*) otp.serial_num) & +=09=090xFFFFFFFFFFFF); + +=09env_set("serial#", env_str); +} + +int mac_read_from_otp(void) +{ +=09unsigned int i; +=09int ret; + +=09if (!is_data_valid()) +=09=09return -1; + +=09for (i =3D 0; i < MAX_NUM_PORTS; i++) { +=09=09char enetvar[9]; + +=09=09sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + +=09=09if (!is_valid_ethaddr(otp.mac_addr[i])) { +=09=09=09debug("Not valid %s!\n", enetvar); +=09=09=09continue; +=09=09} + +=09=09/* Only initialize environment variables that are blank +=09=09 * (i.e. have not yet been set) +=09=09 */ +=09=09if (!env_get(enetvar)) +=09=09=09eth_env_set_enetaddr(enetvar, otp.mac_addr[i]); +=09} + +=09return ret; +} diff --git a/board/kobol/helios64-rk3399/sys_otp.h b/board/kobol/helios64-r= k3399/sys_otp.h new file mode 100644 index 0000000000..779e5b38dc --- /dev/null +++ b/board/kobol/helios64-rk3399/sys_otp.h @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Aditya Prayoga (aditya@kobol.io) + */ + +#ifndef __HELIOS64_RK3399_SYS_OTP_H +#define __HELIOS64_RK3399_SYS_OTP_H + +int read_otp_data(void); +void set_board_info(void); +int get_revision(int *major, int *minor); +const char *get_variant(void); +int mac_read_from_otp(void); + +#endif diff --git a/board/pine64/rockpro64_rk3399/Kconfig b/board/pine64/rockpro64= _rk3399/Kconfig index 3353f1fd09..d7a4f83f0c 100644 --- a/board/pine64/rockpro64_rk3399/Kconfig +++ b/board/pine64/rockpro64_rk3399/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + if TARGET_ROCKPRO64_RK3399 =20 config SYS_BOARD diff --git a/configs/helios64-rk3399_defconfig b/configs/helios64-rk3399_de= fconfig new file mode 100644 index 0000000000..d5938badca --- /dev/null +++ b/configs/helios64-rk3399_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=3Dy +CONFIG_ARCH_ROCKCHIP=3Dy +CONFIG_SYS_TEXT_BASE=3D0x00200000 +CONFIG_NR_DRAM_BANKS=3D1 +CONFIG_SPL_GPIO_SUPPORT=3Dy +CONFIG_ENV_SIZE=3D0x8000 +CONFIG_ENV_OFFSET=3D0x3F8000 +CONFIG_ROCKCHIP_RK3399=3Dy +CONFIG_TARGET_HELIOS64_RK3399=3Dy +CONFIG_DEBUG_UART_BASE=3D0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=3D24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=3Dy +CONFIG_SPL_SPI_SUPPORT=3Dy +CONFIG_DEFAULT_DEVICE_TREE=3D"rk3399-kobol-helios64" +CONFIG_DEBUG_UART=3Dy +CONFIG_AHCI=3Dy +CONFIG_USE_PREBOOT=3Dy +CONFIG_DEFAULT_FDT_FILE=3D"rockchip/rk3399-kobol-helios64.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=3Dy +CONFIG_MISC_INIT_R=3Dy +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=3Dy +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=3D0x10000 +CONFIG_SPL_SPI_LOAD=3Dy +CONFIG_TPL=3Dy +CONFIG_CMD_BOOTZ=3Dy +CONFIG_CMD_GPT=3Dy +CONFIG_CMD_I2C=3Dy +CONFIG_CMD_MMC=3Dy +CONFIG_CMD_PCI=3Dy +CONFIG_CMD_POWEROFF=3Dy +CONFIG_CMD_READ=3Dy +CONFIG_CMD_SPI=3Dy +CONFIG_CMD_USB=3Dy +CONFIG_CMD_ROCKUSB=3Dy +CONFIG_CMD_USB_MASS_STORAGE=3Dy +CONFIG_CMD_TIME=3Dy +CONFIG_CMD_PMIC=3Dy +CONFIG_CMD_REGULATOR=3Dy +CONFIG_CMD_FS_UUID=3Dy +CONFIG_PARTITION_TYPE_GUID=3Dy +CONFIG_SPL_OF_CONTROL=3Dy +CONFIG_OF_SPL_REMOVE_PROPS=3D"pinctrl-0 pinctrl-names clock-names interrup= t-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_SPI_FLASH=3Dy +CONFIG_SYS_RELOC_GD_ENV_ADDR=3Dy +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=3Dy +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SCSI_AHCI=3Dy +CONFIG_AHCI_PCI=3Dy +CONFIG_GPIO_HOG=3Dy +CONFIG_SPL_DM_SEQ_ALIAS=3Dy +CONFIG_ROCKCHIP_GPIO=3Dy +CONFIG_DM_PCA953X=3Dy +CONFIG_I2C_SET_DEFAULT_BUS_NUM=3Dy +CONFIG_I2C_DEFAULT_BUS_NUMBER=3D0x8 +CONFIG_SYS_I2C_ROCKCHIP=3Dy +CONFIG_LED=3Dy +CONFIG_LED_GPIO=3Dy +CONFIG_MISC=3Dy +CONFIG_ROCKCHIP_EFUSE=3Dy +CONFIG_ROCKCHIP_OTP=3Dy +CONFIG_MMC_DW=3Dy +CONFIG_MMC_DW_ROCKCHIP=3Dy +CONFIG_MMC_SDHCI=3Dy +CONFIG_MMC_SDHCI_ROCKCHIP=3Dy +CONFIG_SF_DEFAULT_BUS=3D1 +CONFIG_SPI_FLASH_WINBOND=3Dy +CONFIG_PHY_REALTEK=3Dy +CONFIG_DM_ETH=3Dy +CONFIG_DM_MDIO=3Dy +CONFIG_PHY_GIGE=3Dy +CONFIG_ETH_DESIGNWARE=3Dy +CONFIG_RGMII=3Dy +CONFIG_MII=3Dy +CONFIG_GMAC_ROCKCHIP=3Dy +CONFIG_PCI=3Dy +CONFIG_PHY_ROCKCHIP_INNO_USB2=3Dy +CONFIG_PHY_ROCKCHIP_TYPEC=3Dy +CONFIG_DM_PMIC_FAN53555=3Dy +CONFIG_PMIC_RK8XX=3Dy +CONFIG_SPL_DM_REGULATOR=3Dy +CONFIG_REGULATOR_PWM=3Dy +CONFIG_SPL_DM_REGULATOR_FIXED=3Dy +CONFIG_DM_REGULATOR_GPIO=3Dy +CONFIG_SPL_DM_REGULATOR_GPIO=3Dy +CONFIG_REGULATOR_RK8XX=3Dy +CONFIG_PWM_ROCKCHIP=3Dy +CONFIG_RAM_RK3399_LPDDR4=3Dy +CONFIG_DM_RESET=3Dy +CONFIG_SCSI=3Dy +CONFIG_DM_SCSI=3Dy +CONFIG_DM_RNG=3Dy +CONFIG_RNG_ROCKCHIP=3Dy +CONFIG_BAUDRATE=3D1500000 +CONFIG_DEBUG_UART_SHIFT=3D2 +CONFIG_ROCKCHIP_SPI=3Dy +CONFIG_SYSRESET=3Dy +CONFIG_DM_THERMAL=3Dy +CONFIG_USB=3Dy +CONFIG_USB_XHCI_HCD=3Dy +CONFIG_USB_XHCI_DWC3=3Dy +CONFIG_USB_EHCI_HCD=3Dy +CONFIG_USB_EHCI_GENERIC=3Dy +CONFIG_USB_OHCI_HCD=3Dy +CONFIG_USB_OHCI_GENERIC=3Dy +CONFIG_USB_DWC3=3Dy +CONFIG_USB_DWC3_GENERIC=3Dy +CONFIG_USB_KEYBOARD=3Dy +CONFIG_USB_GADGET=3Dy +CONFIG_USB_FUNCTION_ROCKUSB=3Dy +CONFIG_USB_HOST_ETHER=3Dy +CONFIG_USB_ETHER_RTL8152=3Dy +CONFIG_SPL_TINY_MEMSET=3Dy +CONFIG_ERRNO_STR=3Dy diff --git a/include/configs/helios64-rk3399.h b/include/configs/helios64-r= k3399.h new file mode 100644 index 0000000000..fc1abf5c67 --- /dev/null +++ b/include/configs/helios64-rk3399.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Aditya Prayoga + * (C) Copyright 2021 Dennis Gilmore + */ + +#ifndef __HELIOS64_RK3399_H +#define __HELIOS64_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ +=09=09"stdin=3Dserial,usbkbd\0" \ +=09=09"stdout=3Dserial,vidconsole\0" \ +=09=09"stderr=3Dserial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#if defined(CONFIG_ENV_IS_IN_MMC) +=09#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +=09#define CONFIG_ENV_SPI_BUS=09=09CONFIG_SF_DEFAULT_BUS +=09#define CONFIG_ENV_SPI_CS=09=09CONFIG_SF_DEFAULT_CS +=09#define CONFIG_ENV_SPI_MODE=09=09CONFIG_SF_DEFAULT_MODE +=09#define CONFIG_ENV_SPI_MAX_HZ=09CONFIG_SF_DEFAULT_SPEED +#endif + + +#ifndef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(SCSI) + +=09#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 +=09#define CONFIG_SYS_SCSI_MAX_LUN 1 +=09#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * = \ +=09=09=09=09=09=09CONFIG_SYS_SCSI_MAX_LUN) + +=09#define BOOT_TARGET_SCSI(func) \ +=09 func(SCSI, scsi, 0) +#else +=09#define BOOT_TARGET_SCSI(func) +#endif + +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ +=09BOOT_TARGET_MMC(func) \ +=09BOOT_TARGET_USB(func) \ +=09BOOT_TARGET_SCSI(func) \ +=09BOOT_TARGET_PXE(func) \ +=09BOOT_TARGET_DHCP(func) + +#endif + +#endif --=20 2.31.1