* [PATCH v2 00/14] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, PSEUDO_OVL and MERGE.
Add DRM and these modules support by the patches below:
Change in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
[6] [v5,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210628113730.26107-3-Christine.Zhu@mediatek.com/
Nancy.Lin (14):
dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
dt-bindings: reset: mt8195: Move reset controller constants into
common location
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add pseudo ovl support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +
.../display/mediatek/mediatek,disp.yaml | 38 ++
.../display/mediatek/mediatek,ethdr.yaml | 144 +++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 381 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 122 +++-
drivers/soc/mediatek/mtk-mmsys.c | 138 ++++
drivers/soc/mediatek/mtk-mmsys.h | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 ++++----
.../mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 20 +
25 files changed, 2996 insertions(+), 185 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (66%)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 00/14] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, PSEUDO_OVL and MERGE.
Add DRM and these modules support by the patches below:
Change in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
[6] [v5,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210628113730.26107-3-Christine.Zhu@mediatek.com/
Nancy.Lin (14):
dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
dt-bindings: reset: mt8195: Move reset controller constants into
common location
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add pseudo ovl support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +
.../display/mediatek/mediatek,disp.yaml | 38 ++
.../display/mediatek/mediatek,ethdr.yaml | 144 +++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 381 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 122 +++-
drivers/soc/mediatek/mtk-mmsys.c | 138 ++++
drivers/soc/mediatek/mtk-mmsys.h | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 ++++----
.../mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 20 +
25 files changed, 2996 insertions(+), 185 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (66%)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 00/14] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, PSEUDO_OVL and MERGE.
Add DRM and these modules support by the patches below:
Change in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
[6] [v5,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210628113730.26107-3-Christine.Zhu@mediatek.com/
Nancy.Lin (14):
dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
dt-bindings: reset: mt8195: Move reset controller constants into
common location
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add pseudo ovl support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +
.../display/mediatek/mediatek,disp.yaml | 38 ++
.../display/mediatek/mediatek,ethdr.yaml | 144 +++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 381 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 122 +++-
drivers/soc/mediatek/mtk-mmsys.c | 138 ++++
drivers/soc/mediatek/mtk-mmsys.h | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 ++++----
.../mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 20 +
25 files changed, 2996 insertions(+), 185 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (66%)
--
2.18.0
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 01/14] dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA and MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..b5a80c683ef6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,14 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+
reg:
description: Physical base address and length of the function block register space.
@@ -461,4 +469,26 @@ examples:
/* See mediatek,dsc.yaml for details */
};
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 01/14] dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA and MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..b5a80c683ef6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,14 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+
reg:
description: Physical base address and length of the function block register space.
@@ -461,4 +469,26 @@ examples:
/* See mediatek,dsc.yaml for details */
};
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 01/14] dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add vdosys1 RDMA and MERGE definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..b5a80c683ef6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,14 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+
reg:
description: Physical base address and length of the function block register space.
@@ -461,4 +469,26 @@ examples:
/* See mediatek,dsc.yaml for details */
};
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
...
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 02/14] dt-bindings: mediatek: add ethdr definition for mt8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 8 +
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
2 files changed, 152 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index b5a80c683ef6..0dc432561c18 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -238,6 +238,11 @@ properties:
- items:
- const: mediatek,mt8195-vdo1-merge
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
@@ -491,4 +496,7 @@ examples:
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
};
+ disp_ethdr@1c114000 {
+ /* See mediatek,ethdr.yaml for details */
+ };
...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 02/14] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 8 +
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
2 files changed, 152 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index b5a80c683ef6..0dc432561c18 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -238,6 +238,11 @@ properties:
- items:
- const: mediatek,mt8195-vdo1-merge
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
@@ -491,4 +496,7 @@ examples:
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
};
+ disp_ethdr@1c114000 {
+ /* See mediatek,ethdr.yaml for details */
+ };
...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 02/14] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 8 +
.../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++
2 files changed, 152 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index b5a80c683ef6..0dc432561c18 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -238,6 +238,11 @@ properties:
- items:
- const: mediatek,mt8195-vdo1-merge
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
@@ -491,4 +496,7 @@ examples:
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
};
+ disp_ethdr@1c114000 {
+ /* See mediatek,ethdr.yaml for details */
+ };
...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..64d5349cdf8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 03/14] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index e6cd6e2173d4..480194c20adf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -87,6 +87,9 @@ properties:
The available clocks are defined in dt-bindings/clock/mt*-clk.h
const: 1
+ "#reset-cells":
+ const: 1
+
mboxes:
description: |
Client use mailbox to communicate with GCE, it should have this
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 03/14] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index e6cd6e2173d4..480194c20adf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -87,6 +87,9 @@ properties:
The available clocks are defined in dt-bindings/clock/mt*-clk.h
const: 1
+ "#reset-cells":
+ const: 1
+
mboxes:
description: |
Client use mailbox to communicate with GCE, it should have this
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 03/14] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index e6cd6e2173d4..480194c20adf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -87,6 +87,9 @@ properties:
The available clocks are defined in dt-bindings/clock/mt*-clk.h
const: 1
+ "#reset-cells":
+ const: 1
+
mboxes:
description: |
Client use mailbox to communicate with GCE, it should have this
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The DT binding includes for reset controllers are located in
include/dt-bindings/reset/. Move the Mediatek reset constants in there.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
similarity index 100%
rename from include/dt-bindings/reset-controller/mt8195-resets.h
rename to include/dt-bindings/reset/mt8195-resets.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The DT binding includes for reset controllers are located in
include/dt-bindings/reset/. Move the Mediatek reset constants in there.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
similarity index 100%
rename from include/dt-bindings/reset-controller/mt8195-resets.h
rename to include/dt-bindings/reset/mt8195-resets.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
The DT binding includes for reset controllers are located in
include/dt-bindings/reset/. Move the Mediatek reset constants in there.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
similarity index 100%
rename from include/dt-bindings/reset-controller/mt8195-resets.h
rename to include/dt-bindings/reset/mt8195-resets.h
--
2.18.0
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PATCH v2 05/14] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 7ec27a64afc7..e024b2b6a3a7 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 05/14] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 7ec27a64afc7..e024b2b6a3a7 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 05/14] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 7ec27a64afc7..e024b2b6a3a7 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 06/14] arm64: dts: mt8195: add display node for vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 06/14] arm64: dts: mt8195: add display node for vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 06/14] arm64: dts: mt8195: add display node for vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,7 +1291,208 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 90 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..104ba575f765 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..338c71570aeb 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 90 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..104ba575f765 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..338c71570aeb 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 90 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..104ba575f765 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..338c71570aeb 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
4 files changed, 116 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 104ba575f765..4bdb2087250c 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,18 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..d0f4a407f8f8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
};
@@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..084b1f5f3c88 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 338c71570aeb..ba3925661cc9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
4 files changed, 116 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 104ba575f765..4bdb2087250c 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,18 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..d0f4a407f8f8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
};
@@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..084b1f5f3c88 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 338c71570aeb..ba3925661cc9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add mmsys config API.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
4 files changed, 116 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 104ba575f765..4bdb2087250c 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,18 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..d0f4a407f8f8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
struct mtk_mmsys {
void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
};
@@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..084b1f5f3c88 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 338c71570aeb..ba3925661cc9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 79 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 4bdb2087250c..a7f6e275bfe5 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,7 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index d0f4a407f8f8..1ae04efeadab 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -15,6 +17,8 @@
#include "mt8183-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = 1 << (id % MMSYS_SW_RESET_PER_REG);
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (ret)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 084b1f5f3c88..cc57c3895c51 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 79 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 4bdb2087250c..a7f6e275bfe5 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,7 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index d0f4a407f8f8..1ae04efeadab 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -15,6 +17,8 @@
#include "mt8183-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = 1 << (id % MMSYS_SW_RESET_PER_REG);
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (ret)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 084b1f5f3c88..cc57c3895c51 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 79 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 4bdb2087250c..a7f6e275bfe5 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -154,6 +154,7 @@
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index d0f4a407f8f8..1ae04efeadab 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,10 +4,12 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include "mtk-mmsys.h"
@@ -15,6 +17,8 @@
#include "mt8183-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
};
struct mtk_mmsys {
void __iomem *regs;
struct cmdq_client_reg cmdq_base;
const struct mtk_mmsys_driver_data *data;
+ spinlock_t lock; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
+ unsigned long flags;
+ u32 reg;
+ int i;
+ u32 offset;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = 1 << (id % MMSYS_SW_RESET_PER_REG);
+
+ spin_lock_irqsave(&mmsys->lock, flags);
+
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ if (assert)
+ reg &= ~BIT(id);
+ else
+ reg |= BIT(id);
+
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
+
+ spin_unlock_irqrestore(&mmsys->lock, flags);
+
+ return 0;
+}
+
+static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, true);
+}
+
+static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return mtk_mmsys_reset_update(rcdev, id, false);
+}
+
+static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ int ret;
+
+ ret = mtk_mmsys_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ usleep_range(1000, 1100);
+
+ return mtk_mmsys_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_mmsys_reset_ops = {
+ .assert = mtk_mmsys_reset_assert,
+ .deassert = mtk_mmsys_reset_deassert,
+ .reset = mtk_mmsys_reset,
+};
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (ret)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
+
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = 64;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 084b1f5f3c88..cc57c3895c51 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
};
/*
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 10/14] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1ae04efeadab..232cc9c19c43 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -78,6 +78,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 10/14] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1ae04efeadab..232cc9c19c43 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -78,6 +78,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 10/14] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1ae04efeadab..232cc9c19c43 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -78,6 +78,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 11/14] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..df289821f8e9 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
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^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 11/14] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..df289821f8e9 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
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^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 11/14] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..df289821f8e9 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
6 files changed, 1344 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..31613564f499 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..0446fa99dd0a
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ const struct pseudo_ovl_data *data;
+ struct device *mmsys_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ priv->data = of_id->data;
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
new file mode 100644
index 000000000000..b3fe1e1702b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_PSEUDO_OVL_H__
+#define __MTK_DISP_PSEUDO_OVL_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
6 files changed, 1344 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..31613564f499 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..0446fa99dd0a
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ const struct pseudo_ovl_data *data;
+ struct device *mmsys_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ priv->data = of_id->data;
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
new file mode 100644
index 000000000000..b3fe1e1702b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_PSEUDO_OVL_H__
+#define __MTK_DISP_PSEUDO_OVL_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
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^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
6 files changed, 1344 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..31613564f499 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..0446fa99dd0a
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ const struct pseudo_ovl_data *data;
+ struct device *mmsys_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ break;
+ case 18:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
+ break;
+ default:
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
+ break;
+ }
+
+ mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12);
+ mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, MERGE_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ device_reset_optional(merge->dev);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ priv->data = of_id->data;
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
new file mode 100644
index 000000000000..b3fe1e1702b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_PSEUDO_OVL_H__
+#define __MTK_DISP_PSEUDO_OVL_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+
+#endif
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
5 files changed, 435 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 31613564f499..b4b305d58b0f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_disp_pseudo_ovl.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..464db52131db 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..58f9f9f06e94 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ }
};
@@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..26e079323de0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *pseudo_ovl_dev;
+ struct device *mmsys_dev;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ return;
+ }
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ int i;
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ (w / 2), cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+
+ for (i = 1; i <= 4; i++) {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ }
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_pseudo_ovl_clk_enable(priv->pseudo_ovl_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ mtk_pseudo_ovl_clk_disable(priv->pseudo_ovl_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *pseudo_ovl;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up pseudo ovl rdma and merge */
+ pseudo_ovl = platform_device_register_data(dev, "mediatek-disp-pseudo-ovl",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(pseudo_ovl))
+ return PTR_ERR(pseudo_ovl);
+
+ priv->pseudo_ovl_dev = &pseudo_ovl->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
5 files changed, 435 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 31613564f499..b4b305d58b0f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_disp_pseudo_ovl.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..464db52131db 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..58f9f9f06e94 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ }
};
@@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..26e079323de0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *pseudo_ovl_dev;
+ struct device *mmsys_dev;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ return;
+ }
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ int i;
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ (w / 2), cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+
+ for (i = 1; i <= 4; i++) {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ }
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_pseudo_ovl_clk_enable(priv->pseudo_ovl_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ mtk_pseudo_ovl_clk_disable(priv->pseudo_ovl_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *pseudo_ovl;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up pseudo ovl rdma and merge */
+ pseudo_ovl = platform_device_register_data(dev, "mediatek-disp-pseudo-ovl",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(pseudo_ovl))
+ return PTR_ERR(pseudo_ovl);
+
+ priv->pseudo_ovl_dev = &pseudo_ovl->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
5 files changed, 435 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 31613564f499..b4b305d58b0f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_disp_pseudo_ovl.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..464db52131db 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+unsigned int mtk_ethdr_layer_nr(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..58f9f9f06e94 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ }
};
@@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..26e079323de0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_pseudo_ovl.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *pseudo_ovl_dev;
+ struct device *mmsys_dev;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ return;
+ }
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+
+ mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ int i;
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ (w / 2), cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+
+ for (i = 1; i <= 4; i++) {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ }
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
+
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
+ mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_pseudo_ovl_clk_enable(priv->pseudo_ovl_dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ mtk_pseudo_ovl_clk_disable(priv->pseudo_ovl_dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+unsigned int mtk_ethdr_layer_nr(struct device *dev)
+{
+ return 4;
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct platform_device *pseudo_ovl;
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+
+ priv->mmsys_dev = drm_private->mmsys_dev;
+
+ /* Bring up pseudo ovl rdma and merge */
+ pseudo_ovl = platform_device_register_data(dev, "mediatek-disp-pseudo-ovl",
+ PLATFORM_DEVID_AUTO, (void *)priv->mmsys_dev,
+ sizeof(*priv->mmsys_dev));
+ if (IS_ERR(pseudo_ovl))
+ return PTR_ERR(pseudo_ovl);
+
+ priv->pseudo_ovl_dev = &pseudo_ovl->dev;
+
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ pm_runtime_enable(dev);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-22 9:45 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 356 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..829570308761 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..3324fa1a9e8c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..25f293542f79 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f2a184b1eceb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 58f9f9f06e94..94527fb040be 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -35,6 +36,16 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ struct cmdq_client_reg cmdq_base_reserved;
+ void *data_reserved;
+ spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev_reserved;
+ void *drm_private;
+};
+
static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};
@@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..212e4f87c35c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 356 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..829570308761 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..3324fa1a9e8c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..25f293542f79 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f2a184b1eceb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 58f9f9f06e94..94527fb040be 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -35,6 +36,16 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ struct cmdq_client_reg cmdq_base_reserved;
+ void *data_reserved;
+ spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev_reserved;
+ void *drm_private;
+};
+
static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};
@@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..212e4f87c35c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-07-22 9:45 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-22 9:45 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
7 files changed, 356 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..829570308761 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..3324fa1a9e8c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..25f293542f79 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+ .layer_nr = mtk_ethdr_layer_nr,
+ .layer_config = mtk_ethdr_layer_config,
+ .enable_vblank = mtk_ethdr_enable_vblank,
+ .disable_vblank = mtk_ethdr_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f2a184b1eceb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 58f9f9f06e94..94527fb040be 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -11,6 +11,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
+#include <linux/reset-controller.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -35,6 +36,16 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ struct cmdq_client_reg cmdq_base_reserved;
+ void *data_reserved;
+ spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
+ struct reset_controller_dev rcdev_reserved;
+ void *drm_private;
+};
+
static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};
@@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..212e4f87c35c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
(?)
@ 2021-07-23 10:57 ` Enric Balletbo Serra
-1 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> Among other features the mmsys driver should implement a reset
> controller to be able to reset different bits from their space.
>
I'm working on a series that does the same, it should be nice if we
can coordinate [1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 79 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 4bdb2087250c..a7f6e275bfe5 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,7 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d0f4a407f8f8..1ae04efeadab 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,10 +4,12 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
>
> #include "mtk-mmsys.h"
> @@ -15,6 +17,8 @@
> #include "mt8183-mmsys.h"
> #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> .config = mmsys_mt8195_config_table,
> .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
That change is interesting and I think I should also take it into
consideration with my series.
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
Seems that mmsys_sw_rst_b reg has different names for different SoCs?
I mean I know that for MT8173 and MT8183 the register is called
mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
So maybe we should update this comment to be more generic.
> + struct reset_controller_dev rcdev;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
> + bool assert)
> +{
> + struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> + unsigned long flags;
> + u32 reg;
> + int i;
> + u32 offset;
> +
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> +
> + spin_lock_irqsave(&mmsys->lock, flags);
> +
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + if (assert)
> + reg &= ~BIT(id);
> + else
> + reg |= BIT(id);
> +
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + spin_unlock_irqrestore(&mmsys->lock, flags);
> +
> + return 0;
> +}
> +
> +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, true);
> +}
> +
> +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, false);
> +}
> +
> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + int ret;
> +
> + ret = mtk_mmsys_reset_assert(rcdev, id);
> + if (ret)
> + return ret;
> +
> + usleep_range(1000, 1100);
> +
One question that I received in my series, and I couldn't answer
because I don't have the datasheet, is if
is this known to be enough for all IP cores that can be reset by this
controller? Is this time specified in the datasheet?
> + return mtk_mmsys_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> + .assert = mtk_mmsys_reset_assert,
> + .deassert = mtk_mmsys_reset_deassert,
> + .reset = mtk_mmsys_reset,
> +};
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> if (ret)
> dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> #endif
> +
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = 64;
Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
MT8183. Can you confirm?
Thanks,
Enric
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> + return ret;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 084b1f5f3c88..cc57c3895c51 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> const struct mtk_mmsys_config *config;
> const unsigned int num_configs;
> + u32 sw_reset_start;
> };
>
> /*
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-23 10:57 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> Among other features the mmsys driver should implement a reset
> controller to be able to reset different bits from their space.
>
I'm working on a series that does the same, it should be nice if we
can coordinate [1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 79 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 4bdb2087250c..a7f6e275bfe5 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,7 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d0f4a407f8f8..1ae04efeadab 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,10 +4,12 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
>
> #include "mtk-mmsys.h"
> @@ -15,6 +17,8 @@
> #include "mt8183-mmsys.h"
> #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> .config = mmsys_mt8195_config_table,
> .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
That change is interesting and I think I should also take it into
consideration with my series.
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
Seems that mmsys_sw_rst_b reg has different names for different SoCs?
I mean I know that for MT8173 and MT8183 the register is called
mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
So maybe we should update this comment to be more generic.
> + struct reset_controller_dev rcdev;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
> + bool assert)
> +{
> + struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> + unsigned long flags;
> + u32 reg;
> + int i;
> + u32 offset;
> +
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> +
> + spin_lock_irqsave(&mmsys->lock, flags);
> +
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + if (assert)
> + reg &= ~BIT(id);
> + else
> + reg |= BIT(id);
> +
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + spin_unlock_irqrestore(&mmsys->lock, flags);
> +
> + return 0;
> +}
> +
> +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, true);
> +}
> +
> +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, false);
> +}
> +
> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + int ret;
> +
> + ret = mtk_mmsys_reset_assert(rcdev, id);
> + if (ret)
> + return ret;
> +
> + usleep_range(1000, 1100);
> +
One question that I received in my series, and I couldn't answer
because I don't have the datasheet, is if
is this known to be enough for all IP cores that can be reset by this
controller? Is this time specified in the datasheet?
> + return mtk_mmsys_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> + .assert = mtk_mmsys_reset_assert,
> + .deassert = mtk_mmsys_reset_deassert,
> + .reset = mtk_mmsys_reset,
> +};
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> if (ret)
> dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> #endif
> +
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = 64;
Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
MT8183. Can you confirm?
Thanks,
Enric
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> + return ret;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 084b1f5f3c88..cc57c3895c51 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> const struct mtk_mmsys_config *config;
> const unsigned int num_configs;
> + u32 sw_reset_start;
> };
>
> /*
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-23 10:57 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> Among other features the mmsys driver should implement a reset
> controller to be able to reset different bits from their space.
>
I'm working on a series that does the same, it should be nice if we
can coordinate [1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 79 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 4bdb2087250c..a7f6e275bfe5 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,7 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d0f4a407f8f8..1ae04efeadab 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,10 +4,12 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
>
> #include "mtk-mmsys.h"
> @@ -15,6 +17,8 @@
> #include "mt8183-mmsys.h"
> #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> .config = mmsys_mt8195_config_table,
> .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
That change is interesting and I think I should also take it into
consideration with my series.
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
Seems that mmsys_sw_rst_b reg has different names for different SoCs?
I mean I know that for MT8173 and MT8183 the register is called
mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
So maybe we should update this comment to be more generic.
> + struct reset_controller_dev rcdev;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
> + bool assert)
> +{
> + struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> + unsigned long flags;
> + u32 reg;
> + int i;
> + u32 offset;
> +
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> +
> + spin_lock_irqsave(&mmsys->lock, flags);
> +
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + if (assert)
> + reg &= ~BIT(id);
> + else
> + reg |= BIT(id);
> +
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + spin_unlock_irqrestore(&mmsys->lock, flags);
> +
> + return 0;
> +}
> +
> +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, true);
> +}
> +
> +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, false);
> +}
> +
> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + int ret;
> +
> + ret = mtk_mmsys_reset_assert(rcdev, id);
> + if (ret)
> + return ret;
> +
> + usleep_range(1000, 1100);
> +
One question that I received in my series, and I couldn't answer
because I don't have the datasheet, is if
is this known to be enough for all IP cores that can be reset by this
controller? Is this time specified in the datasheet?
> + return mtk_mmsys_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> + .assert = mtk_mmsys_reset_assert,
> + .deassert = mtk_mmsys_reset_deassert,
> + .reset = mtk_mmsys_reset,
> +};
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> if (ret)
> dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> #endif
> +
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = 64;
Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
MT8183. Can you confirm?
Thanks,
Enric
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> + return ret;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 084b1f5f3c88..cc57c3895c51 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> const struct mtk_mmsys_config *config;
> const unsigned int num_configs;
> + u32 sw_reset_start;
> };
>
> /*
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-23 10:57 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> Among other features the mmsys driver should implement a reset
> controller to be able to reset different bits from their space.
>
I'm working on a series that does the same, it should be nice if we
can coordinate [1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 77 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 79 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 4bdb2087250c..a7f6e275bfe5 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,7 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d0f4a407f8f8..1ae04efeadab 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,10 +4,12 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
>
> #include "mtk-mmsys.h"
> @@ -15,6 +17,8 @@
> #include "mt8183-mmsys.h"
> #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> .config = mmsys_mt8195_config_table,
> .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
That change is interesting and I think I should also take it into
consideration with my series.
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
Seems that mmsys_sw_rst_b reg has different names for different SoCs?
I mean I know that for MT8173 and MT8183 the register is called
mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
So maybe we should update this comment to be more generic.
> + struct reset_controller_dev rcdev;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
> + bool assert)
> +{
> + struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> + unsigned long flags;
> + u32 reg;
> + int i;
> + u32 offset;
> +
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> +
> + spin_lock_irqsave(&mmsys->lock, flags);
> +
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + if (assert)
> + reg &= ~BIT(id);
> + else
> + reg |= BIT(id);
> +
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> + spin_unlock_irqrestore(&mmsys->lock, flags);
> +
> + return 0;
> +}
> +
> +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, true);
> +}
> +
> +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + return mtk_mmsys_reset_update(rcdev, id, false);
> +}
> +
> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + int ret;
> +
> + ret = mtk_mmsys_reset_assert(rcdev, id);
> + if (ret)
> + return ret;
> +
> + usleep_range(1000, 1100);
> +
One question that I received in my series, and I couldn't answer
because I don't have the datasheet, is if
is this known to be enough for all IP cores that can be reset by this
controller? Is this time specified in the datasheet?
> + return mtk_mmsys_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> + .assert = mtk_mmsys_reset_assert,
> + .deassert = mtk_mmsys_reset_deassert,
> + .reset = mtk_mmsys_reset,
> +};
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> if (ret)
> dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> #endif
> +
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = 64;
Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
MT8183. Can you confirm?
Thanks,
Enric
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> + return ret;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 084b1f5f3c88..cc57c3895c51 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> const struct mtk_mmsys_config *config;
> const unsigned int num_configs;
> + u32 sw_reset_start;
> };
>
> /*
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-23 11:05 ` Enric Balletbo Serra
-1 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:05 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:45:
>
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 90 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 73e9e8286d50..104ba575f765 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -64,16 +64,16 @@
> #define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> -#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
This definition was introduced in this patch [1] that didn't land yet.
And you're removing it now. Could you sync with Jason and only
introduce the bits that are needed for your patches. Also all the
comments I made to the Jason's patch apply here.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/
> +#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> -#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> -#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
> +#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> -#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
>
> #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
> @@ -88,7 +88,7 @@
> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
>
> #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> #define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }, {
> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
> }
> };
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 1fb241750897..9e31aad6c5c8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
Why do you need a second compatible, isn't this the same IP block? I
mean, I understand that you have 2 mmsys blocks, but both are the same
IP block, right? or are they different?
Thanks,
Enric
> + .data = &mt8195_vdosys1_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 34cb605e5df9..338c71570aeb 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSC1_VIRTUAL0,
> DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> + DDP_COMPONENT_PSEUDO_OVL,
> DDP_COMPONENT_ID_MAX,
> };
>
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-23 11:05 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:05 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:45:
>
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 90 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 73e9e8286d50..104ba575f765 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -64,16 +64,16 @@
> #define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> -#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
This definition was introduced in this patch [1] that didn't land yet.
And you're removing it now. Could you sync with Jason and only
introduce the bits that are needed for your patches. Also all the
comments I made to the Jason's patch apply here.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/
> +#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> -#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> -#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
> +#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> -#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
>
> #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
> @@ -88,7 +88,7 @@
> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
>
> #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> #define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }, {
> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
> }
> };
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 1fb241750897..9e31aad6c5c8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
Why do you need a second compatible, isn't this the same IP block? I
mean, I understand that you have 2 mmsys blocks, but both are the same
IP block, right? or are they different?
Thanks,
Enric
> + .data = &mt8195_vdosys1_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 34cb605e5df9..338c71570aeb 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSC1_VIRTUAL0,
> DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> + DDP_COMPONENT_PSEUDO_OVL,
> DDP_COMPONENT_ID_MAX,
> };
>
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-23 11:05 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:05 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Nancy,
Thank you for your patch.
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:45:
>
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 90 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 73e9e8286d50..104ba575f765 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -64,16 +64,16 @@
> #define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> -#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
This definition was introduced in this patch [1] that didn't land yet.
And you're removing it now. Could you sync with Jason and only
introduce the bits that are needed for your patches. Also all the
comments I made to the Jason's patch apply here.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/
> +#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> -#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> -#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
> +#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> -#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
> +#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
>
> #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
> @@ -88,7 +88,7 @@
> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
>
> #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
>
> #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> #define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }, {
> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + },
> + {
> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + },
> + {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
> }
> };
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 1fb241750897..9e31aad6c5c8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
Why do you need a second compatible, isn't this the same IP block? I
mean, I understand that you have 2 mmsys blocks, but both are the same
IP block, right? or are they different?
Thanks,
Enric
> + .data = &mt8195_vdosys1_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 34cb605e5df9..338c71570aeb 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSC1_VIRTUAL0,
> DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> + DDP_COMPONENT_PSEUDO_OVL,
> DDP_COMPONENT_ID_MAX,
> };
>
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
2021-07-22 9:45 ` Nancy.Lin
(?)
(?)
@ 2021-07-23 11:10 ` Enric Balletbo Serra
-1 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:10 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> The DT binding includes for reset controllers are located in
> include/dt-bindings/reset/. Move the Mediatek reset constants in there.
>
I think that the patch that introduces mt8195-resets.h into the
reset-controller directory didn't land yet, please sync with the
author of that patch and just put it in the correct place the first
time.
Thanks,
Enric
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
>
> diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> similarity index 100%
> rename from include/dt-bindings/reset-controller/mt8195-resets.h
> rename to include/dt-bindings/reset/mt8195-resets.h
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-23 11:10 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:10 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> The DT binding includes for reset controllers are located in
> include/dt-bindings/reset/. Move the Mediatek reset constants in there.
>
I think that the patch that introduces mt8195-resets.h into the
reset-controller directory didn't land yet, please sync with the
author of that patch and just put it in the correct place the first
time.
Thanks,
Enric
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
>
> diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> similarity index 100%
> rename from include/dt-bindings/reset-controller/mt8195-resets.h
> rename to include/dt-bindings/reset/mt8195-resets.h
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-23 11:10 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:10 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Thank you for your patch
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> The DT binding includes for reset controllers are located in
> include/dt-bindings/reset/. Move the Mediatek reset constants in there.
>
I think that the patch that introduces mt8195-resets.h into the
reset-controller directory didn't land yet, please sync with the
author of that patch and just put it in the correct place the first
time.
Thanks,
Enric
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
>
> diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> similarity index 100%
> rename from include/dt-bindings/reset-controller/mt8195-resets.h
> rename to include/dt-bindings/reset/mt8195-resets.h
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-23 11:10 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:10 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Nancy,
Thank you for your patch
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> The DT binding includes for reset controllers are located in
> include/dt-bindings/reset/. Move the Mediatek reset constants in there.
>
I think that the patch that introduces mt8195-resets.h into the
reset-controller directory didn't land yet, please sync with the
author of that patch and just put it in the correct place the first
time.
Thanks,
Enric
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
>
> diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> similarity index 100%
> rename from include/dt-bindings/reset-controller/mt8195-resets.h
> rename to include/dt-bindings/reset/mt8195-resets.h
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-25 1:57 ` Chun-Kuang Hu
-1 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-25 1:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add pseudo ovl module files:
My English is not good. The word 'pseudo' seems like 'looks like but
indeed not the same'.
I think the 'real' ovl also has rdma and mixer inside it, so I prefer
to treat these two ovl as different kind of ovl, not a real one and a
pseudo one.
Does I misunderstanding the word 'pseudo'?
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
Seperate mtk_dmp_rdma driver to an independent patch.
> 6 files changed, 1344 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..31613564f499 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..0446fa99dd0a
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,593 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
Which hardware has this limitation? I would like this naming to
reflect which hardware has this limitation.
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
PSEUDO_OVL_RDMA_BASE.
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
Ditto.
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + const struct pseudo_ovl_data *data;
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
Now only support one SoC, so remove driver data and change these to
definition instead of variable.
> +
> +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + priv->data = of_id->data;
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> new file mode 100644
> index 000000000000..b3fe1e1702b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> +#define __MTK_DISP_PSEUDO_OVL_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
Why do you enable rdma interrupt?
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
Why do you pass fifo config from ovl to rdma?
I think just rdma know how to set these fifo parameter.
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
This is got from mtk_plane_atomic_update().
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
drm_format_info().
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
Move rdma internal definition in .c file.
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
Move these prototype to mtk_disp_drv.h
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
Only one file need these, so move register definiton in .c file.
Regards,
Chun-Kuang.
> +
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-25 1:57 ` Chun-Kuang Hu
0 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-25 1:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add pseudo ovl module files:
My English is not good. The word 'pseudo' seems like 'looks like but
indeed not the same'.
I think the 'real' ovl also has rdma and mixer inside it, so I prefer
to treat these two ovl as different kind of ovl, not a real one and a
pseudo one.
Does I misunderstanding the word 'pseudo'?
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
Seperate mtk_dmp_rdma driver to an independent patch.
> 6 files changed, 1344 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..31613564f499 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..0446fa99dd0a
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,593 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
Which hardware has this limitation? I would like this naming to
reflect which hardware has this limitation.
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
PSEUDO_OVL_RDMA_BASE.
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
Ditto.
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + const struct pseudo_ovl_data *data;
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
Now only support one SoC, so remove driver data and change these to
definition instead of variable.
> +
> +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + priv->data = of_id->data;
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> new file mode 100644
> index 000000000000..b3fe1e1702b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> +#define __MTK_DISP_PSEUDO_OVL_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
Why do you enable rdma interrupt?
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
Why do you pass fifo config from ovl to rdma?
I think just rdma know how to set these fifo parameter.
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
This is got from mtk_plane_atomic_update().
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
drm_format_info().
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
Move rdma internal definition in .c file.
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
Move these prototype to mtk_disp_drv.h
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
Only one file need these, so move register definiton in .c file.
Regards,
Chun-Kuang.
> +
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-25 1:57 ` Chun-Kuang Hu
0 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-25 1:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add pseudo ovl module files:
My English is not good. The word 'pseudo' seems like 'looks like but
indeed not the same'.
I think the 'real' ovl also has rdma and mixer inside it, so I prefer
to treat these two ovl as different kind of ovl, not a real one and a
pseudo one.
Does I misunderstanding the word 'pseudo'?
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593 ++++++++++++++++++
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
Seperate mtk_dmp_rdma driver to an independent patch.
> 6 files changed, 1344 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..31613564f499 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..0446fa99dd0a
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,593 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
Which hardware has this limitation? I would like this naming to
reflect which hardware has this limitation.
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
PSEUDO_OVL_RDMA_BASE.
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
Ditto.
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + const struct pseudo_ovl_data *data;
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + break;
> + case 18:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27);
> + break;
> + default:
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4);
> + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5);
> + break;
> + }
> +
> + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12);
> + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> +
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, MERGE_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + device_reset_optional(merge->dev);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
Now only support one SoC, so remove driver data and change these to
definition instead of variable.
> +
> +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + priv->data = of_id->data;
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> new file mode 100644
> index 000000000000..b3fe1e1702b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> +#define __MTK_DISP_PSEUDO_OVL_H__
> +
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
Why do you enable rdma interrupt?
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
Why do you pass fifo config from ovl to rdma?
I think just rdma know how to set these fifo parameter.
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
This is got from mtk_plane_atomic_update().
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
drm_format_info().
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
Move rdma internal definition in .c file.
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
Move these prototype to mtk_disp_drv.h
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
Only one file need these, so move register definiton in .c file.
Regards,
Chun-Kuang.
> +
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-07-27 23:39 ` Chun-Kuang Hu
-1 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-27 23:39 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
> 5 files changed, 435 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 31613564f499..b4b305d58b0f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_dsi.o \
> mtk_dpi.o \
> mtk_disp_pseudo_ovl.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..464db52131db 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ethdr_disable_vblank(struct device *dev);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..58f9f9f06e94 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { }
> };
>
> @@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..26e079323de0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *pseudo_ovl_dev;
> + struct device *mmsys_dev;
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
I think register callback function need to be protected like [1].
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3021203
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
Ditto.
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + if (!priv->vblank_cb)
> + return IRQ_NONE;
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + return;
> + }
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> +
> + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + int i;
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
> + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
> + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
> + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
> + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
> + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> +
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(0));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(1));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(2));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(3));
> + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
> + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
> + &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
> + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, MIX_SRC_L0_EN);
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> + (w / 2), cmdq_pkt);
Remove parentheses of (w / 2).
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> + h, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> +
> + for (i = 1; i <= 4; i++) {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
Could these be moved to mtk_ethdr_layer_config()? That means you
config the i only for the layer is on.
> + }
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
whitel();
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
ditto.
Regards,
Chun-Kuang.
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
> + reset_control_reset(devm_reset_control_array_get(dev, true, true));
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
> +}
> +
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-27 23:39 ` Chun-Kuang Hu
0 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-27 23:39 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
> 5 files changed, 435 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 31613564f499..b4b305d58b0f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_dsi.o \
> mtk_dpi.o \
> mtk_disp_pseudo_ovl.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..464db52131db 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ethdr_disable_vblank(struct device *dev);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..58f9f9f06e94 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { }
> };
>
> @@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..26e079323de0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *pseudo_ovl_dev;
> + struct device *mmsys_dev;
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
I think register callback function need to be protected like [1].
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3021203
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
Ditto.
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + if (!priv->vblank_cb)
> + return IRQ_NONE;
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + return;
> + }
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> +
> + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + int i;
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
> + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
> + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
> + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
> + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
> + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> +
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(0));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(1));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(2));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(3));
> + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
> + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
> + &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
> + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, MIX_SRC_L0_EN);
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> + (w / 2), cmdq_pkt);
Remove parentheses of (w / 2).
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> + h, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> +
> + for (i = 1; i <= 4; i++) {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
Could these be moved to mtk_ethdr_layer_config()? That means you
config the i only for the layer is on.
> + }
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
whitel();
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
ditto.
Regards,
Chun-Kuang.
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
> + reset_control_reset(devm_reset_control_array_get(dev, true, true));
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
> +}
> +
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-27 23:39 ` Chun-Kuang Hu
0 siblings, 0 replies; 99+ messages in thread
From: Chun-Kuang Hu @ 2021-07-27 23:39 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 413 ++++++++++++++++++++++++
> 5 files changed, 435 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 31613564f499..b4b305d58b0f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_dsi.o \
> mtk_dpi.o \
> mtk_disp_pseudo_ovl.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..464db52131db 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ethdr_disable_vblank(struct device *dev);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..58f9f9f06e94 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { }
> };
>
> @@ -676,6 +678,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..26e079323de0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_pseudo_ovl.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *pseudo_ovl_dev;
> + struct device *mmsys_dev;
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
I think register callback function need to be protected like [1].
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3021203
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
Ditto.
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + if (!priv->vblank_cb)
> + return IRQ_NONE;
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx, state, cmdq_pkt);
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + return;
> + }
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> +
> + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + int i;
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> +
> + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh, bpc, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
> + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
> + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
> + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
> + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> +
> + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
> + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> +
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(0));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(1));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(2));
> + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
> + MIX_L_SRC_CON(3));
> + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
> + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
> + &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
> + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, MIX_SRC_L0_EN);
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> + (w / 2), cmdq_pkt);
Remove parentheses of (w / 2).
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> + h, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> +
> + for (i = 1; i <= 4; i++) {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
Could these be moved to mtk_ethdr_layer_config()? That means you
config the i only for the layer is on.
> + }
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_EN);
whitel();
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> +
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN);
ditto.
Regards,
Chun-Kuang.
> + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST);
> + reset_control_reset(devm_reset_control_array_get(dev, true, true));
> + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST);
> +}
> +
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
2021-07-23 11:10 ` Enric Balletbo Serra
(?)
@ 2021-07-28 5:21 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:21 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:10 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > The DT binding includes for reset controllers are located in
> > include/dt-bindings/reset/. Move the Mediatek reset constants in
> > there.
> >
>
> I think that the patch that introduces mt8195-resets.h into the
> reset-controller directory didn't land yet, please sync with the
> author of that patch and just put it in the correct place the first
> time.
>
> Thanks,
> Enric
>
OK, I with sync with the author.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > include/dt-bindings/{reset-controller => reset}/mt8195-resets.h |
> > 0
> > 1 file changed, 0 insertions(+), 0 deletions(-)
> > rename include/dt-bindings/{reset-controller => reset}/mt8195-
> > resets.h (100%)
> >
> > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h
> > b/include/dt-bindings/reset/mt8195-resets.h
> > similarity index 100%
> > rename from include/dt-bindings/reset-controller/mt8195-resets.h
> > rename to include/dt-bindings/reset/mt8195-resets.h
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-28 5:21 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:21 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:10 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > The DT binding includes for reset controllers are located in
> > include/dt-bindings/reset/. Move the Mediatek reset constants in
> > there.
> >
>
> I think that the patch that introduces mt8195-resets.h into the
> reset-controller directory didn't land yet, please sync with the
> author of that patch and just put it in the correct place the first
> time.
>
> Thanks,
> Enric
>
OK, I with sync with the author.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > include/dt-bindings/{reset-controller => reset}/mt8195-resets.h |
> > 0
> > 1 file changed, 0 insertions(+), 0 deletions(-)
> > rename include/dt-bindings/{reset-controller => reset}/mt8195-
> > resets.h (100%)
> >
> > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h
> > b/include/dt-bindings/reset/mt8195-resets.h
> > similarity index 100%
> > rename from include/dt-bindings/reset-controller/mt8195-resets.h
> > rename to include/dt-bindings/reset/mt8195-resets.h
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
@ 2021-07-28 5:21 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:21 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:10 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > The DT binding includes for reset controllers are located in
> > include/dt-bindings/reset/. Move the Mediatek reset constants in
> > there.
> >
>
> I think that the patch that introduces mt8195-resets.h into the
> reset-controller directory didn't land yet, please sync with the
> author of that patch and just put it in the correct place the first
> time.
>
> Thanks,
> Enric
>
OK, I with sync with the author.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > include/dt-bindings/{reset-controller => reset}/mt8195-resets.h |
> > 0
> > 1 file changed, 0 insertions(+), 0 deletions(-)
> > rename include/dt-bindings/{reset-controller => reset}/mt8195-
> > resets.h (100%)
> >
> > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h
> > b/include/dt-bindings/reset/mt8195-resets.h
> > similarity index 100%
> > rename from include/dt-bindings/reset-controller/mt8195-resets.h
> > rename to include/dt-bindings/reset/mt8195-resets.h
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-07-23 11:05 ` Enric Balletbo Serra
(?)
@ 2021-07-28 5:34 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:34 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:45:
> >
> > Add mt8195 vdosys1 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > ++++++++++++++++++++++++--
> > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > 3 files changed, 90 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 73e9e8286d50..104ba575f765 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -64,16 +64,16 @@
> > #define SOUT_TO_VPP_MERGE0_P1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > -#define SOUT_TO_HDR_VDO_FE0 (0
> > << 0)
>
> This definition was introduced in this patch [1] that didn't land
> yet.
> And you're removing it now. Could you sync with Jason and only
> introduce the bits that are needed for your patches. Also all the
> comments I made to the Jason's patch apply here.
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>
>
OK, I will sync with Jason and modify it.
> > +#define SOUT_TO_MIXER_IN1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > -#define SOUT_TO_HDR_VDO_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN2_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > -#define SOUT_TO_HDR_GFX_FE0 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN3_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > -#define SOUT_TO_HDR_GFX_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN4_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > << 0)
> > @@ -88,7 +88,7 @@
> > #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > << 0)
> > +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > #define MERGE4_SOUT_TO_VDOSYS0 (0
> > << 0)
> > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }, {
> > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > MT8195_VDO0_SEL_OUT,
> > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN2_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN3_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN4_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DPI1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DP_INTF0_SEL
> > }
> > };
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 1fb241750897..9e31aad6c5c8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .clk_driver = "clk-mt8195-vdo1",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -168,6 +174,10 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8195-vdosys0",
> > .data = &mt8195_vdosys0_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-vdosys1",
>
> Why do you need a second compatible, isn't this the same IP block? I
> mean, I understand that you have 2 mmsys blocks, but both are the
> same
> IP block, right? or are they different?
>
> Thanks,
> Enric
>
They(vdosys0 and vdosys1) are different IP block.
> > + .data = &mt8195_vdosys1_driver_data,
> > + },
> > { }
> > };
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 34cb605e5df9..338c71570aeb 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSC1_VIRTUAL0,
> > DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > + DDP_COMPONENT_PSEUDO_OVL,
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-28 5:34 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:34 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:45:
> >
> > Add mt8195 vdosys1 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > ++++++++++++++++++++++++--
> > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > 3 files changed, 90 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 73e9e8286d50..104ba575f765 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -64,16 +64,16 @@
> > #define SOUT_TO_VPP_MERGE0_P1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > -#define SOUT_TO_HDR_VDO_FE0 (0
> > << 0)
>
> This definition was introduced in this patch [1] that didn't land
> yet.
> And you're removing it now. Could you sync with Jason and only
> introduce the bits that are needed for your patches. Also all the
> comments I made to the Jason's patch apply here.
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>
>
OK, I will sync with Jason and modify it.
> > +#define SOUT_TO_MIXER_IN1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > -#define SOUT_TO_HDR_VDO_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN2_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > -#define SOUT_TO_HDR_GFX_FE0 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN3_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > -#define SOUT_TO_HDR_GFX_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN4_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > << 0)
> > @@ -88,7 +88,7 @@
> > #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > << 0)
> > +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > #define MERGE4_SOUT_TO_VDOSYS0 (0
> > << 0)
> > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }, {
> > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > MT8195_VDO0_SEL_OUT,
> > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN2_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN3_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN4_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DPI1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DP_INTF0_SEL
> > }
> > };
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 1fb241750897..9e31aad6c5c8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .clk_driver = "clk-mt8195-vdo1",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -168,6 +174,10 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8195-vdosys0",
> > .data = &mt8195_vdosys0_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-vdosys1",
>
> Why do you need a second compatible, isn't this the same IP block? I
> mean, I understand that you have 2 mmsys blocks, but both are the
> same
> IP block, right? or are they different?
>
> Thanks,
> Enric
>
They(vdosys0 and vdosys1) are different IP block.
> > + .data = &mt8195_vdosys1_driver_data,
> > + },
> > { }
> > };
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 34cb605e5df9..338c71570aeb 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSC1_VIRTUAL0,
> > DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > + DDP_COMPONENT_PSEUDO_OVL,
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-28 5:34 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 5:34 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:45:
> >
> > Add mt8195 vdosys1 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > ++++++++++++++++++++++++--
> > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > 3 files changed, 90 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 73e9e8286d50..104ba575f765 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -64,16 +64,16 @@
> > #define SOUT_TO_VPP_MERGE0_P1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > -#define SOUT_TO_HDR_VDO_FE0 (0
> > << 0)
>
> This definition was introduced in this patch [1] that didn't land
> yet.
> And you're removing it now. Could you sync with Jason and only
> introduce the bits that are needed for your patches. Also all the
> comments I made to the Jason's patch apply here.
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>
>
OK, I will sync with Jason and modify it.
> > +#define SOUT_TO_MIXER_IN1_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > -#define SOUT_TO_HDR_VDO_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN2_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > -#define SOUT_TO_HDR_GFX_FE0 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN3_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > -#define SOUT_TO_HDR_GFX_FE1 (0
> > << 0)
> > +#define SOUT_TO_MIXER_IN4_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > << 0)
> > @@ -88,7 +88,7 @@
> > #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > << 0)
> >
> > #define
> > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > << 0)
> > +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > << 0)
> >
> > #define
> > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > #define MERGE4_SOUT_TO_VDOSYS0 (0
> > << 0)
> > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }, {
> > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > MT8195_VDO0_SEL_OUT,
> > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN2_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN3_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > SOUT_TO_MIXER_IN4_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > + },
> > + {
> > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DPI1_SEL
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + },
> > + {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > MERGE4_SOUT_TO_DP_INTF0_SEL
> > }
> > };
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 1fb241750897..9e31aad6c5c8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .clk_driver = "clk-mt8195-vdo1",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -168,6 +174,10 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8195-vdosys0",
> > .data = &mt8195_vdosys0_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-vdosys1",
>
> Why do you need a second compatible, isn't this the same IP block? I
> mean, I understand that you have 2 mmsys blocks, but both are the
> same
> IP block, right? or are they different?
>
> Thanks,
> Enric
>
They(vdosys0 and vdosys1) are different IP block.
> > + .data = &mt8195_vdosys1_driver_data,
> > + },
> > { }
> > };
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 34cb605e5df9..338c71570aeb 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSC1_VIRTUAL0,
> > DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > + DDP_COMPONENT_PSEUDO_OVL,
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-07-23 10:57 ` Enric Balletbo Serra
(?)
@ 2021-07-28 6:00 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 6:00 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > Among other features the mmsys driver should implement a reset
> > controller to be able to reset different bits from their space.
> >
>
> I'm working on a series that does the same, it should be nice if we
> can coordinate [1]
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
>
>
OK, I will add this series to my reference base in the next patch
revision.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 77
> > +++++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > 3 files changed, 79 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 4bdb2087250c..a7f6e275bfe5 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,7 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > << 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > << 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index d0f4a407f8f8..1ae04efeadab 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,10 +4,12 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > #include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> >
> > #include "mtk-mmsys.h"
> > @@ -15,6 +17,8 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8195-mmsys.h"
> >
> > +#define MMSYS_SW_RESET_PER_REG 32
> > +
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> > .clk_driver = "clk-mt2701-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > .config = mmsys_mt8195_config_table,
> > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
>
> That change is interesting and I think I should also take it into
> consideration with my series.
>
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
>
> Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> I mean I know that for MT8173 and MT8183 the register is called
> mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> So maybe we should update this comment to be more generic.
>
Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
a different name. Maybe we can change the comment to "protects mmsys sw
reset reg".
> >
> > + struct reset_controller_dev rcdev;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > enum mtk_mmsys_config_type config,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> >
> > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > + bool assert)
> > +{
> > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > mtk_mmsys, rcdev);
> > + unsigned long flags;
> > + u32 reg;
> > + int i;
> > + u32 offset;
> > +
> > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > +
> > + spin_lock_irqsave(&mmsys->lock, flags);
> > +
> > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + if (assert)
> > + reg &= ~BIT(id);
> > + else
> > + reg |= BIT(id);
> > +
> > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, true);
> > +}
> > +
> > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, false);
> > +}
> > +
> > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > unsigned long id)
> > +{
> > + int ret;
> > +
> > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(1000, 1100);
> > +
>
> One question that I received in my series, and I couldn't answer
> because I don't have the datasheet, is if
> is this known to be enough for all IP cores that can be reset by this
> controller? Is this time specified in the datasheet?
It only takes few cycles for the reset. The 1000us is enough for the
reset to take effect.
> > + return mtk_mmsys_reset_deassert(rcdev, id);
> > +}
> > +
> > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > + .assert = mtk_mmsys_reset_assert,
> > + .deassert = mtk_mmsys_reset_deassert,
> > + .reset = mtk_mmsys_reset,
> > +};
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > if (ret)
> > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > #endif
> > +
> > + spin_lock_init(&mmsys->lock);
> > +
> > + mmsys->rcdev.owner = THIS_MODULE;
> > + mmsys->rcdev.nr_resets = 64;
>
> Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> MT8183. Can you confirm?
>
> Thanks,
> Enric
>
The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
are not used).
> > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > >rcdev);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > controller: %d\n", ret);
> > + return ret;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys-
> > >data->clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 084b1f5f3c88..cc57c3895c51 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > const unsigned int num_routes;
> > const struct mtk_mmsys_config *config;
> > const unsigned int num_configs;
> > + u32 sw_reset_start;
> > };
> >
> > /*
> > --
> > 2.18.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-28 6:00 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 6:00 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > Among other features the mmsys driver should implement a reset
> > controller to be able to reset different bits from their space.
> >
>
> I'm working on a series that does the same, it should be nice if we
> can coordinate [1]
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
>
>
OK, I will add this series to my reference base in the next patch
revision.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 77
> > +++++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > 3 files changed, 79 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 4bdb2087250c..a7f6e275bfe5 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,7 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > << 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > << 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index d0f4a407f8f8..1ae04efeadab 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,10 +4,12 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > #include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> >
> > #include "mtk-mmsys.h"
> > @@ -15,6 +17,8 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8195-mmsys.h"
> >
> > +#define MMSYS_SW_RESET_PER_REG 32
> > +
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> > .clk_driver = "clk-mt2701-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > .config = mmsys_mt8195_config_table,
> > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
>
> That change is interesting and I think I should also take it into
> consideration with my series.
>
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
>
> Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> I mean I know that for MT8173 and MT8183 the register is called
> mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> So maybe we should update this comment to be more generic.
>
Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
a different name. Maybe we can change the comment to "protects mmsys sw
reset reg".
> >
> > + struct reset_controller_dev rcdev;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > enum mtk_mmsys_config_type config,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> >
> > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > + bool assert)
> > +{
> > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > mtk_mmsys, rcdev);
> > + unsigned long flags;
> > + u32 reg;
> > + int i;
> > + u32 offset;
> > +
> > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > +
> > + spin_lock_irqsave(&mmsys->lock, flags);
> > +
> > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + if (assert)
> > + reg &= ~BIT(id);
> > + else
> > + reg |= BIT(id);
> > +
> > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, true);
> > +}
> > +
> > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, false);
> > +}
> > +
> > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > unsigned long id)
> > +{
> > + int ret;
> > +
> > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(1000, 1100);
> > +
>
> One question that I received in my series, and I couldn't answer
> because I don't have the datasheet, is if
> is this known to be enough for all IP cores that can be reset by this
> controller? Is this time specified in the datasheet?
It only takes few cycles for the reset. The 1000us is enough for the
reset to take effect.
> > + return mtk_mmsys_reset_deassert(rcdev, id);
> > +}
> > +
> > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > + .assert = mtk_mmsys_reset_assert,
> > + .deassert = mtk_mmsys_reset_deassert,
> > + .reset = mtk_mmsys_reset,
> > +};
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > if (ret)
> > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > #endif
> > +
> > + spin_lock_init(&mmsys->lock);
> > +
> > + mmsys->rcdev.owner = THIS_MODULE;
> > + mmsys->rcdev.nr_resets = 64;
>
> Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> MT8183. Can you confirm?
>
> Thanks,
> Enric
>
The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
are not used).
> > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > >rcdev);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > controller: %d\n", ret);
> > + return ret;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys-
> > >data->clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 084b1f5f3c88..cc57c3895c51 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > const unsigned int num_routes;
> > const struct mtk_mmsys_config *config;
> > const unsigned int num_configs;
> > + u32 sw_reset_start;
> > };
> >
> > /*
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-28 6:00 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-28 6:00 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > Among other features the mmsys driver should implement a reset
> > controller to be able to reset different bits from their space.
> >
>
> I'm working on a series that does the same, it should be nice if we
> can coordinate [1]
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
>
>
OK, I will add this series to my reference base in the next patch
revision.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 77
> > +++++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > 3 files changed, 79 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 4bdb2087250c..a7f6e275bfe5 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,7 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > << 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > << 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index d0f4a407f8f8..1ae04efeadab 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,10 +4,12 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > #include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> >
> > #include "mtk-mmsys.h"
> > @@ -15,6 +17,8 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8195-mmsys.h"
> >
> > +#define MMSYS_SW_RESET_PER_REG 32
> > +
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> > .clk_driver = "clk-mt2701-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > .config = mmsys_mt8195_config_table,
> > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
>
> That change is interesting and I think I should also take it into
> consideration with my series.
>
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
>
> Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> I mean I know that for MT8173 and MT8183 the register is called
> mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> So maybe we should update this comment to be more generic.
>
Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
a different name. Maybe we can change the comment to "protects mmsys sw
reset reg".
> >
> > + struct reset_controller_dev rcdev;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > enum mtk_mmsys_config_type config,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> >
> > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> > + bool assert)
> > +{
> > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > mtk_mmsys, rcdev);
> > + unsigned long flags;
> > + u32 reg;
> > + int i;
> > + u32 offset;
> > +
> > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > +
> > + spin_lock_irqsave(&mmsys->lock, flags);
> > +
> > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + if (assert)
> > + reg &= ~BIT(id);
> > + else
> > + reg |= BIT(id);
> > +
> > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > >sw_reset_start + offset);
> > +
> > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, true);
> > +}
> > +
> > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > *rcdev, unsigned long id)
> > +{
> > + return mtk_mmsys_reset_update(rcdev, id, false);
> > +}
> > +
> > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > unsigned long id)
> > +{
> > + int ret;
> > +
> > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(1000, 1100);
> > +
>
> One question that I received in my series, and I couldn't answer
> because I don't have the datasheet, is if
> is this known to be enough for all IP cores that can be reset by this
> controller? Is this time specified in the datasheet?
It only takes few cycles for the reset. The 1000us is enough for the
reset to take effect.
> > + return mtk_mmsys_reset_deassert(rcdev, id);
> > +}
> > +
> > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > + .assert = mtk_mmsys_reset_assert,
> > + .deassert = mtk_mmsys_reset_deassert,
> > + .reset = mtk_mmsys_reset,
> > +};
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > if (ret)
> > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > #endif
> > +
> > + spin_lock_init(&mmsys->lock);
> > +
> > + mmsys->rcdev.owner = THIS_MODULE;
> > + mmsys->rcdev.nr_resets = 64;
>
> Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> MT8183. Can you confirm?
>
> Thanks,
> Enric
>
The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
are not used).
> > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > >rcdev);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > controller: %d\n", ret);
> > + return ret;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys-
> > >data->clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 084b1f5f3c88..cc57c3895c51 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > const unsigned int num_routes;
> > const struct mtk_mmsys_config *config;
> > const unsigned int num_configs;
> > + u32 sw_reset_start;
> > };
> >
> > /*
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-07-28 6:00 ` Nancy.Lin
(?)
(?)
@ 2021-07-28 10:31 ` Enric Balletbo Serra
-1 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-28 10:31 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de jul.
2021 a les 8:01:
>
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > Hi Nancy,
> >
> > Thank you for your patch.
> >
> > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > jul.
> > 2021 a les 11:46:
> > >
> > > Among other features the mmsys driver should implement a reset
> > > controller to be able to reset different bits from their space.
> > >
> >
> > I'm working on a series that does the same, it should be nice if we
> > can coordinate [1]
> >
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> >
> >
> OK, I will add this series to my reference base in the next patch
> revision.
>
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > +++++++++++++++++++++++++++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > 3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -154,6 +154,7 @@
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > << 0)
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > << 0)
> > >
> > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index d0f4a407f8f8..1ae04efeadab 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,10 +4,12 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > #include <linux/of_device.h>
> > > #include <linux/platform_device.h>
> > > +#include <linux/reset-controller.h>
> > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > >
> > > #include "mtk-mmsys.h"
> > > @@ -15,6 +17,8 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8195-mmsys.h"
> > >
> > > +#define MMSYS_SW_RESET_PER_REG 32
> > > +
> > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > > = {
> > > .clk_driver = "clk-mt2701-mm",
> > > .routes = mmsys_default_routing_table,
> > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys1_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > .config = mmsys_mt8195_config_table,
> > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> >
> > That change is interesting and I think I should also take it into
> > consideration with my series.
> >
> > > };
> > >
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > struct cmdq_client_reg cmdq_base;
> > > const struct mtk_mmsys_driver_data *data;
> > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >
> > Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> > I mean I know that for MT8173 and MT8183 the register is called
> > mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> > So maybe we should update this comment to be more generic.
> >
> Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
> and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
> a different name. Maybe we can change the comment to "protects mmsys sw
> reset reg".
>
> > >
>
> > > + struct reset_controller_dev rcdev;
> > > };
> > >
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > > enum mtk_mmsys_config_type config,
> > > }
> > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > >
> > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > *rcdev, unsigned long id,
> > > + bool assert)
> > > +{
> > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > mtk_mmsys, rcdev);
> > > + unsigned long flags;
> > > + u32 reg;
> > > + int i;
> > > + u32 offset;
> > > +
> > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > +
> > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > +
> > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + if (assert)
> > > + reg &= ~BIT(id);
> > > + else
> > > + reg |= BIT(id);
> > > +
> > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > unsigned long id)
> > > +{
> > > + int ret;
> > > +
> > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + usleep_range(1000, 1100);
> > > +
> >
> > One question that I received in my series, and I couldn't answer
> > because I don't have the datasheet, is if
> > is this known to be enough for all IP cores that can be reset by this
> > controller? Is this time specified in the datasheet?
>
> It only takes few cycles for the reset. The 1000us is enough for the
> reset to take effect.
>
Saying enough looks to me that 1000us is a random number, is there any
specific real number in the datasheet?
Note that I'm not against it, just want to make sure the number makes sense.
> > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > +}
> > > +
> > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > + .assert = mtk_mmsys_reset_assert,
> > > + .deassert = mtk_mmsys_reset_deassert,
> > > + .reset = mtk_mmsys_reset,
> > > +};
> > > +
> > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > if (ret)
> > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > #endif
> > > +
> > > + spin_lock_init(&mmsys->lock);
> > > +
> > > + mmsys->rcdev.owner = THIS_MODULE;
> > > + mmsys->rcdev.nr_resets = 64;
> >
> > Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> > MT8183. Can you confirm?
> >
> > Thanks,
> > Enric
> >
> The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
> are not used).
>
Ok, thanks for the information.
> > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > > >rcdev);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > > controller: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > >data->clk_driver,
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > index 084b1f5f3c88..cc57c3895c51 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > const unsigned int num_routes;
> > > const struct mtk_mmsys_config *config;
> > > const unsigned int num_configs;
> > > + u32 sw_reset_start;
> > > };
> > >
> > > /*
> > > --
> > > 2.18.0
> > >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-28 10:31 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-28 10:31 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de jul.
2021 a les 8:01:
>
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > Hi Nancy,
> >
> > Thank you for your patch.
> >
> > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > jul.
> > 2021 a les 11:46:
> > >
> > > Among other features the mmsys driver should implement a reset
> > > controller to be able to reset different bits from their space.
> > >
> >
> > I'm working on a series that does the same, it should be nice if we
> > can coordinate [1]
> >
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> >
> >
> OK, I will add this series to my reference base in the next patch
> revision.
>
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > +++++++++++++++++++++++++++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > 3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -154,6 +154,7 @@
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > << 0)
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > << 0)
> > >
> > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index d0f4a407f8f8..1ae04efeadab 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,10 +4,12 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > #include <linux/of_device.h>
> > > #include <linux/platform_device.h>
> > > +#include <linux/reset-controller.h>
> > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > >
> > > #include "mtk-mmsys.h"
> > > @@ -15,6 +17,8 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8195-mmsys.h"
> > >
> > > +#define MMSYS_SW_RESET_PER_REG 32
> > > +
> > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > > = {
> > > .clk_driver = "clk-mt2701-mm",
> > > .routes = mmsys_default_routing_table,
> > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys1_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > .config = mmsys_mt8195_config_table,
> > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> >
> > That change is interesting and I think I should also take it into
> > consideration with my series.
> >
> > > };
> > >
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > struct cmdq_client_reg cmdq_base;
> > > const struct mtk_mmsys_driver_data *data;
> > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >
> > Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> > I mean I know that for MT8173 and MT8183 the register is called
> > mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> > So maybe we should update this comment to be more generic.
> >
> Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
> and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
> a different name. Maybe we can change the comment to "protects mmsys sw
> reset reg".
>
> > >
>
> > > + struct reset_controller_dev rcdev;
> > > };
> > >
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > > enum mtk_mmsys_config_type config,
> > > }
> > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > >
> > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > *rcdev, unsigned long id,
> > > + bool assert)
> > > +{
> > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > mtk_mmsys, rcdev);
> > > + unsigned long flags;
> > > + u32 reg;
> > > + int i;
> > > + u32 offset;
> > > +
> > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > +
> > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > +
> > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + if (assert)
> > > + reg &= ~BIT(id);
> > > + else
> > > + reg |= BIT(id);
> > > +
> > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > unsigned long id)
> > > +{
> > > + int ret;
> > > +
> > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + usleep_range(1000, 1100);
> > > +
> >
> > One question that I received in my series, and I couldn't answer
> > because I don't have the datasheet, is if
> > is this known to be enough for all IP cores that can be reset by this
> > controller? Is this time specified in the datasheet?
>
> It only takes few cycles for the reset. The 1000us is enough for the
> reset to take effect.
>
Saying enough looks to me that 1000us is a random number, is there any
specific real number in the datasheet?
Note that I'm not against it, just want to make sure the number makes sense.
> > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > +}
> > > +
> > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > + .assert = mtk_mmsys_reset_assert,
> > > + .deassert = mtk_mmsys_reset_deassert,
> > > + .reset = mtk_mmsys_reset,
> > > +};
> > > +
> > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > if (ret)
> > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > #endif
> > > +
> > > + spin_lock_init(&mmsys->lock);
> > > +
> > > + mmsys->rcdev.owner = THIS_MODULE;
> > > + mmsys->rcdev.nr_resets = 64;
> >
> > Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> > MT8183. Can you confirm?
> >
> > Thanks,
> > Enric
> >
> The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
> are not used).
>
Ok, thanks for the information.
> > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > > >rcdev);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > > controller: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > >data->clk_driver,
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > index 084b1f5f3c88..cc57c3895c51 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > const unsigned int num_routes;
> > > const struct mtk_mmsys_config *config;
> > > const unsigned int num_configs;
> > > + u32 sw_reset_start;
> > > };
> > >
> > > /*
> > > --
> > > 2.18.0
> > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-28 10:31 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-28 10:31 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Nancy,
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de jul.
2021 a les 8:01:
>
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > Hi Nancy,
> >
> > Thank you for your patch.
> >
> > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > jul.
> > 2021 a les 11:46:
> > >
> > > Among other features the mmsys driver should implement a reset
> > > controller to be able to reset different bits from their space.
> > >
> >
> > I'm working on a series that does the same, it should be nice if we
> > can coordinate [1]
> >
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> >
> >
> OK, I will add this series to my reference base in the next patch
> revision.
>
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > +++++++++++++++++++++++++++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > 3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -154,6 +154,7 @@
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > << 0)
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > << 0)
> > >
> > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index d0f4a407f8f8..1ae04efeadab 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,10 +4,12 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > #include <linux/of_device.h>
> > > #include <linux/platform_device.h>
> > > +#include <linux/reset-controller.h>
> > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > >
> > > #include "mtk-mmsys.h"
> > > @@ -15,6 +17,8 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8195-mmsys.h"
> > >
> > > +#define MMSYS_SW_RESET_PER_REG 32
> > > +
> > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > > = {
> > > .clk_driver = "clk-mt2701-mm",
> > > .routes = mmsys_default_routing_table,
> > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys1_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > .config = mmsys_mt8195_config_table,
> > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> >
> > That change is interesting and I think I should also take it into
> > consideration with my series.
> >
> > > };
> > >
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > struct cmdq_client_reg cmdq_base;
> > > const struct mtk_mmsys_driver_data *data;
> > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >
> > Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> > I mean I know that for MT8173 and MT8183 the register is called
> > mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> > So maybe we should update this comment to be more generic.
> >
> Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
> and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
> a different name. Maybe we can change the comment to "protects mmsys sw
> reset reg".
>
> > >
>
> > > + struct reset_controller_dev rcdev;
> > > };
> > >
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > > enum mtk_mmsys_config_type config,
> > > }
> > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > >
> > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > *rcdev, unsigned long id,
> > > + bool assert)
> > > +{
> > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > mtk_mmsys, rcdev);
> > > + unsigned long flags;
> > > + u32 reg;
> > > + int i;
> > > + u32 offset;
> > > +
> > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > +
> > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > +
> > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + if (assert)
> > > + reg &= ~BIT(id);
> > > + else
> > > + reg |= BIT(id);
> > > +
> > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > unsigned long id)
> > > +{
> > > + int ret;
> > > +
> > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + usleep_range(1000, 1100);
> > > +
> >
> > One question that I received in my series, and I couldn't answer
> > because I don't have the datasheet, is if
> > is this known to be enough for all IP cores that can be reset by this
> > controller? Is this time specified in the datasheet?
>
> It only takes few cycles for the reset. The 1000us is enough for the
> reset to take effect.
>
Saying enough looks to me that 1000us is a random number, is there any
specific real number in the datasheet?
Note that I'm not against it, just want to make sure the number makes sense.
> > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > +}
> > > +
> > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > + .assert = mtk_mmsys_reset_assert,
> > > + .deassert = mtk_mmsys_reset_deassert,
> > > + .reset = mtk_mmsys_reset,
> > > +};
> > > +
> > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > if (ret)
> > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > #endif
> > > +
> > > + spin_lock_init(&mmsys->lock);
> > > +
> > > + mmsys->rcdev.owner = THIS_MODULE;
> > > + mmsys->rcdev.nr_resets = 64;
> >
> > Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> > MT8183. Can you confirm?
> >
> > Thanks,
> > Enric
> >
> The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
> are not used).
>
Ok, thanks for the information.
> > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > > >rcdev);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > > controller: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > >data->clk_driver,
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > index 084b1f5f3c88..cc57c3895c51 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > const unsigned int num_routes;
> > > const struct mtk_mmsys_config *config;
> > > const unsigned int num_configs;
> > > + u32 sw_reset_start;
> > > };
> > >
> > > /*
> > > --
> > > 2.18.0
> > >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-28 10:31 ` Enric Balletbo Serra
0 siblings, 0 replies; 99+ messages in thread
From: Enric Balletbo Serra @ 2021-07-28 10:31 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Nancy,
Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de jul.
2021 a les 8:01:
>
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > Hi Nancy,
> >
> > Thank you for your patch.
> >
> > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > jul.
> > 2021 a les 11:46:
> > >
> > > Among other features the mmsys driver should implement a reset
> > > controller to be able to reset different bits from their space.
> > >
> >
> > I'm working on a series that does the same, it should be nice if we
> > can coordinate [1]
> >
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> >
> >
> OK, I will add this series to my reference base in the next patch
> revision.
>
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > +++++++++++++++++++++++++++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > 3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -154,6 +154,7 @@
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > << 0)
> > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > << 0)
> > >
> > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index d0f4a407f8f8..1ae04efeadab 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,10 +4,12 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > #include <linux/of_device.h>
> > > #include <linux/platform_device.h>
> > > +#include <linux/reset-controller.h>
> > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > >
> > > #include "mtk-mmsys.h"
> > > @@ -15,6 +17,8 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8195-mmsys.h"
> > >
> > > +#define MMSYS_SW_RESET_PER_REG 32
> > > +
> > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > > = {
> > > .clk_driver = "clk-mt2701-mm",
> > > .routes = mmsys_default_routing_table,
> > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys1_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > .config = mmsys_mt8195_config_table,
> > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> >
> > That change is interesting and I think I should also take it into
> > consideration with my series.
> >
> > > };
> > >
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > struct cmdq_client_reg cmdq_base;
> > > const struct mtk_mmsys_driver_data *data;
> > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >
> > Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> > I mean I know that for MT8173 and MT8183 the register is called
> > mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> > So maybe we should update this comment to be more generic.
> >
> Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
> and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
> a different name. Maybe we can change the comment to "protects mmsys sw
> reset reg".
>
> > >
>
> > > + struct reset_controller_dev rcdev;
> > > };
> > >
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > > enum mtk_mmsys_config_type config,
> > > }
> > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > >
> > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > *rcdev, unsigned long id,
> > > + bool assert)
> > > +{
> > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > mtk_mmsys, rcdev);
> > > + unsigned long flags;
> > > + u32 reg;
> > > + int i;
> > > + u32 offset;
> > > +
> > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > +
> > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > +
> > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + if (assert)
> > > + reg &= ~BIT(id);
> > > + else
> > > + reg |= BIT(id);
> > > +
> > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > unsigned long id)
> > > +{
> > > + int ret;
> > > +
> > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + usleep_range(1000, 1100);
> > > +
> >
> > One question that I received in my series, and I couldn't answer
> > because I don't have the datasheet, is if
> > is this known to be enough for all IP cores that can be reset by this
> > controller? Is this time specified in the datasheet?
>
> It only takes few cycles for the reset. The 1000us is enough for the
> reset to take effect.
>
Saying enough looks to me that 1000us is a random number, is there any
specific real number in the datasheet?
Note that I'm not against it, just want to make sure the number makes sense.
> > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > +}
> > > +
> > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > + .assert = mtk_mmsys_reset_assert,
> > > + .deassert = mtk_mmsys_reset_deassert,
> > > + .reset = mtk_mmsys_reset,
> > > +};
> > > +
> > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > if (ret)
> > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > #endif
> > > +
> > > + spin_lock_init(&mmsys->lock);
> > > +
> > > + mmsys->rcdev.owner = THIS_MODULE;
> > > + mmsys->rcdev.nr_resets = 64;
> >
> > Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> > MT8183. Can you confirm?
> >
> > Thanks,
> > Enric
> >
> The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
> are not used).
>
Ok, thanks for the information.
> > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > > >rcdev);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "Couldn't register mmsys reset
> > > controller: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > >data->clk_driver,
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > index 084b1f5f3c88..cc57c3895c51 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > const unsigned int num_routes;
> > > const struct mtk_mmsys_config *config;
> > > const unsigned int num_configs;
> > > + u32 sw_reset_start;
> > > };
> > >
> > > /*
> > > --
> > > 2.18.0
> > >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
2021-07-27 23:39 ` Chun-Kuang Hu
(?)
@ 2021-07-29 5:28 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-29 5:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, srv_heupstream, DTML, David Airlie, jason-jh . lin,
singo.chang, linux-kernel, DRI Development, Yongqiang Niu,
Rob Herring, moderated list:ARM/Mediatek SoC support,
Matthias Brugger, Linux ARM
Hi Chun-Kuang,
Thanks for your review.
On Wed, 2021-07-28 at 07:39 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 413
> > ++++++++++++++++++++++++
> > 5 files changed, 435 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 31613564f499..b4b305d58b0f 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > mtk_disp_pseudo_ovl.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..464db52131db 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ethdr_disable_vblank(struct device *dev);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..58f9f9f06e94 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_PSEUDO_OVL },
> > { }
> > };
> >
> > @@ -676,6 +678,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..26e079323de0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,413 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *pseudo_ovl_dev;
> > + struct device *mmsys_dev;
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
>
> I think register callback function need to be protected like [1].
>
> [1]
> https://urldefense.com/v3/__https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/*/3021203__;Kw!!CTRNKA9wMg0ARbw!wCK9OXFCyRgGVJpvcfDrfxp5ALss3HpyazBoU0yAlg0gSBXeOpYGaELw54cYmHbF$
>
OK, I will add the protection.
>
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
>
> Ditto.
>
OK.
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + if (!priv->vblank_cb)
> > + return IRQ_NONE;
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx,
> > state, cmdq_pkt);
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + return;
> > + }
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + int i;
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh,
> > bpc, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe0->cmdq_base,
> > + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe1->cmdq_base,
> > + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe0->cmdq_base,
> > + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe1->cmdq_base,
> > + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL,
> > &vdo_be->cmdq_base,
> > + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> > +
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> > + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_SIZE);
> > + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_BGCLR);
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(0));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(1));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(2));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(3));
> > + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(0));
> > + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL |
> > BACKGROUND_RELAY,
> > + &mixer->cmdq_base, mixer->regs,
> > MIX_DATAPATH_CON);
> > + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_SRC_CON, MIX_SRC_L0_EN);
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > + (w / 2), cmdq_pkt);
>
> Remove parentheses of (w / 2).
>
OK, I will remove it.
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > + h, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> > +
> > + for (i = 1; i <= 4; i++) {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
>
> Could these be moved to mtk_ethdr_layer_config()? That means you
> config the i only for the layer is on.
>
OK, I will move it to mtk_ethdr_layer_config.
> > + }
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> whitel();
>
OK, I will modify it.
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> ditto.
OK, I will modify it.
>
> Regards,
> Chun-Kuang.
>
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > + reset_control_reset(devm_reset_control_array_get(dev, true,
> > true));
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > +}
> > +
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-29 5:28 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-29 5:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, srv_heupstream, DTML, David Airlie, jason-jh . lin,
singo.chang, linux-kernel, DRI Development, Yongqiang Niu,
Rob Herring, moderated list:ARM/Mediatek SoC support,
Matthias Brugger, Linux ARM
Hi Chun-Kuang,
Thanks for your review.
On Wed, 2021-07-28 at 07:39 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 413
> > ++++++++++++++++++++++++
> > 5 files changed, 435 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 31613564f499..b4b305d58b0f 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > mtk_disp_pseudo_ovl.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..464db52131db 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ethdr_disable_vblank(struct device *dev);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..58f9f9f06e94 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_PSEUDO_OVL },
> > { }
> > };
> >
> > @@ -676,6 +678,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..26e079323de0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,413 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *pseudo_ovl_dev;
> > + struct device *mmsys_dev;
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
>
> I think register callback function need to be protected like [1].
>
> [1]
> https://urldefense.com/v3/__https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/*/3021203__;Kw!!CTRNKA9wMg0ARbw!wCK9OXFCyRgGVJpvcfDrfxp5ALss3HpyazBoU0yAlg0gSBXeOpYGaELw54cYmHbF$
>
OK, I will add the protection.
>
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
>
> Ditto.
>
OK.
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + if (!priv->vblank_cb)
> > + return IRQ_NONE;
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx,
> > state, cmdq_pkt);
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + return;
> > + }
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + int i;
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh,
> > bpc, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe0->cmdq_base,
> > + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe1->cmdq_base,
> > + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe0->cmdq_base,
> > + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe1->cmdq_base,
> > + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL,
> > &vdo_be->cmdq_base,
> > + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> > +
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> > + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_SIZE);
> > + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_BGCLR);
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(0));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(1));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(2));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(3));
> > + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(0));
> > + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL |
> > BACKGROUND_RELAY,
> > + &mixer->cmdq_base, mixer->regs,
> > MIX_DATAPATH_CON);
> > + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_SRC_CON, MIX_SRC_L0_EN);
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > + (w / 2), cmdq_pkt);
>
> Remove parentheses of (w / 2).
>
OK, I will remove it.
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > + h, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> > +
> > + for (i = 1; i <= 4; i++) {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
>
> Could these be moved to mtk_ethdr_layer_config()? That means you
> config the i only for the layer is on.
>
OK, I will move it to mtk_ethdr_layer_config.
> > + }
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> whitel();
>
OK, I will modify it.
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> ditto.
OK, I will modify it.
>
> Regards,
> Chun-Kuang.
>
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > + reset_control_reset(devm_reset_control_array_get(dev, true,
> > true));
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > +}
> > +
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 13/14] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-29 5:28 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-29 5:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, srv_heupstream, David Airlie, jason-jh . lin, singo.chang,
linux-kernel, DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Chun-Kuang,
Thanks for your review.
On Wed, 2021-07-28 at 07:39 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 413
> > ++++++++++++++++++++++++
> > 5 files changed, 435 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 31613564f499..b4b305d58b0f 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -15,7 +15,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > mtk_disp_pseudo_ovl.o \
> > - mtk_mdp_rdma.o
> > + mtk_mdp_rdma.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..464db52131db 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,20 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ethdr_disable_vblank(struct device *dev);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +unsigned int mtk_ethdr_layer_nr(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..58f9f9f06e94 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_PSEUDO_OVL },
> > { }
> > };
> >
> > @@ -676,6 +678,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..26e079323de0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,413 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *pseudo_ovl_dev;
> > + struct device *mmsys_dev;
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
>
> I think register callback function need to be protected like [1].
>
> [1]
> https://urldefense.com/v3/__https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/*/3021203__;Kw!!CTRNKA9wMg0ARbw!wCK9OXFCyRgGVJpvcfDrfxp5ALss3HpyazBoU0yAlg0gSBXeOpYGaELw54cYmHbF$
>
OK, I will add the protection.
>
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
>
> Ditto.
>
OK.
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + if (!priv->vblank_cb)
> > + return IRQ_NONE;
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + mtk_pseudo_ovl_layer_config(priv->pseudo_ovl_dev, idx,
> > state, cmdq_pkt);
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + return;
> > + }
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, src_size, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + int i;
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_config(priv->pseudo_ovl_dev, w, h, vrefresh,
> > bpc, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe0->cmdq_base,
> > + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL,
> > &vdo_fe1->cmdq_base,
> > + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe0->cmdq_base,
> > + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL,
> > &gfx_fe1->cmdq_base,
> > + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
> > +
> > + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL,
> > &vdo_be->cmdq_base,
> > + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
> > +
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM0);
> > + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer-
> > >cmdq_base, mixer->regs, MIX_FUNC_DCM1);
> > + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_SIZE);
> > + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base,
> > mixer->regs, MIX_ROI_BGCLR);
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(0));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(1));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(2));
> > + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_L_SRC_CON(3));
> > + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_SIZE(0));
> > + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL |
> > BACKGROUND_RELAY,
> > + &mixer->cmdq_base, mixer->regs,
> > MIX_DATAPATH_CON);
> > + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer-
> > >cmdq_base, mixer->regs,
> > + MIX_SRC_CON, MIX_SRC_L0_EN);
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > + (w / 2), cmdq_pkt);
>
> Remove parentheses of (w / 2).
>
OK, I will remove it.
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > + h, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
> > +
> > + for (i = 1; i <= 4; i++) {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, i,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
>
> Could these be moved to mtk_ethdr_layer_config()? That means you
> config the i only for the layer is on.
>
OK, I will move it to mtk_ethdr_layer_config.
> > + }
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_start(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> whitel();
>
OK, I will modify it.
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_pseudo_ovl_stop(priv->pseudo_ovl_dev);
> > +
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN);
>
> ditto.
OK, I will modify it.
>
> Regards,
> Chun-Kuang.
>
> > + mtk_ddp_write(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > + reset_control_reset(devm_reset_control_array_get(dev, true,
> > true));
> > + mtk_ddp_write(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST);
> > +}
> > +
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
2021-07-25 1:57 ` Chun-Kuang Hu
(?)
@ 2021-07-30 3:28 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for your review.
On Sun, 2021-07-25 at 09:57 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add pseudo ovl module files:
>
> My English is not good. The word 'pseudo' seems like 'looks like but
> indeed not the same'.
> I think the 'real' ovl also has rdma and mixer inside it, so I prefer
> to treat these two ovl as different kind of ovl, not a real one and a
> pseudo one.
> Does I misunderstanding the word 'pseudo'?
>
I was thinking of encapsulating several engines in this component. The
prefix "pseudo" was meant to distinguish with the origin ovl. I will
change pseudo_ovl to ovl_adaptor.
> > Pseudo ovl is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 4 +-
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> > drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
>
> Seperate mtk_dmp_rdma driver to an independent patch.
>
OK, I will separate it.
> > 6 files changed, 1344 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..31613564f499 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_disp_pseudo_ovl.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > new file mode 100644
> > index 000000000000..0446fa99dd0a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > @@ -0,0 +1,593 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_mdp_rdma.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
>
> Which hardware has this limitation? I would like this naming to
> reflect which hardware has this limitation.
>
RDMA has the limitation, I will modify its naming.
> > +
> > +enum mtk_pseudo_ovl_comp_type {
> > + PSEUDO_OVL_TYPE_RDMA = 0,
> > + PSEUDO_OVL_TYPE_MERGE,
> > + PSEUDO_OVL_TYPE_NUM,
> > +};
> > +
> > +enum mtk_pseudo_ovl_comp_id {
> > + PSEUDO_OVL_RDMA_BASE = 0,
> > + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
>
> I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
> PSEUDO_OVL_RDMA_BASE.
>
OK, I will remove it.
> > + PSEUDO_OVL_MDP_RDMA1,
> > + PSEUDO_OVL_MDP_RDMA2,
> > + PSEUDO_OVL_MDP_RDMA3,
> > + PSEUDO_OVL_MDP_RDMA4,
> > + PSEUDO_OVL_MDP_RDMA5,
> > + PSEUDO_OVL_MDP_RDMA6,
> > + PSEUDO_OVL_MDP_RDMA7,
> > + PSEUDO_OVL_MERGE_BASE,
> > + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
>
> Ditto.
OK, I will remove it.
>
> > + PSEUDO_OVL_MERGE1,
> > + PSEUDO_OVL_MERGE2,
> > + PSEUDO_OVL_MERGE3,
> > + PSEUDO_OVL_ID_MAX
> > +};
> > +
> > +struct pseudo_ovl_data {
> > + unsigned int layer_nr;
> > + struct mtk_mdp_rdma_fifo fifo;
> > +};
> > +
> > +struct pseudo_ovl_comp_match {
> > + enum mtk_pseudo_ovl_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct pseudo_ovl_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_pseudo_ovl_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
> > +
> > +struct mtk_disp_pseudo_ovl {
> > + struct mtk_pseudo_ovl_comp
> > pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> > + const struct pseudo_ovl_data *data;
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const pseudo_ovl_comp_str[] = {
> > + "PSEUDO_OVL_MDP_RDMA0",
> > + "PSEUDO_OVL_MDP_RDMA1",
> > + "PSEUDO_OVL_MDP_RDMA2",
> > + "PSEUDO_OVL_MDP_RDMA3",
> > + "PSEUDO_OVL_MDP_RDMA4",
> > + "PSEUDO_OVL_MDP_RDMA5",
> > + "PSEUDO_OVL_MDP_RDMA6",
> > + "PSEUDO_OVL_MDP_RDMA7",
> > + "PSEUDO_OVL_MERGE0",
> > + "PSEUDO_OVL_MERGE1",
> > + "PSEUDO_OVL_MERGE2",
> > + "PSEUDO_OVL_MERGE3",
> > + "PSEUDO_OVL_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] =
> > {
> > + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> > + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct pseudo_ovl_comp_match
> > comp_matches[PSEUDO_OVL_ID_MAX] = {
> > + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0
> > },
> > + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1
> > },
> > + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2
> > },
> > + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3
> > },
> > + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4
> > },
> > + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5
> > },
> > + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6
> > },
> > + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7
> > },
> > + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> > + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> > + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> > + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> > +};
> > +
> > +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl
> > *pseudo_ovl,
> > + struct cmdq_pkt *handle)
> > +{
> > + struct mtk_pseudo_ovl_comp *rdma = NULL;
> > + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> > + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7;
> > i++) {
> > + rdma = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> > + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma-
> > >cmdq_base, fifo);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp
> > *comp,
> > + struct
> > pseudo_ovl_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_5);
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > +}
> > +
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct pseudo_ovl_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx];
> > + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx + 1];
> > + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE
> > + idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > +
> > + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.encode_type = RDMA_ENCODE_NONE;
> > + rdma_config.block_size = RDMA_BLOCK_NONE;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> > +}
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev)
> > +{
> > +}
> > +
> > +void mtk_pseudo_ovl_stop(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> > + rdma_l = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> > + rdma_r = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> > + merge = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int pseudo_ovl_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_pseudo_ovl_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_pseudo_ovl_comp *comp,
> > + enum mtk_pseudo_ovl_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < PSEUDO_OVL_MERGE_BASE)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > pseudo_ovl_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> > + .probe = mtk_disp_pseudo_ovl_comp_probe,
> > + .remove = mtk_disp_pseudo_ovl_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> > +
> > +static int pseudo_ovl_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_pseudo_ovl_comp_type type;
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> > + id = pseudo_ovl_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >pseudo_ovl_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data
> > = {
> > + .layer_nr = 4,
> > + .fifo.read_request_type = 7,
> > + .fifo.command_div = 1,
> > + .fifo.ext_preutra_en = 1,
> > + .fifo.ultra_en = 0,
> > + .fifo.pre_ultra_en = 1,
> > + .fifo.ext_ultra_en = 1,
> > + .fifo.extrd_arb_max_0 = 3,
> > + .fifo.buf_resv_size_0 = 0,
> > + .fifo.issue_req_th_0 = 0,
> > + .fifo.ultra_h_con_0 = 156,
> > + .fifo.ultra_l_con_0 = 104,
> > +};
>
> Now only support one SoC, so remove driver data and change these to
> definition instead of variable.
>
OK, I will remove it.
> > +
> > +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = &mt8195_pseudo_ovl_driver_data},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> > +
> > +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + priv->data = of_id->data;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = pseudo_ovl_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "pseudo_ovl comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE;
> > i++)
> > + pm_runtime_disable(pseudo_ovl-
> > >pseudo_ovl_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> > + .probe = mtk_disp_pseudo_ovl_probe,
> > + .remove = mtk_disp_pseudo_ovl_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > new file mode 100644
> > index 000000000000..b3fe1e1702b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> > +#define __MTK_DISP_PSEUDO_OVL_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev);
> > +void mtk_pseudo_ovl_stop(struct device *dev);
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..81d3cc4872eb
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,456 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_mdp_reg_rdma.h"
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define RDMA_INPUT_SWAP BIT(14)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define IRQ_INT_EN_ALL \
> > + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> > + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> > + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> > +
> > +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 2 * width;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 3 * width;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + case DRM_FORMAT_ARGB2101010:
> > + case DRM_FORMAT_ABGR2101010:
> > + case DRM_FORMAT_RGBA1010102:
> > + case DRM_FORMAT_BGRA1010102:
> > + return 4 * width;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 2 * width;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 4 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_block_h(unsigned int mode)
> > +{
> > + switch (mode) {
> > + default:
> > + return 0;
> > + case RDMA_BLOCK_8x8:
> > + case RDMA_BLOCK_16x8:
> > + case RDMA_BLOCK_32x8:
> > + return 8;
> > + case RDMA_BLOCK_8x16:
> > + case RDMA_BLOCK_16x16:
> > + case RDMA_BLOCK_32x16:
> > + return 16;
> > + case RDMA_BLOCK_8x32:
> > + case RDMA_BLOCK_16x32:
> > + case RDMA_BLOCK_32x32:
> > + return 32;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 16;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 24;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return 32;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 16;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 8;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 16;
> > + }
> > +}
> > +
> > +static bool with_alpha(uint32_t format)
> > +{
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(format);
> > +
> > + return fmt_info->has_alpha;
> > +}
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int inten = IRQ_INT_EN_ALL;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
>
> Why do you enable rdma interrupt?
>
I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > +}
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 0), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_STATUS,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > +}
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo *fifo)
>
> Why do you pass fifo config from ovl to rdma?
> I think just rdma know how to set these fifo parameter.
>
I will move fifo setting inside the rdma driver.
> > +{
> > + int reg;
> > + int reg_val;
> > + int reg_mask;
> > +
> > + reg = MDP_RDMA_GMCIF_CON;
> > + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo-
> > >read_request_type) |
> > + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> > + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo-
> > >ext_preutra_en) |
> > + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> > + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> > + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo-
> > >ext_ultra_en);
> > + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> > + REG_FLD_MASK(FLD_COMMAND_DIV) |
> > + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> > + REG_FLD_MASK(FLD_ULTRA_EN) |
> > + REG_FLD_MASK(PRE_ULTRA_EN) |
> > + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMA_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo-
> > >extrd_arb_max_0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo-
> > >buf_resv_size_0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo-
> > >issue_req_th_0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo-
> > >ultra_h_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_L_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo-
> > >ultra_l_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +}
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt,
> > cfg->source_width);
> > + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg-
> > >source_width);
>
> This is got from mtk_plane_atomic_update().
>
OK,I will modify it.
> > + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg-
> > >fmt);
> > + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg-
> > >fmt);
> > + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> > + unsigned int block_h = rdma_get_block_h(cfg->block_size);
>
> block_h = 0;
OK, I will modify it.
>
> > + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
>
> drm_format_info().
OK, I will modify it.
>
> > + unsigned int y_start_line = 0;
> > + unsigned int offset_y = 0;
> > + unsigned int offset_u = 0;
> > + unsigned int offset_v = 0;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> > + cmdq_base, base, MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > cmdq_base,
> > + base, MDP_RDMA_SRC_CON,
> > REG_FLD_MASK(FLD_SWAP) |
> > + REG_FLD_MASK(FLD_SRC_FORMAT) |
> > + REG_FLD_MASK(FLD_BIT_NUMBER));
> > +
> > + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_0,
> > REG_FLD_MASK(FLD_SRC_BASE_0));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_1,
> > REG_FLD_MASK(FLD_SRC_BASE_1));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_2,
> > REG_FLD_MASK(FLD_SRC_BASE_2));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_MF_BKGD_WB));
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> > + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_SF_BKGD_WB));
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
>
OK, I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_MF_BKGD_WP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_BKGD_HP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_OUTPUT_10B));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_SIMPLE_MODE));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg-
> > >csc_enable),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_TRANS_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> > +
> > + if (cfg->block_size == RDMA_BLOCK_NONE) {
> > + y_start_line = cfg->y_top;
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) +
> > y_start_line * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + } else {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> > + (cfg->y_top) * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + }
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_WP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_WP))
> > ;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_HP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_HP))
> > ;
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0,
> > offset_y),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1,
> > offset_u),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2,
> > offset_v),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg-
> > >width),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg-
> > >height),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W,
> > cfg->width),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H,
> > cfg->height),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> > +}
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..c16bfb716610
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,109 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +enum rdma_profile {
> > + RDMA_CSC_RGB_TO_JPEG = 0,
> > + RDMA_CSC_RGB_TO_FULL709 = 1,
> > + RDMA_CSC_RGB_TO_BT601 = 2,
> > + RDMA_CSC_RGB_TO_BT709 = 3,
> > + RDMA_CSC_JPEG_TO_RGB = 4,
> > + RDMA_CSC_FULL709_TO_RGB = 5,
> > + RDMA_CSC_BT601_TO_RGB = 6,
> > + RDMA_CSC_BT709_TO_RGB = 7,
> > + RDMA_CSC_JPEG_TO_BT601 = 8,
> > + RDMA_CSC_JPEG_TO_BT709 = 9,
> > + RDMA_CSC_BT601_TO_JPEG = 10,
> > + RDMA_CSC_BT709_TO_BT601 = 11,
> > + RDMA_CSC_BT601_TO_BT709 = 12
> > +};
> > +
> > +enum rdma_encode {
> > + RDMA_ENCODE_NONE = 0,
> > + RDMA_ENCODE_AFBC = 1,
> > + RDMA_ENCODE_HYFBC = 2,
> > + RDMA_ENCODE_UFO_DCP = 3
> > +};
> > +
> > +enum rdma_block {
> > + RDMA_BLOCK_NONE = 0,
> > + RDMA_BLOCK_8x8 = 1,
> > + RDMA_BLOCK_8x16 = 2,
> > + RDMA_BLOCK_8x32 = 3,
> > + RDMA_BLOCK_16x8 = 4,
> > + RDMA_BLOCK_16x16 = 5,
> > + RDMA_BLOCK_16x32 = 6,
> > + RDMA_BLOCK_32x8 = 7,
> > + RDMA_BLOCK_32x16 = 8,
> > + RDMA_BLOCK_32x32 = 9
> > +};
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + enum rdma_encode encode_type;
> > + enum rdma_block block_size;
> > + enum rdma_profile profile;
> > + unsigned int source_width;
> > + unsigned int addr0;
> > + unsigned int addr1;
> > + unsigned int addr2;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + bool csc_enable;
> > + int fmt;
> > +};
> > +
> > +struct mtk_mdp_rdma_fifo {
> > + int read_request_type;
> > + int command_div;
> > + int ext_preutra_en;
> > + int ultra_en;
> > + int pre_ultra_en;
> > + int ext_ultra_en;
> > + int extrd_arb_max_0;
> > + int buf_resv_size_0;
> > + int issue_req_th_0;
> > + int ultra_h_con_0;
> > + int ultra_l_con_0;
> > +};
>
> Move rdma internal definition in .c file.
>
OK, I will move it to internal .c file.
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo
> > *fifo);
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base,
> > + struct mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
>
> Move these prototype to mtk_disp_drv.h
>
OK.
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > new file mode 100644
> > index 000000000000..08abd9f39bd8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > @@ -0,0 +1,160 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MDP_RDMA_REGS_H__
> > +#define __MDP_RDMA_REGS_H__
> > +
> > +#define REG_FLD(width, shift) \
> > + ((unsigned int)((((width) & 0xff) << 16) | ((shift) &
> > 0xff)))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > + << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
> > +#define
> > MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_RESET 0x008
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_ENABLE 0x010
> > +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> > +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> > +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_STATUS 0x018
> > +
> > +#define
> > MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> > +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> > +
> > +#define
> > MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> > +#define PRE_ULTRA_EN REG_FLD(2, 16)
> > +#define FLD_ULTRA_EN REG_FLD(2, 12)
> > +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> > +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> > +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> > +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> > +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> > +#define FLD_SWAP REG_FLD(1, 14)
> > +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> > +
> > +#define
> > MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN REG_FLD(1, 22)
> > +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> > +#define FLD_UFBDC_EN REG_FLD(1, 12)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> > +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H REG_FLD(15, 16)
> > +#define FLD_MF_SRC_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> > +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_OFFSET_1 0x080
> > +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> > +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> > +
> > +#define
> > MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> > +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> > +#define FLD_BKGD_HP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_TARGET_LINE 0x0a0
> > +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> > +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_1 0x120
> > +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_2 0x128
> > +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_WP 0x148
> > +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_HP 0x150
> > +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> > +#define FLD_TRANS_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_DMA_CON_0 0x240
> > +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> > +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_0 0x248
> > +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_UTRA_L_CON_0 0x250
> > +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_1 0x258
> > +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> > +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_2 0x270
> > +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_2 0x278
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_3 0x288
> > +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_3 0x290
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_1 0xf08
> > +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_2 0xf10
> > +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> > +
> > +#endif /* __MDP_RDMA_REGS_H__ */
>
> Only one file need these, so move register definiton in .c file.
>
OK.
> Regards,
> Chun-Kuang.
>
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-30 3:28 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for your review.
On Sun, 2021-07-25 at 09:57 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add pseudo ovl module files:
>
> My English is not good. The word 'pseudo' seems like 'looks like but
> indeed not the same'.
> I think the 'real' ovl also has rdma and mixer inside it, so I prefer
> to treat these two ovl as different kind of ovl, not a real one and a
> pseudo one.
> Does I misunderstanding the word 'pseudo'?
>
I was thinking of encapsulating several engines in this component. The
prefix "pseudo" was meant to distinguish with the origin ovl. I will
change pseudo_ovl to ovl_adaptor.
> > Pseudo ovl is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 4 +-
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> > drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
>
> Seperate mtk_dmp_rdma driver to an independent patch.
>
OK, I will separate it.
> > 6 files changed, 1344 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..31613564f499 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_disp_pseudo_ovl.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > new file mode 100644
> > index 000000000000..0446fa99dd0a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > @@ -0,0 +1,593 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_mdp_rdma.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
>
> Which hardware has this limitation? I would like this naming to
> reflect which hardware has this limitation.
>
RDMA has the limitation, I will modify its naming.
> > +
> > +enum mtk_pseudo_ovl_comp_type {
> > + PSEUDO_OVL_TYPE_RDMA = 0,
> > + PSEUDO_OVL_TYPE_MERGE,
> > + PSEUDO_OVL_TYPE_NUM,
> > +};
> > +
> > +enum mtk_pseudo_ovl_comp_id {
> > + PSEUDO_OVL_RDMA_BASE = 0,
> > + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
>
> I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
> PSEUDO_OVL_RDMA_BASE.
>
OK, I will remove it.
> > + PSEUDO_OVL_MDP_RDMA1,
> > + PSEUDO_OVL_MDP_RDMA2,
> > + PSEUDO_OVL_MDP_RDMA3,
> > + PSEUDO_OVL_MDP_RDMA4,
> > + PSEUDO_OVL_MDP_RDMA5,
> > + PSEUDO_OVL_MDP_RDMA6,
> > + PSEUDO_OVL_MDP_RDMA7,
> > + PSEUDO_OVL_MERGE_BASE,
> > + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
>
> Ditto.
OK, I will remove it.
>
> > + PSEUDO_OVL_MERGE1,
> > + PSEUDO_OVL_MERGE2,
> > + PSEUDO_OVL_MERGE3,
> > + PSEUDO_OVL_ID_MAX
> > +};
> > +
> > +struct pseudo_ovl_data {
> > + unsigned int layer_nr;
> > + struct mtk_mdp_rdma_fifo fifo;
> > +};
> > +
> > +struct pseudo_ovl_comp_match {
> > + enum mtk_pseudo_ovl_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct pseudo_ovl_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_pseudo_ovl_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
> > +
> > +struct mtk_disp_pseudo_ovl {
> > + struct mtk_pseudo_ovl_comp
> > pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> > + const struct pseudo_ovl_data *data;
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const pseudo_ovl_comp_str[] = {
> > + "PSEUDO_OVL_MDP_RDMA0",
> > + "PSEUDO_OVL_MDP_RDMA1",
> > + "PSEUDO_OVL_MDP_RDMA2",
> > + "PSEUDO_OVL_MDP_RDMA3",
> > + "PSEUDO_OVL_MDP_RDMA4",
> > + "PSEUDO_OVL_MDP_RDMA5",
> > + "PSEUDO_OVL_MDP_RDMA6",
> > + "PSEUDO_OVL_MDP_RDMA7",
> > + "PSEUDO_OVL_MERGE0",
> > + "PSEUDO_OVL_MERGE1",
> > + "PSEUDO_OVL_MERGE2",
> > + "PSEUDO_OVL_MERGE3",
> > + "PSEUDO_OVL_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] =
> > {
> > + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> > + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct pseudo_ovl_comp_match
> > comp_matches[PSEUDO_OVL_ID_MAX] = {
> > + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0
> > },
> > + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1
> > },
> > + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2
> > },
> > + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3
> > },
> > + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4
> > },
> > + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5
> > },
> > + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6
> > },
> > + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7
> > },
> > + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> > + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> > + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> > + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> > +};
> > +
> > +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl
> > *pseudo_ovl,
> > + struct cmdq_pkt *handle)
> > +{
> > + struct mtk_pseudo_ovl_comp *rdma = NULL;
> > + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> > + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7;
> > i++) {
> > + rdma = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> > + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma-
> > >cmdq_base, fifo);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp
> > *comp,
> > + struct
> > pseudo_ovl_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_5);
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > +}
> > +
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct pseudo_ovl_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx];
> > + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx + 1];
> > + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE
> > + idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > +
> > + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.encode_type = RDMA_ENCODE_NONE;
> > + rdma_config.block_size = RDMA_BLOCK_NONE;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> > +}
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev)
> > +{
> > +}
> > +
> > +void mtk_pseudo_ovl_stop(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> > + rdma_l = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> > + rdma_r = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> > + merge = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int pseudo_ovl_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_pseudo_ovl_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_pseudo_ovl_comp *comp,
> > + enum mtk_pseudo_ovl_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < PSEUDO_OVL_MERGE_BASE)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > pseudo_ovl_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> > + .probe = mtk_disp_pseudo_ovl_comp_probe,
> > + .remove = mtk_disp_pseudo_ovl_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> > +
> > +static int pseudo_ovl_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_pseudo_ovl_comp_type type;
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> > + id = pseudo_ovl_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >pseudo_ovl_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data
> > = {
> > + .layer_nr = 4,
> > + .fifo.read_request_type = 7,
> > + .fifo.command_div = 1,
> > + .fifo.ext_preutra_en = 1,
> > + .fifo.ultra_en = 0,
> > + .fifo.pre_ultra_en = 1,
> > + .fifo.ext_ultra_en = 1,
> > + .fifo.extrd_arb_max_0 = 3,
> > + .fifo.buf_resv_size_0 = 0,
> > + .fifo.issue_req_th_0 = 0,
> > + .fifo.ultra_h_con_0 = 156,
> > + .fifo.ultra_l_con_0 = 104,
> > +};
>
> Now only support one SoC, so remove driver data and change these to
> definition instead of variable.
>
OK, I will remove it.
> > +
> > +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = &mt8195_pseudo_ovl_driver_data},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> > +
> > +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + priv->data = of_id->data;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = pseudo_ovl_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "pseudo_ovl comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE;
> > i++)
> > + pm_runtime_disable(pseudo_ovl-
> > >pseudo_ovl_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> > + .probe = mtk_disp_pseudo_ovl_probe,
> > + .remove = mtk_disp_pseudo_ovl_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > new file mode 100644
> > index 000000000000..b3fe1e1702b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> > +#define __MTK_DISP_PSEUDO_OVL_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev);
> > +void mtk_pseudo_ovl_stop(struct device *dev);
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..81d3cc4872eb
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,456 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_mdp_reg_rdma.h"
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define RDMA_INPUT_SWAP BIT(14)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define IRQ_INT_EN_ALL \
> > + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> > + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> > + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> > +
> > +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 2 * width;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 3 * width;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + case DRM_FORMAT_ARGB2101010:
> > + case DRM_FORMAT_ABGR2101010:
> > + case DRM_FORMAT_RGBA1010102:
> > + case DRM_FORMAT_BGRA1010102:
> > + return 4 * width;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 2 * width;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 4 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_block_h(unsigned int mode)
> > +{
> > + switch (mode) {
> > + default:
> > + return 0;
> > + case RDMA_BLOCK_8x8:
> > + case RDMA_BLOCK_16x8:
> > + case RDMA_BLOCK_32x8:
> > + return 8;
> > + case RDMA_BLOCK_8x16:
> > + case RDMA_BLOCK_16x16:
> > + case RDMA_BLOCK_32x16:
> > + return 16;
> > + case RDMA_BLOCK_8x32:
> > + case RDMA_BLOCK_16x32:
> > + case RDMA_BLOCK_32x32:
> > + return 32;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 16;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 24;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return 32;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 16;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 8;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 16;
> > + }
> > +}
> > +
> > +static bool with_alpha(uint32_t format)
> > +{
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(format);
> > +
> > + return fmt_info->has_alpha;
> > +}
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int inten = IRQ_INT_EN_ALL;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
>
> Why do you enable rdma interrupt?
>
I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > +}
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 0), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_STATUS,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > +}
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo *fifo)
>
> Why do you pass fifo config from ovl to rdma?
> I think just rdma know how to set these fifo parameter.
>
I will move fifo setting inside the rdma driver.
> > +{
> > + int reg;
> > + int reg_val;
> > + int reg_mask;
> > +
> > + reg = MDP_RDMA_GMCIF_CON;
> > + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo-
> > >read_request_type) |
> > + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> > + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo-
> > >ext_preutra_en) |
> > + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> > + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> > + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo-
> > >ext_ultra_en);
> > + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> > + REG_FLD_MASK(FLD_COMMAND_DIV) |
> > + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> > + REG_FLD_MASK(FLD_ULTRA_EN) |
> > + REG_FLD_MASK(PRE_ULTRA_EN) |
> > + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMA_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo-
> > >extrd_arb_max_0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo-
> > >buf_resv_size_0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo-
> > >issue_req_th_0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo-
> > >ultra_h_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_L_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo-
> > >ultra_l_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +}
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt,
> > cfg->source_width);
> > + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg-
> > >source_width);
>
> This is got from mtk_plane_atomic_update().
>
OK,I will modify it.
> > + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg-
> > >fmt);
> > + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg-
> > >fmt);
> > + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> > + unsigned int block_h = rdma_get_block_h(cfg->block_size);
>
> block_h = 0;
OK, I will modify it.
>
> > + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
>
> drm_format_info().
OK, I will modify it.
>
> > + unsigned int y_start_line = 0;
> > + unsigned int offset_y = 0;
> > + unsigned int offset_u = 0;
> > + unsigned int offset_v = 0;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> > + cmdq_base, base, MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > cmdq_base,
> > + base, MDP_RDMA_SRC_CON,
> > REG_FLD_MASK(FLD_SWAP) |
> > + REG_FLD_MASK(FLD_SRC_FORMAT) |
> > + REG_FLD_MASK(FLD_BIT_NUMBER));
> > +
> > + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_0,
> > REG_FLD_MASK(FLD_SRC_BASE_0));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_1,
> > REG_FLD_MASK(FLD_SRC_BASE_1));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_2,
> > REG_FLD_MASK(FLD_SRC_BASE_2));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_MF_BKGD_WB));
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> > + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_SF_BKGD_WB));
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
>
OK, I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_MF_BKGD_WP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_BKGD_HP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_OUTPUT_10B));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_SIMPLE_MODE));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg-
> > >csc_enable),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_TRANS_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> > +
> > + if (cfg->block_size == RDMA_BLOCK_NONE) {
> > + y_start_line = cfg->y_top;
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) +
> > y_start_line * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + } else {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> > + (cfg->y_top) * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + }
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_WP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_WP))
> > ;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_HP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_HP))
> > ;
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0,
> > offset_y),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1,
> > offset_u),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2,
> > offset_v),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg-
> > >width),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg-
> > >height),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W,
> > cfg->width),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H,
> > cfg->height),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> > +}
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..c16bfb716610
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,109 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +enum rdma_profile {
> > + RDMA_CSC_RGB_TO_JPEG = 0,
> > + RDMA_CSC_RGB_TO_FULL709 = 1,
> > + RDMA_CSC_RGB_TO_BT601 = 2,
> > + RDMA_CSC_RGB_TO_BT709 = 3,
> > + RDMA_CSC_JPEG_TO_RGB = 4,
> > + RDMA_CSC_FULL709_TO_RGB = 5,
> > + RDMA_CSC_BT601_TO_RGB = 6,
> > + RDMA_CSC_BT709_TO_RGB = 7,
> > + RDMA_CSC_JPEG_TO_BT601 = 8,
> > + RDMA_CSC_JPEG_TO_BT709 = 9,
> > + RDMA_CSC_BT601_TO_JPEG = 10,
> > + RDMA_CSC_BT709_TO_BT601 = 11,
> > + RDMA_CSC_BT601_TO_BT709 = 12
> > +};
> > +
> > +enum rdma_encode {
> > + RDMA_ENCODE_NONE = 0,
> > + RDMA_ENCODE_AFBC = 1,
> > + RDMA_ENCODE_HYFBC = 2,
> > + RDMA_ENCODE_UFO_DCP = 3
> > +};
> > +
> > +enum rdma_block {
> > + RDMA_BLOCK_NONE = 0,
> > + RDMA_BLOCK_8x8 = 1,
> > + RDMA_BLOCK_8x16 = 2,
> > + RDMA_BLOCK_8x32 = 3,
> > + RDMA_BLOCK_16x8 = 4,
> > + RDMA_BLOCK_16x16 = 5,
> > + RDMA_BLOCK_16x32 = 6,
> > + RDMA_BLOCK_32x8 = 7,
> > + RDMA_BLOCK_32x16 = 8,
> > + RDMA_BLOCK_32x32 = 9
> > +};
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + enum rdma_encode encode_type;
> > + enum rdma_block block_size;
> > + enum rdma_profile profile;
> > + unsigned int source_width;
> > + unsigned int addr0;
> > + unsigned int addr1;
> > + unsigned int addr2;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + bool csc_enable;
> > + int fmt;
> > +};
> > +
> > +struct mtk_mdp_rdma_fifo {
> > + int read_request_type;
> > + int command_div;
> > + int ext_preutra_en;
> > + int ultra_en;
> > + int pre_ultra_en;
> > + int ext_ultra_en;
> > + int extrd_arb_max_0;
> > + int buf_resv_size_0;
> > + int issue_req_th_0;
> > + int ultra_h_con_0;
> > + int ultra_l_con_0;
> > +};
>
> Move rdma internal definition in .c file.
>
OK, I will move it to internal .c file.
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo
> > *fifo);
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base,
> > + struct mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
>
> Move these prototype to mtk_disp_drv.h
>
OK.
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > new file mode 100644
> > index 000000000000..08abd9f39bd8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > @@ -0,0 +1,160 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MDP_RDMA_REGS_H__
> > +#define __MDP_RDMA_REGS_H__
> > +
> > +#define REG_FLD(width, shift) \
> > + ((unsigned int)((((width) & 0xff) << 16) | ((shift) &
> > 0xff)))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > + << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
> > +#define
> > MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_RESET 0x008
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_ENABLE 0x010
> > +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> > +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> > +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_STATUS 0x018
> > +
> > +#define
> > MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> > +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> > +
> > +#define
> > MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> > +#define PRE_ULTRA_EN REG_FLD(2, 16)
> > +#define FLD_ULTRA_EN REG_FLD(2, 12)
> > +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> > +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> > +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> > +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> > +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> > +#define FLD_SWAP REG_FLD(1, 14)
> > +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> > +
> > +#define
> > MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN REG_FLD(1, 22)
> > +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> > +#define FLD_UFBDC_EN REG_FLD(1, 12)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> > +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H REG_FLD(15, 16)
> > +#define FLD_MF_SRC_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> > +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_OFFSET_1 0x080
> > +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> > +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> > +
> > +#define
> > MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> > +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> > +#define FLD_BKGD_HP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_TARGET_LINE 0x0a0
> > +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> > +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_1 0x120
> > +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_2 0x128
> > +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_WP 0x148
> > +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_HP 0x150
> > +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> > +#define FLD_TRANS_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_DMA_CON_0 0x240
> > +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> > +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_0 0x248
> > +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_UTRA_L_CON_0 0x250
> > +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_1 0x258
> > +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> > +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_2 0x270
> > +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_2 0x278
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_3 0x288
> > +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_3 0x290
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_1 0xf08
> > +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_2 0xf10
> > +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> > +
> > +#endif /* __MDP_RDMA_REGS_H__ */
>
> Only one file need these, so move register definiton in .c file.
>
OK.
> Regards,
> Chun-Kuang.
>
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-30 3:28 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:28 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, srv_heupstream, David Airlie, jason-jh . lin, singo.chang,
linux-kernel, DRI Development, Yongqiang Niu, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Chun-Kuang,
Thanks for your review.
On Sun, 2021-07-25 at 09:57 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add pseudo ovl module files:
>
> My English is not good. The word 'pseudo' seems like 'looks like but
> indeed not the same'.
> I think the 'real' ovl also has rdma and mixer inside it, so I prefer
> to treat these two ovl as different kind of ovl, not a real one and a
> pseudo one.
> Does I misunderstanding the word 'pseudo'?
>
I was thinking of encapsulating several engines in this component. The
prefix "pseudo" was meant to distinguish with the origin ovl. I will
change pseudo_ovl to ovl_adaptor.
> > Pseudo ovl is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 4 +-
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 593
> > ++++++++++++++++++
> > .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.h | 23 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 ++++
> > drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
>
> Seperate mtk_dmp_rdma driver to an independent patch.
>
OK, I will separate it.
> > 6 files changed, 1344 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..31613564f499 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_disp_pseudo_ovl.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > new file mode 100644
> > index 000000000000..0446fa99dd0a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> > @@ -0,0 +1,593 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_mdp_rdma.h"
> > +#include "mtk_disp_pseudo_ovl.h"
> > +
> > +#define DISP_MERGE_ENABLE 0x0
> > + #define MERGE_ENABLE BIT(0)
> > +#define DISP_MERGE_CFG_0 0x10
> > +#define DISP_MERGE_CFG_1 0x14
> > +#define DISP_MERGE_CFG_4 0x20
> > +#define DISP_MERGE_CFG_5 0x24
> > +#define DISP_MERGE_CFG_10 0x38
> > + #define CFG_10_NO_SWAP 0
> > +#define DISP_MERGE_CFG_12 0x40
> > + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> > + #define CFG12_11_10_1PI_2PO_MERGE 18
> > +#define DISP_MERGE_CFG_24 0x70
> > +#define DISP_MERGE_CFG_25 0x74
> > +#define DISP_MERGE_CFG_26 0x78
> > +#define DISP_MERGE_CFG_27 0x7c
> > +#define DISP_MERGE_MUTE_0 0xf00
> > +
> > +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
>
> Which hardware has this limitation? I would like this naming to
> reflect which hardware has this limitation.
>
RDMA has the limitation, I will modify its naming.
> > +
> > +enum mtk_pseudo_ovl_comp_type {
> > + PSEUDO_OVL_TYPE_RDMA = 0,
> > + PSEUDO_OVL_TYPE_MERGE,
> > + PSEUDO_OVL_TYPE_NUM,
> > +};
> > +
> > +enum mtk_pseudo_ovl_comp_id {
> > + PSEUDO_OVL_RDMA_BASE = 0,
> > + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
>
> I think you could directly use PSEUDO_OVL_MDP_RDMA0 and remove
> PSEUDO_OVL_RDMA_BASE.
>
OK, I will remove it.
> > + PSEUDO_OVL_MDP_RDMA1,
> > + PSEUDO_OVL_MDP_RDMA2,
> > + PSEUDO_OVL_MDP_RDMA3,
> > + PSEUDO_OVL_MDP_RDMA4,
> > + PSEUDO_OVL_MDP_RDMA5,
> > + PSEUDO_OVL_MDP_RDMA6,
> > + PSEUDO_OVL_MDP_RDMA7,
> > + PSEUDO_OVL_MERGE_BASE,
> > + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
>
> Ditto.
OK, I will remove it.
>
> > + PSEUDO_OVL_MERGE1,
> > + PSEUDO_OVL_MERGE2,
> > + PSEUDO_OVL_MERGE3,
> > + PSEUDO_OVL_ID_MAX
> > +};
> > +
> > +struct pseudo_ovl_data {
> > + unsigned int layer_nr;
> > + struct mtk_mdp_rdma_fifo fifo;
> > +};
> > +
> > +struct pseudo_ovl_comp_match {
> > + enum mtk_pseudo_ovl_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct pseudo_ovl_merge_config {
> > + unsigned int fmt;
> > + unsigned int merge_mode;
> > + unsigned int in_w[2];
> > + unsigned int out_w[2];
> > + unsigned int in_h;
> > +};
> > +
> > +struct mtk_pseudo_ovl_comp {
> > + struct device *dev;
> > + struct clk *clks[2];
> > + struct cmdq_client_reg cmdq_base;
> > + void __iomem *regs;
> > +};
> > +
> > +struct mtk_disp_pseudo_ovl {
> > + struct mtk_pseudo_ovl_comp
> > pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> > + const struct pseudo_ovl_data *data;
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const pseudo_ovl_comp_str[] = {
> > + "PSEUDO_OVL_MDP_RDMA0",
> > + "PSEUDO_OVL_MDP_RDMA1",
> > + "PSEUDO_OVL_MDP_RDMA2",
> > + "PSEUDO_OVL_MDP_RDMA3",
> > + "PSEUDO_OVL_MDP_RDMA4",
> > + "PSEUDO_OVL_MDP_RDMA5",
> > + "PSEUDO_OVL_MDP_RDMA6",
> > + "PSEUDO_OVL_MDP_RDMA7",
> > + "PSEUDO_OVL_MERGE0",
> > + "PSEUDO_OVL_MERGE1",
> > + "PSEUDO_OVL_MERGE2",
> > + "PSEUDO_OVL_MERGE3",
> > + "PSEUDO_OVL_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] =
> > {
> > + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> > + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> > +};
> > +
> > +static const struct pseudo_ovl_comp_match
> > comp_matches[PSEUDO_OVL_ID_MAX] = {
> > + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0
> > },
> > + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1
> > },
> > + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2
> > },
> > + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3
> > },
> > + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4
> > },
> > + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5
> > },
> > + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6
> > },
> > + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7
> > },
> > + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> > + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> > + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> > + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> > +};
> > +
> > +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl
> > *pseudo_ovl,
> > + struct cmdq_pkt *handle)
> > +{
> > + struct mtk_pseudo_ovl_comp *rdma = NULL;
> > + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> > + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7;
> > i++) {
> > + rdma = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> > + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma-
> > >cmdq_base, fifo);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp
> > *comp,
> > + struct
> > pseudo_ovl_merge_config *merge_cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + switch (merge_cfg->merge_mode) {
> > + case 6:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + break;
> > + case 18:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_24);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_25);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_27);
> > + break;
> > + default:
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_0);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->in_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[0]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_4);
> > + mtk_ddp_write(cmdq_pkt, (merge_cfg->in_h << 16 |
> > merge_cfg->out_w[1]),
> > + &comp->cmdq_base, comp->regs,
> > DISP_MERGE_CFG_5);
> > + break;
> > + }
> > +
> > + mtk_ddp_write(cmdq_pkt, merge_cfg->merge_mode, &comp-
> > >cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_12);
> > + mtk_ddp_write(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> > + comp->regs, DISP_MERGE_CFG_10);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > +}
> > +
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct pseudo_ovl_merge_config merge_cfg = {0};
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx];
> > + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE
> > + 2 * idx + 1];
> > + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE
> > + idx];
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge-
> > >cmdq_base, merge->regs,
> > + DISP_MERGE_ENABLE,
> > MERGE_ENABLE);
> > + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + return;
> > + }
> > +
> > + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + merge_cfg.out_w[0] = pending->width;
> > + merge_cfg.in_h = pending->height;
> > + merge_cfg.fmt = pending->format;
> > + if (use_dual_pipe) {
> > + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> > + merge_cfg.in_w[0] = (pending->width / 2) +
> > ((pending->width / 2) % 2);
> > + merge_cfg.in_w[1] = (pending->width / 2) -
> > ((pending->width / 2) % 2);
> > + } else {
> > + merge_cfg.merge_mode =
> > CFG12_10_10_1PI_2PO_BUF_MODE;
> > + merge_cfg.in_w[0] = pending->width;
> > + }
> > +
> > + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> > +
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(pseudo_ovl->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.source_width = pending->pitch / fmt_info-
> > >cpp[0];
> > + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> > + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> > + rdma_config.encode_type = RDMA_ENCODE_NONE;
> > + rdma_config.block_size = RDMA_BLOCK_NONE;
> > + rdma_config.width = merge_cfg.in_w[0];
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt,
> > &rdma_l->cmdq_base);
> > +
> > + rdma_config.x_left = merge_cfg.in_w[0];
> > + rdma_config.width = merge_cfg.in_w[1];
> > + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt,
> > &rdma_r->cmdq_base);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_ENABLE, MERGE_ENABLE);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge-
> > >regs,
> > + DISP_MERGE_MUTE_0, 0x1);
> > +
> > + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l-
> > >cmdq_base);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r-
> > >cmdq_base);
> > +}
> > +
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> > +
> > + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> > +}
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev)
> > +{
> > +}
> > +
> > +void mtk_pseudo_ovl_stop(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *rdma_l;
> > + struct mtk_pseudo_ovl_comp *rdma_r;
> > + struct mtk_pseudo_ovl_comp *merge;
> > + unsigned int reg;
> > + u32 i;
> > +
> > + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> > + rdma_l = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> > + rdma_r = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> > + merge = &pseudo_ovl-
> > >pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l-
> > >cmdq_base);
> > + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r-
> > >cmdq_base);
> > +
> > + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> > + reg = reg & ~MERGE_ENABLE;
> > + writel_relaxed(reg, merge->regs +
> > DISP_MERGE_ENABLE);
> > +
> > + device_reset_optional(merge->dev);
> > + }
> > +}
> > +
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + /* Need to power on for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_get_sync(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power on, err
> > %d-%s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > +
> > + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > +
> > + ret = clk_prepare_enable(comp->clks[j]);
> > + if (ret)
> > + dev_err(dev,
> > + "Failed to enable clock %d,
> > err %d-%s\n",
> > + i, ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(dev);
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int ret;
> > + int i;
> > + int j;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++)
> > {
> > + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> > + if (!comp->dev)
> > + continue;
> > +
> > + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> > + if (IS_ERR(comp->clks[j]))
> > + break;
> > + clk_disable_unprepare(comp->clks[j]);
> > + }
> > +
> > + /* Need to power off for private rdma devices */
> > + if (i < PSEUDO_OVL_MERGE_BASE) {
> > + ret = pm_runtime_put(comp->dev);
> > + if (ret < 0)
> > + dev_err(dev,
> > + "Failed to power off, err-
> > %s\n",
> > + ret,
> > pseudo_ovl_comp_str[i]);
> > + }
> > + }
> > +}
> > +
> > +static int pseudo_ovl_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_pseudo_ovl_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static int private_comp_init(struct device *dev, struct
> > device_node *node,
> > + struct mtk_pseudo_ovl_comp *comp,
> > + enum mtk_pseudo_ovl_comp_id id)
> > +{
> > + struct platform_device *comp_pdev;
> > + int ret;
> > + int i;
> > +
> > + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> > + dev_err(dev, "Invalid component id %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + comp->dev = &comp_pdev->dev;
> > + comp->regs = of_iomap(node, 0);
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> > + comp->clks[i] = of_clk_get(node, i);
> > + if (IS_ERR(comp->clks[i]))
> > + break;
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base,
> > 0);
> > + if (ret)
> > + dev_info(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + if (id < PSEUDO_OVL_MERGE_BASE)
> > + pm_runtime_enable(comp->dev);
> > +
> > + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs,
> > pseudo_ovl_comp_str[id]);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device
> > *pdev)
> > +{
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-vdo1-merge",
> > + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> > + },
> > + {},
> > +};
> > +
> > +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> > + .probe = mtk_disp_pseudo_ovl_comp_probe,
> > + .remove = mtk_disp_pseudo_ovl_comp_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl-comp",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> > +
> > +static int pseudo_ovl_comp_init(struct device *dev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + int i, ret;
> > +
> > + parent = dev->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_pseudo_ovl_comp_type type;
> > + struct mtk_pseudo_ovl_comp *comp;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> > + id = pseudo_ovl_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + ret = private_comp_init(dev, node, &priv-
> > >pseudo_ovl_comp[id], id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data
> > = {
> > + .layer_nr = 4,
> > + .fifo.read_request_type = 7,
> > + .fifo.command_div = 1,
> > + .fifo.ext_preutra_en = 1,
> > + .fifo.ultra_en = 0,
> > + .fifo.pre_ultra_en = 1,
> > + .fifo.ext_ultra_en = 1,
> > + .fifo.extrd_arb_max_0 = 3,
> > + .fifo.buf_resv_size_0 = 0,
> > + .fifo.issue_req_th_0 = 0,
> > + .fifo.ultra_h_con_0 = 156,
> > + .fifo.ultra_l_con_0 = 104,
> > +};
>
> Now only support one SoC, so remove driver data and change these to
> definition instead of variable.
>
OK, I will remove it.
> > +
> > +static const struct of_device_id pseudo_ovl_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = &mt8195_pseudo_ovl_driver_data},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> > +
> > +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *priv;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *phandle = dev->parent->of_node;
> > + const struct of_device_id *of_id;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + of_id = of_match_node(pseudo_ovl_driver_dt_match, phandle);
> > + if (!of_id)
> > + return -ENODEV;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + priv->data = of_id->data;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = pseudo_ovl_comp_init(dev);
> > + if (ret) {
> > + dev_notice(dev, "pseudo_ovl comp init fail\n");
> > + return ret;
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_pseudo_ovl_remove(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_pseudo_ovl *pseudo_ovl =
> > dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE;
> > i++)
> > + pm_runtime_disable(pseudo_ovl-
> > >pseudo_ovl_comp[i].dev);
> > +
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> > + .probe = mtk_disp_pseudo_ovl_probe,
> > + .remove = mtk_disp_pseudo_ovl_remove,
> > + .driver = {
> > + .name = "mediatek-disp-pseudo-ovl",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > +module_platform_driver(mtk_disp_pseudo_ovl_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > new file mode 100644
> > index 000000000000..b3fe1e1702b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_PSEUDO_OVL_H__
> > +#define __MTK_DISP_PSEUDO_OVL_H__
> > +
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_pseudo_ovl_start(struct device *dev);
> > +void mtk_pseudo_ovl_stop(struct device *dev);
> > +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> > +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> > +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h,
> > + unsigned int vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +
> > +#endif
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..81d3cc4872eb
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,456 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_mdp_reg_rdma.h"
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define RDMA_INPUT_SWAP BIT(14)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define IRQ_INT_EN_ALL \
> > + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> > + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> > + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> > +
> > +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 2 * width;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 3 * width;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + case DRM_FORMAT_ARGB2101010:
> > + case DRM_FORMAT_ABGR2101010:
> > + case DRM_FORMAT_RGBA1010102:
> > + case DRM_FORMAT_BGRA1010102:
> > + return 4 * width;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 2 * width;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned
> > int width)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 4 * width;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_block_h(unsigned int mode)
> > +{
> > + switch (mode) {
> > + default:
> > + return 0;
> > + case RDMA_BLOCK_8x8:
> > + case RDMA_BLOCK_16x8:
> > + case RDMA_BLOCK_32x8:
> > + return 8;
> > + case RDMA_BLOCK_8x16:
> > + case RDMA_BLOCK_16x16:
> > + case RDMA_BLOCK_32x16:
> > + return 16;
> > + case RDMA_BLOCK_8x32:
> > + case RDMA_BLOCK_16x32:
> > + case RDMA_BLOCK_32x32:
> > + return 32;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 1;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + case DRM_FORMAT_BGR565:
> > + return 16;
> > + case DRM_FORMAT_RGB888:
> > + case DRM_FORMAT_BGR888:
> > + return 24;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return 32;
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YUYV:
> > + return 16;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 8;
> > + }
> > +}
> > +
> > +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + return 0;
> > + case DRM_FORMAT_NV12:
> > + case DRM_FORMAT_NV21:
> > + return 16;
> > + }
> > +}
> > +
> > +static bool with_alpha(uint32_t format)
> > +{
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(format);
> > +
> > + return fmt_info->has_alpha;
> > +}
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP
> > |
> > + RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int inten = IRQ_INT_EN_ALL;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
>
> Why do you enable rdma interrupt?
>
I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > +}
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE,
> > 0), cmdq_base,
> > + base, MDP_RDMA_EN,
> > REG_FLD_MASK(FLD_ROT_ENABLE));
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_ENABLE,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > + MDP_RDMA_INTERRUPT_STATUS,
> > IRQ_INT_EN_ALL);
> > + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> > MDP_RDMA_RESET, ~0);
> > +}
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt
> > *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo *fifo)
>
> Why do you pass fifo config from ovl to rdma?
> I think just rdma know how to set these fifo parameter.
>
I will move fifo setting inside the rdma driver.
> > +{
> > + int reg;
> > + int reg_val;
> > + int reg_mask;
> > +
> > + reg = MDP_RDMA_GMCIF_CON;
> > + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo-
> > >read_request_type) |
> > + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> > + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo-
> > >ext_preutra_en) |
> > + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> > + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> > + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo-
> > >ext_ultra_en);
> > + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> > + REG_FLD_MASK(FLD_COMMAND_DIV) |
> > + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> > + REG_FLD_MASK(FLD_ULTRA_EN) |
> > + REG_FLD_MASK(PRE_ULTRA_EN) |
> > + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMA_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo-
> > >extrd_arb_max_0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo-
> > >buf_resv_size_0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo-
> > >issue_req_th_0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo-
> > >ultra_h_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_L_CON_0;
> > + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo-
> > >ultra_l_con_0);
> > + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_DMABUF_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> > + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> > + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> > + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> > + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_UTRA_H_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +
> > + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> > + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> > + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> > + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg,
> > reg_mask);
> > +}
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base)
> > +{
> > + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt,
> > cfg->source_width);
> > + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg-
> > >source_width);
>
> This is got from mtk_plane_atomic_update().
>
OK,I will modify it.
> > + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg-
> > >fmt);
> > + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg-
> > >fmt);
> > + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
> > + unsigned int block_h = rdma_get_block_h(cfg->block_size);
>
> block_h = 0;
OK, I will modify it.
>
> > + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
>
> drm_format_info().
OK, I will modify it.
>
> > + unsigned int y_start_line = 0;
> > + unsigned int offset_y = 0;
> > + unsigned int offset_u = 0;
> > + unsigned int offset_v = 0;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> > + cmdq_base, base, MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > cmdq_base,
> > + base, MDP_RDMA_SRC_CON,
> > REG_FLD_MASK(FLD_SWAP) |
> > + REG_FLD_MASK(FLD_SRC_FORMAT) |
> > + REG_FLD_MASK(FLD_BIT_NUMBER));
> > +
> > + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_CON,
> > + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_0,
> > REG_FLD_MASK(FLD_SRC_BASE_0));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_1,
> > REG_FLD_MASK(FLD_SRC_BASE_1));
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> > + MDP_RDMA_SRC_BASE_2,
> > REG_FLD_MASK(FLD_SRC_BASE_2));
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_MF_BKGD_WB));
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> > + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> > + REG_FLD_MASK(FLD_SF_BKGD_WB));
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
>
OK, I will remove it.
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_MF_BKGD_WP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> > + cmdq_base, base,
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> > + REG_FLD_MASK(FLD_BKGD_HP));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> > + cmdq_base, base,
> > MDP_RDMA_COMP_CON,
> > + REG_FLD_MASK(FLD_AFBC_YUV_TRANSF
> > ORM));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_UFBDC_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> > + base, MDP_RDMA_COMP_CON,
> > REG_FLD_MASK(FLD_AFBC_EN));
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_OUTPUT_10B));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE,
> > 1), cmdq_base,
> > + base, MDP_RDMA_CON,
> > REG_FLD_MASK(FLD_SIMPLE_MODE));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg-
> > >csc_enable),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_TRANS_EN));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> > + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> > + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> > +
> > + if (cfg->block_size == RDMA_BLOCK_NONE) {
> > + y_start_line = cfg->y_top;
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) +
> > y_start_line * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv
> > >> 3) +
> > + (y_start_line >> v_shift_uv) *
> > src_pitch_uv;
> > + } else {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> > + (cfg->y_top) * src_pitch_y;
> > + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h
> > >> v_shift_uv) *
> > + bpp_uv >> 3) + (cfg->y_top) *
> > src_pitch_uv;
> > + }
> > +
> > + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
>
> Never be here, so remove.
OK, I will remove it.
>
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_WP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_WP))
> > ;
> > +
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> > + cmdq_base, base,
> > MDP_RDMA_SRC_OFFSET_HP,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_HP))
> > ;
> > + }
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0,
> > offset_y),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_0));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1,
> > offset_u),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2,
> > offset_v),
> > + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> > + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg-
> > >width),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg-
> > >height),
> > + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> > + REG_FLD_MASK(FLD_MF_SRC_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W,
> > cfg->width),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_W));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H,
> > cfg->height),
> > + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> > + REG_FLD_MASK(FLD_MF_CLIP_H));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> > + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1,
> > 0),
> > + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> > + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> > + mtk_ddp_write_mask(cmdq_pkt,
> > REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> > + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> > + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> > +}
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..c16bfb716610
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,109 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +enum rdma_profile {
> > + RDMA_CSC_RGB_TO_JPEG = 0,
> > + RDMA_CSC_RGB_TO_FULL709 = 1,
> > + RDMA_CSC_RGB_TO_BT601 = 2,
> > + RDMA_CSC_RGB_TO_BT709 = 3,
> > + RDMA_CSC_JPEG_TO_RGB = 4,
> > + RDMA_CSC_FULL709_TO_RGB = 5,
> > + RDMA_CSC_BT601_TO_RGB = 6,
> > + RDMA_CSC_BT709_TO_RGB = 7,
> > + RDMA_CSC_JPEG_TO_BT601 = 8,
> > + RDMA_CSC_JPEG_TO_BT709 = 9,
> > + RDMA_CSC_BT601_TO_JPEG = 10,
> > + RDMA_CSC_BT709_TO_BT601 = 11,
> > + RDMA_CSC_BT601_TO_BT709 = 12
> > +};
> > +
> > +enum rdma_encode {
> > + RDMA_ENCODE_NONE = 0,
> > + RDMA_ENCODE_AFBC = 1,
> > + RDMA_ENCODE_HYFBC = 2,
> > + RDMA_ENCODE_UFO_DCP = 3
> > +};
> > +
> > +enum rdma_block {
> > + RDMA_BLOCK_NONE = 0,
> > + RDMA_BLOCK_8x8 = 1,
> > + RDMA_BLOCK_8x16 = 2,
> > + RDMA_BLOCK_8x32 = 3,
> > + RDMA_BLOCK_16x8 = 4,
> > + RDMA_BLOCK_16x16 = 5,
> > + RDMA_BLOCK_16x32 = 6,
> > + RDMA_BLOCK_32x8 = 7,
> > + RDMA_BLOCK_32x16 = 8,
> > + RDMA_BLOCK_32x32 = 9
> > +};
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + enum rdma_encode encode_type;
> > + enum rdma_block block_size;
> > + enum rdma_profile profile;
> > + unsigned int source_width;
> > + unsigned int addr0;
> > + unsigned int addr1;
> > + unsigned int addr2;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + bool csc_enable;
> > + int fmt;
> > +};
> > +
> > +struct mtk_mdp_rdma_fifo {
> > + int read_request_type;
> > + int command_div;
> > + int ext_preutra_en;
> > + int ultra_en;
> > + int pre_ultra_en;
> > + int ext_ultra_en;
> > + int extrd_arb_max_0;
> > + int buf_resv_size_0;
> > + int issue_req_th_0;
> > + int ultra_h_con_0;
> > + int ultra_l_con_0;
> > +};
>
> Move rdma internal definition in .c file.
>
OK, I will move it to internal .c file.
> > +
> > +void mtk_mdp_rdma_start(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_stop(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
> > +
> > +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base,
> > + const struct mtk_mdp_rdma_fifo
> > *fifo);
> > +
> > +void mtk_mdp_rdma_config(void __iomem *base,
> > + struct mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt,
> > + struct cmdq_client_reg *cmdq_base);
>
> Move these prototype to mtk_disp_drv.h
>
OK.
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > new file mode 100644
> > index 000000000000..08abd9f39bd8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> > @@ -0,0 +1,160 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MDP_RDMA_REGS_H__
> > +#define __MDP_RDMA_REGS_H__
> > +
> > +#define REG_FLD(width, shift) \
> > + ((unsigned int)((((width) & 0xff) << 16) | ((shift) &
> > 0xff)))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > + << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
> > +#define
> > MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_RESET 0x008
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_ENABLE 0x010
> > +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> > +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> > +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_INTERRUPT_STATUS 0x018
> > +
> > +#define
> > MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> > +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> > +
> > +#define
> > MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> > +#define PRE_ULTRA_EN REG_FLD(2, 16)
> > +#define FLD_ULTRA_EN REG_FLD(2, 12)
> > +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> > +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> > +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> > +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> > +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> > +#define FLD_SWAP REG_FLD(1, 14)
> > +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> > +
> > +#define
> > MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN REG_FLD(1, 22)
> > +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> > +#define FLD_UFBDC_EN REG_FLD(1, 12)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> > +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H REG_FLD(15, 16)
> > +#define FLD_MF_SRC_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> > +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> > +
> > +#define
> > MDP_RDMA_MF_OFFSET_1 0x080
> > +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> > +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> > +
> > +#define
> > MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> > +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> > +#define FLD_BKGD_HP REG_FLD(23, 0)
> > +
> > +#define
> > MDP_RDMA_TARGET_LINE 0x0a0
> > +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> > +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_1 0x120
> > +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_2 0x128
> > +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_WP 0x148
> > +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_OFFSET_HP 0x150
> > +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> > +#define FLD_TRANS_EN REG_FLD(1, 16)
> > +
> > +#define
> > MDP_RDMA_DMA_CON_0 0x240
> > +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> > +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_0 0x248
> > +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_UTRA_L_CON_0 0x250
> > +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_1 0x258
> > +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> > +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_2 0x270
> > +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_2 0x278
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_DMABUF_CON_3 0x288
> > +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> > +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> > +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> > +
> > +#define
> > MDP_RDMA_UTRA_H_CON_3 0x290
> > +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> > +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_1 0xf08
> > +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> > +
> > +#define
> > MDP_RDMA_SRC_BASE_2 0xf10
> > +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> > +
> > +#endif /* __MDP_RDMA_REGS_H__ */
>
> Only one file need these, so move register definiton in .c file.
>
OK.
> Regards,
> Chun-Kuang.
>
> > +
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
2021-07-28 10:31 ` Enric Balletbo Serra
(?)
@ 2021-07-30 3:47 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:47 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
On Wed, 2021-07-28 at 12:31 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de
> jul.
> 2021 a les 8:01:
> >
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:46:
> > > >
> > > > Among other features the mmsys driver should implement a reset
> > > > controller to be able to reset different bits from their space.
> > > >
> > >
> > > I'm working on a series that does the same, it should be nice if
> > > we
> > > can coordinate [1]
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> > >
> > >
> >
> > OK, I will add this series to my reference base in the next patch
> > revision.
> >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > > +++++++++++++++++++++++++++++
> > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > 3 files changed, 79 insertions(+)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -154,6 +154,7 @@
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > > << 0)
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > > << 0)
> > > >
> > > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index d0f4a407f8f8..1ae04efeadab 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -4,10 +4,12 @@
> > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > */
> > > >
> > > > +#include <linux/delay.h>
> > > > #include <linux/device.h>
> > > > #include <linux/io.h>
> > > > #include <linux/of_device.h>
> > > > #include <linux/platform_device.h>
> > > > +#include <linux/reset-controller.h>
> > > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > > >
> > > > #include "mtk-mmsys.h"
> > > > @@ -15,6 +17,8 @@
> > > > #include "mt8183-mmsys.h"
> > > > #include "mt8195-mmsys.h"
> > > >
> > > > +#define MMSYS_SW_RESET_PER_REG 32
> > > > +
> > > > static const struct mtk_mmsys_driver_data
> > > > mt2701_mmsys_driver_data
> > > > = {
> > > > .clk_driver = "clk-mt2701-mm",
> > > > .routes = mmsys_default_routing_table,
> > > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > .config = mmsys_mt8195_config_table,
> > > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> > >
> > > That change is interesting and I think I should also take it into
> > > consideration with my series.
> > >
> > > > };
> > > >
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > struct cmdq_client_reg cmdq_base;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > >
> > > Seems that mmsys_sw_rst_b reg has different names for different
> > > SoCs?
> > > I mean I know that for MT8173 and MT8183 the register is called
> > > mmsys_sw0_rst_b but looks like for MT8195 the name is
> > > vdo1_sw0_rst_b?
> > > So maybe we should update this comment to be more generic.
> > >
> >
> > Yes, the name of MT8195 vdosys1 sw reset is called
> > VDOSYS1_SW0_RST_B
> > and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They
> > have
> > a different name. Maybe we can change the comment to "protects
> > mmsys sw
> > reset reg".
> >
> > > >
> > > > + struct reset_controller_dev rcdev;
> > > > };
> > > >
> > > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device
> > > > *dev,
> > > > enum mtk_mmsys_config_type config,
> > > > }
> > > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > > >
> > > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > > *rcdev, unsigned long id,
> > > > + bool assert)
> > > > +{
> > > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > > mtk_mmsys, rcdev);
> > > > + unsigned long flags;
> > > > + u32 reg;
> > > > + int i;
> > > > + u32 offset;
> > > > +
> > > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > > +
> > > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > > +
> > > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + if (assert)
> > > > + reg &= ~BIT(id);
> > > > + else
> > > > + reg |= BIT(id);
> > > > +
> > > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_deassert(struct
> > > > reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > > unsigned long id)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + usleep_range(1000, 1100);
> > > > +
> > >
> > > One question that I received in my series, and I couldn't answer
> > > because I don't have the datasheet, is if
> > > is this known to be enough for all IP cores that can be reset by
> > > this
> > > controller? Is this time specified in the datasheet?
> >
> > It only takes few cycles for the reset. The 1000us is enough for
> > the
> > reset to take effect.
> >
>
> Saying enough looks to me that 1000us is a random number, is there
> any
> specific real number in the datasheet?
>
> Note that I'm not against it, just want to make sure the number makes
> sense.
>
No real number is specified in the datasheet. I checked with the
hardware designer, and the reset takes four cycles of mm IP cores.
For example: If the mm IP cores run at 200MHz, it will take
20ns(4/200M) for the reset to take effect.
>
> > > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > > +}
> > > > +
> > > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > > + .assert = mtk_mmsys_reset_assert,
> > > > + .deassert = mtk_mmsys_reset_deassert,
> > > > + .reset = mtk_mmsys_reset,
> > > > +};
> > > > +
> > > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > > {
> > > > struct device *dev = &pdev->dev;
> > > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > > platform_device *pdev)
> > > > if (ret)
> > > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > > #endif
> > > > +
> > > > + spin_lock_init(&mmsys->lock);
> > > > +
> > > > + mmsys->rcdev.owner = THIS_MODULE;
> > > > + mmsys->rcdev.nr_resets = 64;
> > >
> > > Is the number of resets 64 for MT8195? I think is 32 for MT8173
> > > and
> > > MT8183. Can you confirm?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > The number of resets in MT8195 vdosys1 is 64 (43 resets are used,
> > 21
> > are not used).
> >
>
> Ok, thanks for the information.
>
> > > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > > + ret = devm_reset_controller_register(&pdev->dev,
> > > > &mmsys-
> > > > > rcdev);
> > > >
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "Couldn't register mmsys
> > > > reset
> > > > controller: %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > platform_set_drvdata(pdev, mmsys);
> > > >
> > > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > > > data->clk_driver,
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > > index 084b1f5f3c88..cc57c3895c51 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > > const unsigned int num_routes;
> > > > const struct mtk_mmsys_config *config;
> > > > const unsigned int num_configs;
> > > > + u32 sw_reset_start;
> > > > };
> > > >
> > > > /*
> > > > --
> > > > 2.18.0
> > > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-30 3:47 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:47 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi Enric,
On Wed, 2021-07-28 at 12:31 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de
> jul.
> 2021 a les 8:01:
> >
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:46:
> > > >
> > > > Among other features the mmsys driver should implement a reset
> > > > controller to be able to reset different bits from their space.
> > > >
> > >
> > > I'm working on a series that does the same, it should be nice if
> > > we
> > > can coordinate [1]
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> > >
> > >
> >
> > OK, I will add this series to my reference base in the next patch
> > revision.
> >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > > +++++++++++++++++++++++++++++
> > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > 3 files changed, 79 insertions(+)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -154,6 +154,7 @@
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > > << 0)
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > > << 0)
> > > >
> > > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index d0f4a407f8f8..1ae04efeadab 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -4,10 +4,12 @@
> > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > */
> > > >
> > > > +#include <linux/delay.h>
> > > > #include <linux/device.h>
> > > > #include <linux/io.h>
> > > > #include <linux/of_device.h>
> > > > #include <linux/platform_device.h>
> > > > +#include <linux/reset-controller.h>
> > > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > > >
> > > > #include "mtk-mmsys.h"
> > > > @@ -15,6 +17,8 @@
> > > > #include "mt8183-mmsys.h"
> > > > #include "mt8195-mmsys.h"
> > > >
> > > > +#define MMSYS_SW_RESET_PER_REG 32
> > > > +
> > > > static const struct mtk_mmsys_driver_data
> > > > mt2701_mmsys_driver_data
> > > > = {
> > > > .clk_driver = "clk-mt2701-mm",
> > > > .routes = mmsys_default_routing_table,
> > > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > .config = mmsys_mt8195_config_table,
> > > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> > >
> > > That change is interesting and I think I should also take it into
> > > consideration with my series.
> > >
> > > > };
> > > >
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > struct cmdq_client_reg cmdq_base;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > >
> > > Seems that mmsys_sw_rst_b reg has different names for different
> > > SoCs?
> > > I mean I know that for MT8173 and MT8183 the register is called
> > > mmsys_sw0_rst_b but looks like for MT8195 the name is
> > > vdo1_sw0_rst_b?
> > > So maybe we should update this comment to be more generic.
> > >
> >
> > Yes, the name of MT8195 vdosys1 sw reset is called
> > VDOSYS1_SW0_RST_B
> > and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They
> > have
> > a different name. Maybe we can change the comment to "protects
> > mmsys sw
> > reset reg".
> >
> > > >
> > > > + struct reset_controller_dev rcdev;
> > > > };
> > > >
> > > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device
> > > > *dev,
> > > > enum mtk_mmsys_config_type config,
> > > > }
> > > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > > >
> > > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > > *rcdev, unsigned long id,
> > > > + bool assert)
> > > > +{
> > > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > > mtk_mmsys, rcdev);
> > > > + unsigned long flags;
> > > > + u32 reg;
> > > > + int i;
> > > > + u32 offset;
> > > > +
> > > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > > +
> > > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > > +
> > > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + if (assert)
> > > > + reg &= ~BIT(id);
> > > > + else
> > > > + reg |= BIT(id);
> > > > +
> > > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_deassert(struct
> > > > reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > > unsigned long id)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + usleep_range(1000, 1100);
> > > > +
> > >
> > > One question that I received in my series, and I couldn't answer
> > > because I don't have the datasheet, is if
> > > is this known to be enough for all IP cores that can be reset by
> > > this
> > > controller? Is this time specified in the datasheet?
> >
> > It only takes few cycles for the reset. The 1000us is enough for
> > the
> > reset to take effect.
> >
>
> Saying enough looks to me that 1000us is a random number, is there
> any
> specific real number in the datasheet?
>
> Note that I'm not against it, just want to make sure the number makes
> sense.
>
No real number is specified in the datasheet. I checked with the
hardware designer, and the reset takes four cycles of mm IP cores.
For example: If the mm IP cores run at 200MHz, it will take
20ns(4/200M) for the reset to take effect.
>
> > > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > > +}
> > > > +
> > > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > > + .assert = mtk_mmsys_reset_assert,
> > > > + .deassert = mtk_mmsys_reset_deassert,
> > > > + .reset = mtk_mmsys_reset,
> > > > +};
> > > > +
> > > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > > {
> > > > struct device *dev = &pdev->dev;
> > > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > > platform_device *pdev)
> > > > if (ret)
> > > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > > #endif
> > > > +
> > > > + spin_lock_init(&mmsys->lock);
> > > > +
> > > > + mmsys->rcdev.owner = THIS_MODULE;
> > > > + mmsys->rcdev.nr_resets = 64;
> > >
> > > Is the number of resets 64 for MT8195? I think is 32 for MT8173
> > > and
> > > MT8183. Can you confirm?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > The number of resets in MT8195 vdosys1 is 64 (43 resets are used,
> > 21
> > are not used).
> >
>
> Ok, thanks for the information.
>
> > > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > > + ret = devm_reset_controller_register(&pdev->dev,
> > > > &mmsys-
> > > > > rcdev);
> > > >
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "Couldn't register mmsys
> > > > reset
> > > > controller: %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > platform_set_drvdata(pdev, mmsys);
> > > >
> > > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > > > data->clk_driver,
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > > index 084b1f5f3c88..cc57c3895c51 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > > const unsigned int num_routes;
> > > > const struct mtk_mmsys_config *config;
> > > > const unsigned int num_configs;
> > > > + u32 sw_reset_start;
> > > > };
> > > >
> > > > /*
> > > > --
> > > > 2.18.0
> > > >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
@ 2021-07-30 3:47 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-07-30 3:47 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Yongqiang Niu,
Linux ARM
Hi Enric,
On Wed, 2021-07-28 at 12:31 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de
> jul.
> 2021 a les 8:01:
> >
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:46:
> > > >
> > > > Among other features the mmsys driver should implement a reset
> > > > controller to be able to reset different bits from their space.
> > > >
> > >
> > > I'm working on a series that does the same, it should be nice if
> > > we
> > > can coordinate [1]
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> > >
> > >
> >
> > OK, I will add this series to my reference base in the next patch
> > revision.
> >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > > > drivers/soc/mediatek/mtk-mmsys.c | 77
> > > > +++++++++++++++++++++++++++++
> > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > 3 files changed, 79 insertions(+)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -154,6 +154,7 @@
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1
> > > > << 0)
> > > > #define
> > > > DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2
> > > > << 0)
> > > >
> > > > +#define MT8195_VDO1_SW0_RST_B 0x1d0
> > > > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > > > #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > > > #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index d0f4a407f8f8..1ae04efeadab 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -4,10 +4,12 @@
> > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > */
> > > >
> > > > +#include <linux/delay.h>
> > > > #include <linux/device.h>
> > > > #include <linux/io.h>
> > > > #include <linux/of_device.h>
> > > > #include <linux/platform_device.h>
> > > > +#include <linux/reset-controller.h>
> > > > #include <linux/soc/mediatek/mtk-mmsys.h>
> > > >
> > > > #include "mtk-mmsys.h"
> > > > @@ -15,6 +17,8 @@
> > > > #include "mt8183-mmsys.h"
> > > > #include "mt8195-mmsys.h"
> > > >
> > > > +#define MMSYS_SW_RESET_PER_REG 32
> > > > +
> > > > static const struct mtk_mmsys_driver_data
> > > > mt2701_mmsys_driver_data
> > > > = {
> > > > .clk_driver = "clk-mt2701-mm",
> > > > .routes = mmsys_default_routing_table,
> > > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > .config = mmsys_mt8195_config_table,
> > > > .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > > + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> > >
> > > That change is interesting and I think I should also take it into
> > > consideration with my series.
> > >
> > > > };
> > > >
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > struct cmdq_client_reg cmdq_base;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > + spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > >
> > > Seems that mmsys_sw_rst_b reg has different names for different
> > > SoCs?
> > > I mean I know that for MT8173 and MT8183 the register is called
> > > mmsys_sw0_rst_b but looks like for MT8195 the name is
> > > vdo1_sw0_rst_b?
> > > So maybe we should update this comment to be more generic.
> > >
> >
> > Yes, the name of MT8195 vdosys1 sw reset is called
> > VDOSYS1_SW0_RST_B
> > and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They
> > have
> > a different name. Maybe we can change the comment to "protects
> > mmsys sw
> > reset reg".
> >
> > > >
> > > > + struct reset_controller_dev rcdev;
> > > > };
> > > >
> > > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device
> > > > *dev,
> > > > enum mtk_mmsys_config_type config,
> > > > }
> > > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > > >
> > > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > > *rcdev, unsigned long id,
> > > > + bool assert)
> > > > +{
> > > > + struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > > mtk_mmsys, rcdev);
> > > > + unsigned long flags;
> > > > + u32 reg;
> > > > + int i;
> > > > + u32 offset;
> > > > +
> > > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > > + id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > > +
> > > > + spin_lock_irqsave(&mmsys->lock, flags);
> > > > +
> > > > + reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + if (assert)
> > > > + reg &= ~BIT(id);
> > > > + else
> > > > + reg |= BIT(id);
> > > > +
> > > > + writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > > > sw_reset_start + offset);
> > > >
> > > > +
> > > > + spin_unlock_irqrestore(&mmsys->lock, flags);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, true);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset_deassert(struct
> > > > reset_controller_dev
> > > > *rcdev, unsigned long id)
> > > > +{
> > > > + return mtk_mmsys_reset_update(rcdev, id, false);
> > > > +}
> > > > +
> > > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > > unsigned long id)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + ret = mtk_mmsys_reset_assert(rcdev, id);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + usleep_range(1000, 1100);
> > > > +
> > >
> > > One question that I received in my series, and I couldn't answer
> > > because I don't have the datasheet, is if
> > > is this known to be enough for all IP cores that can be reset by
> > > this
> > > controller? Is this time specified in the datasheet?
> >
> > It only takes few cycles for the reset. The 1000us is enough for
> > the
> > reset to take effect.
> >
>
> Saying enough looks to me that 1000us is a random number, is there
> any
> specific real number in the datasheet?
>
> Note that I'm not against it, just want to make sure the number makes
> sense.
>
No real number is specified in the datasheet. I checked with the
hardware designer, and the reset takes four cycles of mm IP cores.
For example: If the mm IP cores run at 200MHz, it will take
20ns(4/200M) for the reset to take effect.
>
> > > > + return mtk_mmsys_reset_deassert(rcdev, id);
> > > > +}
> > > > +
> > > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > > + .assert = mtk_mmsys_reset_assert,
> > > > + .deassert = mtk_mmsys_reset_deassert,
> > > > + .reset = mtk_mmsys_reset,
> > > > +};
> > > > +
> > > > static int mtk_mmsys_probe(struct platform_device *pdev)
> > > > {
> > > > struct device *dev = &pdev->dev;
> > > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > > platform_device *pdev)
> > > > if (ret)
> > > > dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > > > #endif
> > > > +
> > > > + spin_lock_init(&mmsys->lock);
> > > > +
> > > > + mmsys->rcdev.owner = THIS_MODULE;
> > > > + mmsys->rcdev.nr_resets = 64;
> > >
> > > Is the number of resets 64 for MT8195? I think is 32 for MT8173
> > > and
> > > MT8183. Can you confirm?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > The number of resets in MT8195 vdosys1 is 64 (43 resets are used,
> > 21
> > are not used).
> >
>
> Ok, thanks for the information.
>
> > > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > > + mmsys->rcdev.of_node = pdev->dev.of_node;
> > > > + ret = devm_reset_controller_register(&pdev->dev,
> > > > &mmsys-
> > > > > rcdev);
> > > >
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "Couldn't register mmsys
> > > > reset
> > > > controller: %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > platform_set_drvdata(pdev, mmsys);
> > > >
> > > > clks = platform_device_register_data(&pdev->dev, mmsys-
> > > > > data->clk_driver,
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > > index 084b1f5f3c88..cc57c3895c51 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > > > const unsigned int num_routes;
> > > > const struct mtk_mmsys_config *config;
> > > > const unsigned int num_configs;
> > > > + u32 sw_reset_start;
> > > > };
> > > >
> > > > /*
> > > > --
> > > > 2.18.0
> > > >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-08-02 3:34 ` CK Hu
-1 siblings, 0 replies; 99+ messages in thread
From: CK Hu @ 2021-08-02 3:34 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Thu, 2021-07-22 at 17:45 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 356 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 768c282d2d63..829570308761 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/reset.h>
> #include <linux/component.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> @@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
> +
> + if (priv->async_clk)
> + device_reset_optional(dev);
Move this to the merge patch [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729170737.21424-7-jason-jh.lin@mediatek.com/
> }
>
> static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 40df2c823187..3324fa1a9e8c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> - const enum mtk_ddp_comp_id *path, unsigned int path_len)
> + const enum mtk_ddp_comp_id *path, unsigned int path_len,
> + int priv_data_index)
> {
> struct mtk_drm_private *priv = drm_dev->dev_private;
> struct device *dev = drm_dev->dev;
> struct mtk_drm_crtc *mtk_crtc;
> unsigned int num_comp_planes = 0;
> - int pipe = priv->num_pipes;
> int ret;
> int i;
> bool has_ctm = false;
> uint gamma_lut_size = 0;
> + struct drm_crtc *tmp;
> + int crtc_i = 0;
>
> if (!path)
> return 0;
>
> + priv = priv->all_drm_private[priv_data_index];
> +
> + drm_for_each_crtc(tmp, drm_dev)
> + crtc_i++;
> +
> for (i = 0; i < path_len; i++) {
> enum mtk_ddp_comp_id comp_id = path[i];
> struct device_node *node;
> @@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> if (!node) {
> dev_info(dev,
> "Not creating crtc %d because component %d is disabled or missing\n",
> - pipe, comp_id);
> + crtc_i, comp_id);
> return 0;
> }
> }
> @@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
> - pipe);
> + crtc_i);
> if (ret)
> return ret;
> }
>
> - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
> + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
> if (ret < 0)
> return ret;
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> - priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 66d1cf03dfe8..0646fafffd8b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -31,7 +31,8 @@
> void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> - unsigned int path_len);
> + unsigned int path_len,
> + int priv_data_index);
> int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
> struct mtk_plane_state *state);
> void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..25f293542f79 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
Move this to the pseudo ovl patch.
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
ditto.
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
ditto.
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
ditto.
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f2a184b1eceb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_PSEUDO_OVL,
ditto.
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 58f9f9f06e94..94527fb040be 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -11,6 +11,7 @@
> #include <linux/of_platform.h>
> #include <linux/pm_runtime.h>
> #include <linux/dma-mapping.h>
> +#include <linux/reset-controller.h>
>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> @@ -35,6 +36,16 @@
> #define DRIVER_MAJOR 1
> #define DRIVER_MINOR 0
>
> +/* duplicate with mmsys private data */
> +struct mtk_mmsys_private {
> + void __iomem *regs_reserved;
> + struct cmdq_client_reg cmdq_base_reserved;
> + void *data_reserved;
> + spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
> + struct reset_controller_dev rcdev_reserved;
> + void *drm_private;
> +};
> +
> static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
> .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
> };
> @@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> DDP_COMPONENT_DP_INTF0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
> + DDP_COMPONENT_PSEUDO_OVL,
> + DDP_COMPONENT_MERGE5,
> + DDP_COMPONENT_DP_INTF1,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> .ext_path = mt2701_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> @@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> .ext_path = mt7623_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> @@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
> .third_path = mt2712_mtk_ddp_third,
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> @@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> .ext_path = mt8173_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> @@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> .ext_path = mt8183_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .main_path = mt8195_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .ext_path = mt8195_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
> + .mmsys_id = 1,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct of_device_id mtk_drm_of_ids[] = {
> + { .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data},
> + { .compatible = "mediatek,mt7623-mmsys",
> + .data = &mt7623_mmsys_driver_data},
> + { .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data},
> + { .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data},
> + { .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys0",
> + .data = &mt8195_vdosys0_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data},
> + { }
> };
> +MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> +
> +static int mtk_drm_get_mmsys_priv(struct device *dev,
> + struct mtk_drm_private **all_drm_priv,
> + int num)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + struct device_node *node;
> + int cnt = 0;
> +
> + for_each_child_of_node(phandle->parent, node) {
> + struct platform_device *pdev;
> + struct mtk_mmsys_private *mmsys_priv;
> +
> + of_id = of_match_node(mtk_drm_of_ids, node);
> + if (!of_id)
> + continue;
> +
> + pdev = of_find_device_by_node(node);
> + if (!pdev)
> + continue;
> +
> + mmsys_priv = dev_get_drvdata(&pdev->dev);
> + if (!mmsys_priv || !mmsys_priv->drm_private)
> + continue;
> +
> + all_drm_priv[cnt++] = mmsys_priv->drm_private;
> + if (cnt == num)
> + break;
> + }
> +
> + return 0;
> +}
Move "support multiple mmsys" related code to another patch, and left
only mt8195 part in this patch.
Regards,
CK
> +
> +static bool mtk_drm_check_last_drm_bind(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int cnt = 0;
> + int i;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++)
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
> + cnt++;
> +
> + return (drm_priv->data->mmsys_dev_num == cnt);
> +}
> +
> +static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
> +{
> + struct device_node *phandle = dev->parent->of_node;
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int i;
> +
> + if (!drm_priv->data->mmsys_dev_num)
> + return false;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++) {
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
> + *drm = all_drm_priv[i]->drm;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> +static int mtk_drm_setup_all_drm_private(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
> + int i;
> + int j;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
> +
> + for (i = 0; i < mmsys_dev_num; i++)
> + for (j = 0; j < mmsys_dev_num; j++)
> + all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
> +
> + return 0;
> +}
> +
> +static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
> +{
> + const struct mtk_mmsys_driver_data *drv_data = private->data;
> + int ret = false;
> + int i;
> +
> + if (drv_data->mmsys_dev_num == 1)
> + return true;
> +
> + if (drv_data->main_path) {
> + for (i = 0; i < drv_data->main_len; i++)
> + if (drv_data->main_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->main_len)
> + ret |= false;
> + }
> +
> + if (drv_data->ext_path) {
> + for (i = 0; i < drv_data->ext_len; i++)
> + if (drv_data->ext_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->ext_len)
> + ret |= false;
> + }
> +
> + if (drv_data->third_path) {
> + for (i = 0; i < drv_data->third_len; i++)
> + if (drv_data->third_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->third_len)
> + ret |= false;
> + }
> +
> + return ret;
> +}
> +
> +static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
> +{
> + struct platform_device *pdev;
> + struct mtk_drm_private *priv_i;
> + int ret;
> + int i;
> +
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> +
> + pdev = of_find_device_by_node(priv_i->mutex_node);
> + if (!pdev) {
> + dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
> + priv_i->mutex_node);
> + ret = -EPROBE_DEFER;
> + goto err_put_mutex;
> + }
> + priv_i->mutex_dev = &pdev->dev;
> + }
> +
> + return 0;
> +
> +err_put_mutex:
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> + of_node_put(priv_i->mutex_node);
> + }
> +
> + return ret;
> +}
>
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> + struct mtk_drm_private *priv_n;
> struct platform_device *pdev;
> - struct device_node *np;
> + struct device_node *np = NULL;
> struct device *dma_dev;
> int ret;
> + int i;
> + int j;
>
> if (!iommu_present(&platform_bus_type))
> return -EPROBE_DEFER;
>
> - pdev = of_find_device_by_node(private->mutex_node);
> - if (!pdev) {
> - dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
> - private->mutex_node);
> - of_node_put(private->mutex_node);
> - return -EPROBE_DEFER;
> - }
> - private->mutex_dev = &pdev->dev;
> + ret = mtk_drm_check_mutex_dev(private);
> + if (ret)
> + return ret;
>
> ret = drmm_mode_config_init(drm);
> if (ret)
> @@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
> drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
>
> - ret = component_bind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + drm->dev_private = private->all_drm_private[i];
> + ret = component_bind_all(private->all_drm_private[i]->dev, drm);
> if (ret)
> goto put_mutex_dev;
> + }
>
> /*
> * We currently support two fixed data streams, each optional,
> * and each statically assigned to a crtc:
> * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
> */
> - ret = mtk_drm_crtc_create(drm, private->data->main_path,
> - private->data->main_len);
> - if (ret < 0)
> - goto err_component_unbind;
> - /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
> - ret = mtk_drm_crtc_create(drm, private->data->ext_path,
> - private->data->ext_len);
> - if (ret < 0)
> - goto err_component_unbind;
> -
> - ret = mtk_drm_crtc_create(drm, private->data->third_path,
> - private->data->third_len);
> - if (ret < 0)
> - goto err_component_unbind;
> + for (i = 0; i < MAX_CRTC; i++) {
> + for (j = 0; j < private->data->mmsys_dev_num; j++) {
> + priv_n = private->all_drm_private[j];
> +
> + if (i == 0 && priv_n->data->main_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
> + priv_n->data->main_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->main_path[0]];
> +
> + continue;
> + } else if (i == 1 && priv_n->data->ext_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
> + priv_n->data->ext_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->ext_path[0]];
> +
> + continue;
> + } else if (i == 2 && priv_n->data->third_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
> + priv_n->data->third_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->third_path[0]];
> +
> + continue;
> + }
> + }
> + }
>
> /* Use OVL device for all DMA memory allocations */
> - np = private->comp_node[private->data->main_path[0]] ?:
> - private->comp_node[private->data->ext_path[0]];
> pdev = of_find_device_by_node(np);
> if (!pdev) {
> ret = -ENODEV;
> @@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> }
>
> dma_dev = &pdev->dev;
> - private->dma_dev = dma_dev;
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + private->all_drm_private[i]->dma_dev = dma_dev;
>
> /*
> * Configure the DMA segment size to make sure we get contiguous IOVA
> * when importing PRIME buffers.
> */
> ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
> +
> if (ret) {
> dev_err(dma_dev, "Failed to set DMA segment size\n");
> goto err_component_unbind;
> @@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> return 0;
>
> err_component_unbind:
> - component_unbind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + component_unbind_all(private->all_drm_private[i]->dev, drm);
> put_mutex_dev:
> - put_device(private->mutex_dev);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + put_device(private->all_drm_private[i]->mutex_dev);
> +
> return ret;
> }
>
> @@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
> struct drm_device *drm;
> int ret;
>
> - drm = drm_dev_alloc(&mtk_drm_driver, dev);
> - if (IS_ERR(drm))
> - return PTR_ERR(drm);
> + if (!mtk_drm_find_drm_dev(dev, &drm)) {
> + drm = drm_dev_alloc(&mtk_drm_driver, dev);
> + if (IS_ERR(drm))
> + return PTR_ERR(drm);
> + drm->dev_private = private;
> + }
>
> - drm->dev_private = private;
> + private->dev = dev;
> private->drm = drm;
> + private->mtk_drm_bound = true;
> +
> + if (!mtk_drm_check_last_drm_bind(dev))
> + return 0;
> +
> + mtk_drm_setup_all_drm_private(dev);
>
> ret = mtk_drm_kms_init(drm);
> if (ret < 0)
> @@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
> {
> struct mtk_drm_private *private = dev_get_drvdata(dev);
>
> - drm_dev_unregister(private->drm);
> - mtk_drm_kms_deinit(private->drm);
> - drm_dev_put(private->drm);
> - private->num_pipes = 0;
> + /* for multi mmsys dev, unregister drm dev in mmsys master */
> + if (private->data->mmsys_id == 0) {
> + drm_dev_unregister(private->drm);
> + mtk_drm_kms_deinit(private->drm);
> + drm_dev_put(private->drm);
> + }
> + private->mtk_drm_bound = false;
> private->drm = NULL;
> }
>
> @@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { }
> };
>
> -static const struct of_device_id mtk_drm_of_ids[] = {
> - { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> - { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> - { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> - { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> - { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> - {.compatible = "mediatek,mt8195-vdosys0",
> - .data = &mt8195_vdosys0_driver_data},
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> -
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_driver_data *drv_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> + struct mtk_mmsys_private *mmsys_priv;
> int ret;
> int i;
>
> + of_id = of_match_node(mtk_drm_of_ids, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + drv_data = of_id->data;
> private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
> if (!private)
> return -ENOMEM;
>
> + private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
> + sizeof(*private->all_drm_private),
> + GFP_KERNEL);
> + if (!private->all_drm_private)
> + return -ENOMEM;
> +
> + private->data = drv_data;
> private->mmsys_dev = dev->parent;
> if (!private->mmsys_dev) {
> dev_err(dev, "Failed to get MMSYS device\n");
> return -ENODEV;
> }
> -
> - of_id = of_match_node(mtk_drm_of_ids, phandle);
> - if (!of_id)
> - return -ENODEV;
> -
> - private->data = of_id->data;
> + mmsys_priv = dev_get_drvdata(private->mmsys_dev);
> + mmsys_priv->drm_private = private;
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> @@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type = (enum mtk_ddp_comp_type)of_id->data;
>
> if (comp_type == MTK_DISP_MUTEX) {
> - private->mutex_node = of_node_get(node);
> + int id;
> +
> + id = of_alias_get_id(node, "mutex");
> + if (id < 0 || id == drv_data->mmsys_id) {
> + private->mutex_node = of_node_get(node);
> + dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
> + }
> continue;
> }
>
> @@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
> continue;
> }
>
> + if (!mtk_drm_find_mmsys_comp(private, comp_id))
> + continue;
> +
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> @@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..212e4f87c35c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
> unsigned int third_len;
>
> bool shadow_register;
> + unsigned int mmsys_id;
> + unsigned int mmsys_dev_num;
> };
>
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
> -
> - unsigned int num_pipes;
> -
> + bool mtk_drm_bound;
> + struct device *dev;
> struct device_node *mutex_node;
> struct device *mutex_dev;
> struct device *mmsys_dev;
> @@ -44,6 +45,7 @@ struct mtk_drm_private {
> struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
> const struct mtk_mmsys_driver_data *data;
> struct drm_atomic_state *suspend_state;
> + struct mtk_drm_private **all_drm_private;
> };
>
> extern struct platform_driver mtk_disp_ccorr_driver;
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-02 3:34 ` CK Hu
0 siblings, 0 replies; 99+ messages in thread
From: CK Hu @ 2021-08-02 3:34 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Thu, 2021-07-22 at 17:45 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 356 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 768c282d2d63..829570308761 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/reset.h>
> #include <linux/component.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> @@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
> +
> + if (priv->async_clk)
> + device_reset_optional(dev);
Move this to the merge patch [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729170737.21424-7-jason-jh.lin@mediatek.com/
> }
>
> static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 40df2c823187..3324fa1a9e8c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> - const enum mtk_ddp_comp_id *path, unsigned int path_len)
> + const enum mtk_ddp_comp_id *path, unsigned int path_len,
> + int priv_data_index)
> {
> struct mtk_drm_private *priv = drm_dev->dev_private;
> struct device *dev = drm_dev->dev;
> struct mtk_drm_crtc *mtk_crtc;
> unsigned int num_comp_planes = 0;
> - int pipe = priv->num_pipes;
> int ret;
> int i;
> bool has_ctm = false;
> uint gamma_lut_size = 0;
> + struct drm_crtc *tmp;
> + int crtc_i = 0;
>
> if (!path)
> return 0;
>
> + priv = priv->all_drm_private[priv_data_index];
> +
> + drm_for_each_crtc(tmp, drm_dev)
> + crtc_i++;
> +
> for (i = 0; i < path_len; i++) {
> enum mtk_ddp_comp_id comp_id = path[i];
> struct device_node *node;
> @@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> if (!node) {
> dev_info(dev,
> "Not creating crtc %d because component %d is disabled or missing\n",
> - pipe, comp_id);
> + crtc_i, comp_id);
> return 0;
> }
> }
> @@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
> - pipe);
> + crtc_i);
> if (ret)
> return ret;
> }
>
> - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
> + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
> if (ret < 0)
> return ret;
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> - priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 66d1cf03dfe8..0646fafffd8b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -31,7 +31,8 @@
> void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> - unsigned int path_len);
> + unsigned int path_len,
> + int priv_data_index);
> int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
> struct mtk_plane_state *state);
> void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..25f293542f79 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
Move this to the pseudo ovl patch.
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
ditto.
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
ditto.
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
ditto.
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f2a184b1eceb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_PSEUDO_OVL,
ditto.
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 58f9f9f06e94..94527fb040be 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -11,6 +11,7 @@
> #include <linux/of_platform.h>
> #include <linux/pm_runtime.h>
> #include <linux/dma-mapping.h>
> +#include <linux/reset-controller.h>
>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> @@ -35,6 +36,16 @@
> #define DRIVER_MAJOR 1
> #define DRIVER_MINOR 0
>
> +/* duplicate with mmsys private data */
> +struct mtk_mmsys_private {
> + void __iomem *regs_reserved;
> + struct cmdq_client_reg cmdq_base_reserved;
> + void *data_reserved;
> + spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
> + struct reset_controller_dev rcdev_reserved;
> + void *drm_private;
> +};
> +
> static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
> .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
> };
> @@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> DDP_COMPONENT_DP_INTF0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
> + DDP_COMPONENT_PSEUDO_OVL,
> + DDP_COMPONENT_MERGE5,
> + DDP_COMPONENT_DP_INTF1,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> .ext_path = mt2701_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> @@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> .ext_path = mt7623_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> @@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
> .third_path = mt2712_mtk_ddp_third,
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> @@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> .ext_path = mt8173_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> @@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> .ext_path = mt8183_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .main_path = mt8195_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .ext_path = mt8195_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
> + .mmsys_id = 1,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct of_device_id mtk_drm_of_ids[] = {
> + { .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data},
> + { .compatible = "mediatek,mt7623-mmsys",
> + .data = &mt7623_mmsys_driver_data},
> + { .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data},
> + { .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data},
> + { .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys0",
> + .data = &mt8195_vdosys0_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data},
> + { }
> };
> +MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> +
> +static int mtk_drm_get_mmsys_priv(struct device *dev,
> + struct mtk_drm_private **all_drm_priv,
> + int num)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + struct device_node *node;
> + int cnt = 0;
> +
> + for_each_child_of_node(phandle->parent, node) {
> + struct platform_device *pdev;
> + struct mtk_mmsys_private *mmsys_priv;
> +
> + of_id = of_match_node(mtk_drm_of_ids, node);
> + if (!of_id)
> + continue;
> +
> + pdev = of_find_device_by_node(node);
> + if (!pdev)
> + continue;
> +
> + mmsys_priv = dev_get_drvdata(&pdev->dev);
> + if (!mmsys_priv || !mmsys_priv->drm_private)
> + continue;
> +
> + all_drm_priv[cnt++] = mmsys_priv->drm_private;
> + if (cnt == num)
> + break;
> + }
> +
> + return 0;
> +}
Move "support multiple mmsys" related code to another patch, and left
only mt8195 part in this patch.
Regards,
CK
> +
> +static bool mtk_drm_check_last_drm_bind(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int cnt = 0;
> + int i;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++)
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
> + cnt++;
> +
> + return (drm_priv->data->mmsys_dev_num == cnt);
> +}
> +
> +static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
> +{
> + struct device_node *phandle = dev->parent->of_node;
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int i;
> +
> + if (!drm_priv->data->mmsys_dev_num)
> + return false;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++) {
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
> + *drm = all_drm_priv[i]->drm;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> +static int mtk_drm_setup_all_drm_private(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
> + int i;
> + int j;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
> +
> + for (i = 0; i < mmsys_dev_num; i++)
> + for (j = 0; j < mmsys_dev_num; j++)
> + all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
> +
> + return 0;
> +}
> +
> +static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
> +{
> + const struct mtk_mmsys_driver_data *drv_data = private->data;
> + int ret = false;
> + int i;
> +
> + if (drv_data->mmsys_dev_num == 1)
> + return true;
> +
> + if (drv_data->main_path) {
> + for (i = 0; i < drv_data->main_len; i++)
> + if (drv_data->main_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->main_len)
> + ret |= false;
> + }
> +
> + if (drv_data->ext_path) {
> + for (i = 0; i < drv_data->ext_len; i++)
> + if (drv_data->ext_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->ext_len)
> + ret |= false;
> + }
> +
> + if (drv_data->third_path) {
> + for (i = 0; i < drv_data->third_len; i++)
> + if (drv_data->third_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->third_len)
> + ret |= false;
> + }
> +
> + return ret;
> +}
> +
> +static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
> +{
> + struct platform_device *pdev;
> + struct mtk_drm_private *priv_i;
> + int ret;
> + int i;
> +
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> +
> + pdev = of_find_device_by_node(priv_i->mutex_node);
> + if (!pdev) {
> + dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
> + priv_i->mutex_node);
> + ret = -EPROBE_DEFER;
> + goto err_put_mutex;
> + }
> + priv_i->mutex_dev = &pdev->dev;
> + }
> +
> + return 0;
> +
> +err_put_mutex:
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> + of_node_put(priv_i->mutex_node);
> + }
> +
> + return ret;
> +}
>
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> + struct mtk_drm_private *priv_n;
> struct platform_device *pdev;
> - struct device_node *np;
> + struct device_node *np = NULL;
> struct device *dma_dev;
> int ret;
> + int i;
> + int j;
>
> if (!iommu_present(&platform_bus_type))
> return -EPROBE_DEFER;
>
> - pdev = of_find_device_by_node(private->mutex_node);
> - if (!pdev) {
> - dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
> - private->mutex_node);
> - of_node_put(private->mutex_node);
> - return -EPROBE_DEFER;
> - }
> - private->mutex_dev = &pdev->dev;
> + ret = mtk_drm_check_mutex_dev(private);
> + if (ret)
> + return ret;
>
> ret = drmm_mode_config_init(drm);
> if (ret)
> @@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
> drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
>
> - ret = component_bind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + drm->dev_private = private->all_drm_private[i];
> + ret = component_bind_all(private->all_drm_private[i]->dev, drm);
> if (ret)
> goto put_mutex_dev;
> + }
>
> /*
> * We currently support two fixed data streams, each optional,
> * and each statically assigned to a crtc:
> * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
> */
> - ret = mtk_drm_crtc_create(drm, private->data->main_path,
> - private->data->main_len);
> - if (ret < 0)
> - goto err_component_unbind;
> - /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
> - ret = mtk_drm_crtc_create(drm, private->data->ext_path,
> - private->data->ext_len);
> - if (ret < 0)
> - goto err_component_unbind;
> -
> - ret = mtk_drm_crtc_create(drm, private->data->third_path,
> - private->data->third_len);
> - if (ret < 0)
> - goto err_component_unbind;
> + for (i = 0; i < MAX_CRTC; i++) {
> + for (j = 0; j < private->data->mmsys_dev_num; j++) {
> + priv_n = private->all_drm_private[j];
> +
> + if (i == 0 && priv_n->data->main_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
> + priv_n->data->main_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->main_path[0]];
> +
> + continue;
> + } else if (i == 1 && priv_n->data->ext_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
> + priv_n->data->ext_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->ext_path[0]];
> +
> + continue;
> + } else if (i == 2 && priv_n->data->third_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
> + priv_n->data->third_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->third_path[0]];
> +
> + continue;
> + }
> + }
> + }
>
> /* Use OVL device for all DMA memory allocations */
> - np = private->comp_node[private->data->main_path[0]] ?:
> - private->comp_node[private->data->ext_path[0]];
> pdev = of_find_device_by_node(np);
> if (!pdev) {
> ret = -ENODEV;
> @@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> }
>
> dma_dev = &pdev->dev;
> - private->dma_dev = dma_dev;
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + private->all_drm_private[i]->dma_dev = dma_dev;
>
> /*
> * Configure the DMA segment size to make sure we get contiguous IOVA
> * when importing PRIME buffers.
> */
> ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
> +
> if (ret) {
> dev_err(dma_dev, "Failed to set DMA segment size\n");
> goto err_component_unbind;
> @@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> return 0;
>
> err_component_unbind:
> - component_unbind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + component_unbind_all(private->all_drm_private[i]->dev, drm);
> put_mutex_dev:
> - put_device(private->mutex_dev);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + put_device(private->all_drm_private[i]->mutex_dev);
> +
> return ret;
> }
>
> @@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
> struct drm_device *drm;
> int ret;
>
> - drm = drm_dev_alloc(&mtk_drm_driver, dev);
> - if (IS_ERR(drm))
> - return PTR_ERR(drm);
> + if (!mtk_drm_find_drm_dev(dev, &drm)) {
> + drm = drm_dev_alloc(&mtk_drm_driver, dev);
> + if (IS_ERR(drm))
> + return PTR_ERR(drm);
> + drm->dev_private = private;
> + }
>
> - drm->dev_private = private;
> + private->dev = dev;
> private->drm = drm;
> + private->mtk_drm_bound = true;
> +
> + if (!mtk_drm_check_last_drm_bind(dev))
> + return 0;
> +
> + mtk_drm_setup_all_drm_private(dev);
>
> ret = mtk_drm_kms_init(drm);
> if (ret < 0)
> @@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
> {
> struct mtk_drm_private *private = dev_get_drvdata(dev);
>
> - drm_dev_unregister(private->drm);
> - mtk_drm_kms_deinit(private->drm);
> - drm_dev_put(private->drm);
> - private->num_pipes = 0;
> + /* for multi mmsys dev, unregister drm dev in mmsys master */
> + if (private->data->mmsys_id == 0) {
> + drm_dev_unregister(private->drm);
> + mtk_drm_kms_deinit(private->drm);
> + drm_dev_put(private->drm);
> + }
> + private->mtk_drm_bound = false;
> private->drm = NULL;
> }
>
> @@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { }
> };
>
> -static const struct of_device_id mtk_drm_of_ids[] = {
> - { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> - { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> - { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> - { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> - { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> - {.compatible = "mediatek,mt8195-vdosys0",
> - .data = &mt8195_vdosys0_driver_data},
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> -
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_driver_data *drv_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> + struct mtk_mmsys_private *mmsys_priv;
> int ret;
> int i;
>
> + of_id = of_match_node(mtk_drm_of_ids, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + drv_data = of_id->data;
> private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
> if (!private)
> return -ENOMEM;
>
> + private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
> + sizeof(*private->all_drm_private),
> + GFP_KERNEL);
> + if (!private->all_drm_private)
> + return -ENOMEM;
> +
> + private->data = drv_data;
> private->mmsys_dev = dev->parent;
> if (!private->mmsys_dev) {
> dev_err(dev, "Failed to get MMSYS device\n");
> return -ENODEV;
> }
> -
> - of_id = of_match_node(mtk_drm_of_ids, phandle);
> - if (!of_id)
> - return -ENODEV;
> -
> - private->data = of_id->data;
> + mmsys_priv = dev_get_drvdata(private->mmsys_dev);
> + mmsys_priv->drm_private = private;
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> @@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type = (enum mtk_ddp_comp_type)of_id->data;
>
> if (comp_type == MTK_DISP_MUTEX) {
> - private->mutex_node = of_node_get(node);
> + int id;
> +
> + id = of_alias_get_id(node, "mutex");
> + if (id < 0 || id == drv_data->mmsys_id) {
> + private->mutex_node = of_node_get(node);
> + dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
> + }
> continue;
> }
>
> @@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
> continue;
> }
>
> + if (!mtk_drm_find_mmsys_comp(private, comp_id))
> + continue;
> +
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> @@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..212e4f87c35c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
> unsigned int third_len;
>
> bool shadow_register;
> + unsigned int mmsys_id;
> + unsigned int mmsys_dev_num;
> };
>
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
> -
> - unsigned int num_pipes;
> -
> + bool mtk_drm_bound;
> + struct device *dev;
> struct device_node *mutex_node;
> struct device *mutex_dev;
> struct device *mmsys_dev;
> @@ -44,6 +45,7 @@ struct mtk_drm_private {
> struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
> const struct mtk_mmsys_driver_data *data;
> struct drm_atomic_state *suspend_state;
> + struct mtk_drm_private **all_drm_private;
> };
>
> extern struct platform_driver mtk_disp_ccorr_driver;
_______________________________________________
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-08-02 3:34 ` CK Hu
0 siblings, 0 replies; 99+ messages in thread
From: CK Hu @ 2021-08-02 3:34 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Thu, 2021-07-22 at 17:45 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378 ++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 356 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 768c282d2d63..829570308761 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/reset.h>
> #include <linux/component.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> @@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
> +
> + if (priv->async_clk)
> + device_reset_optional(dev);
Move this to the merge patch [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729170737.21424-7-jason-jh.lin@mediatek.com/
> }
>
> static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 40df2c823187..3324fa1a9e8c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> - const enum mtk_ddp_comp_id *path, unsigned int path_len)
> + const enum mtk_ddp_comp_id *path, unsigned int path_len,
> + int priv_data_index)
> {
> struct mtk_drm_private *priv = drm_dev->dev_private;
> struct device *dev = drm_dev->dev;
> struct mtk_drm_crtc *mtk_crtc;
> unsigned int num_comp_planes = 0;
> - int pipe = priv->num_pipes;
> int ret;
> int i;
> bool has_ctm = false;
> uint gamma_lut_size = 0;
> + struct drm_crtc *tmp;
> + int crtc_i = 0;
>
> if (!path)
> return 0;
>
> + priv = priv->all_drm_private[priv_data_index];
> +
> + drm_for_each_crtc(tmp, drm_dev)
> + crtc_i++;
> +
> for (i = 0; i < path_len; i++) {
> enum mtk_ddp_comp_id comp_id = path[i];
> struct device_node *node;
> @@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> if (!node) {
> dev_info(dev,
> "Not creating crtc %d because component %d is disabled or missing\n",
> - pipe, comp_id);
> + crtc_i, comp_id);
> return 0;
> }
> }
> @@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
> - pipe);
> + crtc_i);
> if (ret)
> return ret;
> }
>
> - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
> + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
> if (ret < 0)
> return ret;
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> - priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 66d1cf03dfe8..0646fafffd8b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -31,7 +31,8 @@
> void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> - unsigned int path_len);
> + unsigned int path_len,
> + int priv_data_index);
> int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
> struct mtk_plane_state *state);
> void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..25f293542f79 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> + .layer_nr = mtk_ethdr_layer_nr,
> + .layer_config = mtk_ethdr_layer_config,
> + .enable_vblank = mtk_ethdr_enable_vblank,
> + .disable_vblank = mtk_ethdr_disable_vblank,
> +};
Move this to the pseudo ovl patch.
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -368,6 +380,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
ditto.
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -412,6 +425,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
ditto.
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -540,6 +554,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
ditto.
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f2a184b1eceb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_PSEUDO_OVL,
ditto.
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 58f9f9f06e94..94527fb040be 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -11,6 +11,7 @@
> #include <linux/of_platform.h>
> #include <linux/pm_runtime.h>
> #include <linux/dma-mapping.h>
> +#include <linux/reset-controller.h>
>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> @@ -35,6 +36,16 @@
> #define DRIVER_MAJOR 1
> #define DRIVER_MINOR 0
>
> +/* duplicate with mmsys private data */
> +struct mtk_mmsys_private {
> + void __iomem *regs_reserved;
> + struct cmdq_client_reg cmdq_base_reserved;
> + void *data_reserved;
> + spinlock_t lock_reserved; /* protects mmsys_sw_rst_b reg */
> + struct reset_controller_dev rcdev_reserved;
> + void *drm_private;
> +};
> +
> static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
> .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
> };
> @@ -160,12 +171,20 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> DDP_COMPONENT_DP_INTF0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
> + DDP_COMPONENT_PSEUDO_OVL,
> + DDP_COMPONENT_MERGE5,
> + DDP_COMPONENT_DP_INTF1,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> .ext_path = mt2701_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> @@ -174,6 +193,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
> .ext_path = mt7623_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
> .shadow_register = true,
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> @@ -183,6 +204,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
> .third_path = mt2712_mtk_ddp_third,
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> @@ -190,6 +213,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> .ext_path = mt8173_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> @@ -197,32 +222,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> .ext_path = mt8183_mtk_ddp_ext,
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 1,
> };
>
> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .main_path = mt8195_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> + .mmsys_id = 0,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .ext_path = mt8195_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
> + .mmsys_id = 1,
> + .mmsys_dev_num = 2,
> +};
> +
> +static const struct of_device_id mtk_drm_of_ids[] = {
> + { .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data},
> + { .compatible = "mediatek,mt7623-mmsys",
> + .data = &mt7623_mmsys_driver_data},
> + { .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data},
> + { .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data},
> + { .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys0",
> + .data = &mt8195_vdosys0_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data},
> + { }
> };
> +MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> +
> +static int mtk_drm_get_mmsys_priv(struct device *dev,
> + struct mtk_drm_private **all_drm_priv,
> + int num)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> + struct device_node *node;
> + int cnt = 0;
> +
> + for_each_child_of_node(phandle->parent, node) {
> + struct platform_device *pdev;
> + struct mtk_mmsys_private *mmsys_priv;
> +
> + of_id = of_match_node(mtk_drm_of_ids, node);
> + if (!of_id)
> + continue;
> +
> + pdev = of_find_device_by_node(node);
> + if (!pdev)
> + continue;
> +
> + mmsys_priv = dev_get_drvdata(&pdev->dev);
> + if (!mmsys_priv || !mmsys_priv->drm_private)
> + continue;
> +
> + all_drm_priv[cnt++] = mmsys_priv->drm_private;
> + if (cnt == num)
> + break;
> + }
> +
> + return 0;
> +}
Move "support multiple mmsys" related code to another patch, and left
only mt8195 part in this patch.
Regards,
CK
> +
> +static bool mtk_drm_check_last_drm_bind(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int cnt = 0;
> + int i;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++)
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
> + cnt++;
> +
> + return (drm_priv->data->mmsys_dev_num == cnt);
> +}
> +
> +static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
> +{
> + struct device_node *phandle = dev->parent->of_node;
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int i;
> +
> + if (!drm_priv->data->mmsys_dev_num)
> + return false;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
> +
> + for (i = 0; i < MAX_CRTC; i++) {
> + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
> + *drm = all_drm_priv[i]->drm;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> +static int mtk_drm_setup_all_drm_private(struct device *dev)
> +{
> + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
> + struct mtk_drm_private *all_drm_priv[MAX_CRTC];
> + int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
> + int i;
> + int j;
> +
> + mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
> +
> + for (i = 0; i < mmsys_dev_num; i++)
> + for (j = 0; j < mmsys_dev_num; j++)
> + all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
> +
> + return 0;
> +}
> +
> +static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
> +{
> + const struct mtk_mmsys_driver_data *drv_data = private->data;
> + int ret = false;
> + int i;
> +
> + if (drv_data->mmsys_dev_num == 1)
> + return true;
> +
> + if (drv_data->main_path) {
> + for (i = 0; i < drv_data->main_len; i++)
> + if (drv_data->main_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->main_len)
> + ret |= false;
> + }
> +
> + if (drv_data->ext_path) {
> + for (i = 0; i < drv_data->ext_len; i++)
> + if (drv_data->ext_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->ext_len)
> + ret |= false;
> + }
> +
> + if (drv_data->third_path) {
> + for (i = 0; i < drv_data->third_len; i++)
> + if (drv_data->third_path[i] == comp_id)
> + ret |= true;
> +
> + if (i == drv_data->third_len)
> + ret |= false;
> + }
> +
> + return ret;
> +}
> +
> +static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
> +{
> + struct platform_device *pdev;
> + struct mtk_drm_private *priv_i;
> + int ret;
> + int i;
> +
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> +
> + pdev = of_find_device_by_node(priv_i->mutex_node);
> + if (!pdev) {
> + dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
> + priv_i->mutex_node);
> + ret = -EPROBE_DEFER;
> + goto err_put_mutex;
> + }
> + priv_i->mutex_dev = &pdev->dev;
> + }
> +
> + return 0;
> +
> +err_put_mutex:
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + priv_i = private->all_drm_private[i];
> + of_node_put(priv_i->mutex_node);
> + }
> +
> + return ret;
> +}
>
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> + struct mtk_drm_private *priv_n;
> struct platform_device *pdev;
> - struct device_node *np;
> + struct device_node *np = NULL;
> struct device *dma_dev;
> int ret;
> + int i;
> + int j;
>
> if (!iommu_present(&platform_bus_type))
> return -EPROBE_DEFER;
>
> - pdev = of_find_device_by_node(private->mutex_node);
> - if (!pdev) {
> - dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
> - private->mutex_node);
> - of_node_put(private->mutex_node);
> - return -EPROBE_DEFER;
> - }
> - private->mutex_dev = &pdev->dev;
> + ret = mtk_drm_check_mutex_dev(private);
> + if (ret)
> + return ret;
>
> ret = drmm_mode_config_init(drm);
> if (ret)
> @@ -241,33 +453,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
> drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
>
> - ret = component_bind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++) {
> + drm->dev_private = private->all_drm_private[i];
> + ret = component_bind_all(private->all_drm_private[i]->dev, drm);
> if (ret)
> goto put_mutex_dev;
> + }
>
> /*
> * We currently support two fixed data streams, each optional,
> * and each statically assigned to a crtc:
> * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
> */
> - ret = mtk_drm_crtc_create(drm, private->data->main_path,
> - private->data->main_len);
> - if (ret < 0)
> - goto err_component_unbind;
> - /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
> - ret = mtk_drm_crtc_create(drm, private->data->ext_path,
> - private->data->ext_len);
> - if (ret < 0)
> - goto err_component_unbind;
> -
> - ret = mtk_drm_crtc_create(drm, private->data->third_path,
> - private->data->third_len);
> - if (ret < 0)
> - goto err_component_unbind;
> + for (i = 0; i < MAX_CRTC; i++) {
> + for (j = 0; j < private->data->mmsys_dev_num; j++) {
> + priv_n = private->all_drm_private[j];
> +
> + if (i == 0 && priv_n->data->main_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
> + priv_n->data->main_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->main_path[0]];
> +
> + continue;
> + } else if (i == 1 && priv_n->data->ext_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
> + priv_n->data->ext_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->ext_path[0]];
> +
> + continue;
> + } else if (i == 2 && priv_n->data->third_len) {
> + ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
> + priv_n->data->third_len, j);
> + if (ret)
> + goto err_component_unbind;
> +
> + if (!np)
> + np = priv_n->comp_node[priv_n->data->third_path[0]];
> +
> + continue;
> + }
> + }
> + }
>
> /* Use OVL device for all DMA memory allocations */
> - np = private->comp_node[private->data->main_path[0]] ?:
> - private->comp_node[private->data->ext_path[0]];
> pdev = of_find_device_by_node(np);
> if (!pdev) {
> ret = -ENODEV;
> @@ -276,13 +512,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> }
>
> dma_dev = &pdev->dev;
> - private->dma_dev = dma_dev;
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + private->all_drm_private[i]->dma_dev = dma_dev;
>
> /*
> * Configure the DMA segment size to make sure we get contiguous IOVA
> * when importing PRIME buffers.
> */
> ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
> +
> if (ret) {
> dev_err(dma_dev, "Failed to set DMA segment size\n");
> goto err_component_unbind;
> @@ -304,9 +542,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> return 0;
>
> err_component_unbind:
> - component_unbind_all(drm->dev, drm);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + component_unbind_all(private->all_drm_private[i]->dev, drm);
> put_mutex_dev:
> - put_device(private->mutex_dev);
> + for (i = 0; i < private->data->mmsys_dev_num; i++)
> + put_device(private->all_drm_private[i]->mutex_dev);
> +
> return ret;
> }
>
> @@ -371,12 +612,21 @@ static int mtk_drm_bind(struct device *dev)
> struct drm_device *drm;
> int ret;
>
> - drm = drm_dev_alloc(&mtk_drm_driver, dev);
> - if (IS_ERR(drm))
> - return PTR_ERR(drm);
> + if (!mtk_drm_find_drm_dev(dev, &drm)) {
> + drm = drm_dev_alloc(&mtk_drm_driver, dev);
> + if (IS_ERR(drm))
> + return PTR_ERR(drm);
> + drm->dev_private = private;
> + }
>
> - drm->dev_private = private;
> + private->dev = dev;
> private->drm = drm;
> + private->mtk_drm_bound = true;
> +
> + if (!mtk_drm_check_last_drm_bind(dev))
> + return 0;
> +
> + mtk_drm_setup_all_drm_private(dev);
>
> ret = mtk_drm_kms_init(drm);
> if (ret < 0)
> @@ -401,10 +651,13 @@ static void mtk_drm_unbind(struct device *dev)
> {
> struct mtk_drm_private *private = dev_get_drvdata(dev);
>
> - drm_dev_unregister(private->drm);
> - mtk_drm_kms_deinit(private->drm);
> - drm_dev_put(private->drm);
> - private->num_pipes = 0;
> + /* for multi mmsys dev, unregister drm dev in mmsys master */
> + if (private->data->mmsys_id == 0) {
> + drm_dev_unregister(private->drm);
> + mtk_drm_kms_deinit(private->drm);
> + drm_dev_put(private->drm);
> + }
> + private->mtk_drm_bound = false;
> private->drm = NULL;
> }
>
> @@ -485,49 +738,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { }
> };
>
> -static const struct of_device_id mtk_drm_of_ids[] = {
> - { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> - { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> - { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> - { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> - { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> - {.compatible = "mediatek,mt8195-vdosys0",
> - .data = &mt8195_vdosys0_driver_data},
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> -
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_driver_data *drv_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> + struct mtk_mmsys_private *mmsys_priv;
> int ret;
> int i;
>
> + of_id = of_match_node(mtk_drm_of_ids, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + drv_data = of_id->data;
> private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
> if (!private)
> return -ENOMEM;
>
> + private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
> + sizeof(*private->all_drm_private),
> + GFP_KERNEL);
> + if (!private->all_drm_private)
> + return -ENOMEM;
> +
> + private->data = drv_data;
> private->mmsys_dev = dev->parent;
> if (!private->mmsys_dev) {
> dev_err(dev, "Failed to get MMSYS device\n");
> return -ENODEV;
> }
> -
> - of_id = of_match_node(mtk_drm_of_ids, phandle);
> - if (!of_id)
> - return -ENODEV;
> -
> - private->data = of_id->data;
> + mmsys_priv = dev_get_drvdata(private->mmsys_dev);
> + mmsys_priv->drm_private = private;
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> @@ -548,7 +794,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type = (enum mtk_ddp_comp_type)of_id->data;
>
> if (comp_type == MTK_DISP_MUTEX) {
> - private->mutex_node = of_node_get(node);
> + int id;
> +
> + id = of_alias_get_id(node, "mutex");
> + if (id < 0 || id == drv_data->mmsys_id) {
> + private->mutex_node = of_node_get(node);
> + dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
> + }
> continue;
> }
>
> @@ -559,6 +811,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
> continue;
> }
>
> + if (!mtk_drm_find_mmsys_comp(private, comp_id))
> + continue;
> +
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> @@ -573,6 +828,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..212e4f87c35c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
> unsigned int third_len;
>
> bool shadow_register;
> + unsigned int mmsys_id;
> + unsigned int mmsys_dev_num;
> };
>
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
> -
> - unsigned int num_pipes;
> -
> + bool mtk_drm_bound;
> + struct device *dev;
> struct device_node *mutex_node;
> struct device *mutex_dev;
> struct device *mmsys_dev;
> @@ -44,6 +45,7 @@ struct mtk_drm_private {
> struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
> const struct mtk_mmsys_driver_data *data;
> struct drm_atomic_state *suspend_state;
> + struct mtk_drm_private **all_drm_private;
> };
>
> extern struct platform_driver mtk_disp_ccorr_driver;
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-07-28 5:34 ` Nancy.Lin
(?)
@ 2021-08-06 12:20 ` Matthias Brugger
-1 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 12:20 UTC (permalink / raw)
To: Nancy.Lin, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
On 28/07/2021 07:34, Nancy.Lin wrote:
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
>> Hi Nancy,
>>
>> Thank you for your patch.
>>
>> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
>> jul.
>> 2021 a les 11:45:
>>>
>>> Add mt8195 vdosys1 clock driver name and routing table to
>>> the driver data of mtk-mmsys.
>>>
>>> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mt8195-mmsys.h | 83
>>> ++++++++++++++++++++++++--
>>> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
>>> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
>>> 3 files changed, 90 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
>>> b/drivers/soc/mediatek/mt8195-mmsys.h
>>> index 73e9e8286d50..104ba575f765 100644
>>> --- a/drivers/soc/mediatek/mt8195-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
>>> @@ -64,16 +64,16 @@
>>> #define SOUT_TO_VPP_MERGE0_P1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
>>> -#define SOUT_TO_HDR_VDO_FE0 (0
>>> << 0)
>>
>> This definition was introduced in this patch [1] that didn't land
>> yet.
>> And you're removing it now. Could you sync with Jason and only
>> introduce the bits that are needed for your patches. Also all the
>> comments I made to the Jason's patch apply here.
>>
>> [1]
>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>>
>>
> OK, I will sync with Jason and modify it.
>
>>> +#define SOUT_TO_MIXER_IN1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
>>> -#define SOUT_TO_HDR_VDO_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN2_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
>>> -#define SOUT_TO_HDR_GFX_FE0 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN3_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
>>> -#define SOUT_TO_HDR_GFX_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN4_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
>>> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>> @@ -88,7 +88,7 @@
>>> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
>>> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
>>> << 0)
>>> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
>>> #define MERGE4_SOUT_TO_VDOSYS0 (0
>>> << 0)
>>> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
>>> mmsys_mt8195_routing_table[] = {
>>> }, {
>>> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
>>> MT8195_VDO0_SEL_OUT,
>>> SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
>>> VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
>>> VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
>>> VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN2_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN3_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN4_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
>>> MIXER_SOUT_TO_MERGE4_ASYNC_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN1_SEL_IN,
>>> MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN2_SEL_IN,
>>> MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN3_SEL_IN,
>>> MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN4_SEL_IN,
>>> MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_SOUT_SEL_IN,
>>> MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
>>> MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_DISP_DPI1_SEL_IN,
>>> DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DPI1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
>>> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DP_INTF0_SEL
>>> }
>>> };
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 1fb241750897..9e31aad6c5c8 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys1_driver_data = {
>>> + .clk_driver = "clk-mt8195-vdo1",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> struct mtk_mmsys {
>>> void __iomem *regs;
>>> const struct mtk_mmsys_driver_data *data;
>>> @@ -168,6 +174,10 @@ static const struct of_device_id
>>> of_match_mtk_mmsys[] = {
>>> .compatible = "mediatek,mt8195-vdosys0",
>>> .data = &mt8195_vdosys0_driver_data,
>>> },
>>> + {
>>> + .compatible = "mediatek,mt8195-vdosys1",
>>
>> Why do you need a second compatible, isn't this the same IP block? I
>> mean, I understand that you have 2 mmsys blocks, but both are the
>> same
>> IP block, right? or are they different?
>>
>> Thanks,
>> Enric
>>
> They(vdosys0 and vdosys1) are different IP block.
>
Please explain in what they are different. From what I see, you use the same
routing table for both compatibles and only register another platform device for
a second clock. Is that correct?
Regards,
Matthias
>>> + .data = &mt8195_vdosys1_driver_data,
>>> + },
>>> { }
>>> };
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
>>> b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 34cb605e5df9..338c71570aeb 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_DSC1,
>>> DDP_COMPONENT_DSC1_VIRTUAL0,
>>> DDP_COMPONENT_DP_INTF0,
>>> + DDP_COMPONENT_DP_INTF1,
>>> + DDP_COMPONENT_PSEUDO_OVL,
>>> DDP_COMPONENT_ID_MAX,
>>> };
>>>
>>> --
>>> 2.18.0
>>>
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-06 12:20 ` Matthias Brugger
0 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 12:20 UTC (permalink / raw)
To: Nancy.Lin, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
On 28/07/2021 07:34, Nancy.Lin wrote:
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
>> Hi Nancy,
>>
>> Thank you for your patch.
>>
>> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
>> jul.
>> 2021 a les 11:45:
>>>
>>> Add mt8195 vdosys1 clock driver name and routing table to
>>> the driver data of mtk-mmsys.
>>>
>>> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mt8195-mmsys.h | 83
>>> ++++++++++++++++++++++++--
>>> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
>>> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
>>> 3 files changed, 90 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
>>> b/drivers/soc/mediatek/mt8195-mmsys.h
>>> index 73e9e8286d50..104ba575f765 100644
>>> --- a/drivers/soc/mediatek/mt8195-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
>>> @@ -64,16 +64,16 @@
>>> #define SOUT_TO_VPP_MERGE0_P1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
>>> -#define SOUT_TO_HDR_VDO_FE0 (0
>>> << 0)
>>
>> This definition was introduced in this patch [1] that didn't land
>> yet.
>> And you're removing it now. Could you sync with Jason and only
>> introduce the bits that are needed for your patches. Also all the
>> comments I made to the Jason's patch apply here.
>>
>> [1]
>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>>
>>
> OK, I will sync with Jason and modify it.
>
>>> +#define SOUT_TO_MIXER_IN1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
>>> -#define SOUT_TO_HDR_VDO_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN2_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
>>> -#define SOUT_TO_HDR_GFX_FE0 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN3_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
>>> -#define SOUT_TO_HDR_GFX_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN4_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
>>> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>> @@ -88,7 +88,7 @@
>>> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
>>> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
>>> << 0)
>>> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
>>> #define MERGE4_SOUT_TO_VDOSYS0 (0
>>> << 0)
>>> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
>>> mmsys_mt8195_routing_table[] = {
>>> }, {
>>> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
>>> MT8195_VDO0_SEL_OUT,
>>> SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
>>> VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
>>> VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
>>> VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN2_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN3_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN4_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
>>> MIXER_SOUT_TO_MERGE4_ASYNC_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN1_SEL_IN,
>>> MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN2_SEL_IN,
>>> MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN3_SEL_IN,
>>> MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN4_SEL_IN,
>>> MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_SOUT_SEL_IN,
>>> MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
>>> MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_DISP_DPI1_SEL_IN,
>>> DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DPI1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
>>> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DP_INTF0_SEL
>>> }
>>> };
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 1fb241750897..9e31aad6c5c8 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys1_driver_data = {
>>> + .clk_driver = "clk-mt8195-vdo1",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> struct mtk_mmsys {
>>> void __iomem *regs;
>>> const struct mtk_mmsys_driver_data *data;
>>> @@ -168,6 +174,10 @@ static const struct of_device_id
>>> of_match_mtk_mmsys[] = {
>>> .compatible = "mediatek,mt8195-vdosys0",
>>> .data = &mt8195_vdosys0_driver_data,
>>> },
>>> + {
>>> + .compatible = "mediatek,mt8195-vdosys1",
>>
>> Why do you need a second compatible, isn't this the same IP block? I
>> mean, I understand that you have 2 mmsys blocks, but both are the
>> same
>> IP block, right? or are they different?
>>
>> Thanks,
>> Enric
>>
> They(vdosys0 and vdosys1) are different IP block.
>
Please explain in what they are different. From what I see, you use the same
routing table for both compatibles and only register another platform device for
a second clock. Is that correct?
Regards,
Matthias
>>> + .data = &mt8195_vdosys1_driver_data,
>>> + },
>>> { }
>>> };
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
>>> b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 34cb605e5df9..338c71570aeb 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_DSC1,
>>> DDP_COMPONENT_DSC1_VIRTUAL0,
>>> DDP_COMPONENT_DP_INTF0,
>>> + DDP_COMPONENT_DP_INTF1,
>>> + DDP_COMPONENT_PSEUDO_OVL,
>>> DDP_COMPONENT_ID_MAX,
>>> };
>>>
>>> --
>>> 2.18.0
>>>
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* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-06 12:20 ` Matthias Brugger
0 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 12:20 UTC (permalink / raw)
To: Nancy.Lin, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
On 28/07/2021 07:34, Nancy.Lin wrote:
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
>> Hi Nancy,
>>
>> Thank you for your patch.
>>
>> Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
>> jul.
>> 2021 a les 11:45:
>>>
>>> Add mt8195 vdosys1 clock driver name and routing table to
>>> the driver data of mtk-mmsys.
>>>
>>> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mt8195-mmsys.h | 83
>>> ++++++++++++++++++++++++--
>>> drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
>>> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
>>> 3 files changed, 90 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
>>> b/drivers/soc/mediatek/mt8195-mmsys.h
>>> index 73e9e8286d50..104ba575f765 100644
>>> --- a/drivers/soc/mediatek/mt8195-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
>>> @@ -64,16 +64,16 @@
>>> #define SOUT_TO_VPP_MERGE0_P1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
>>> -#define SOUT_TO_HDR_VDO_FE0 (0
>>> << 0)
>>
>> This definition was introduced in this patch [1] that didn't land
>> yet.
>> And you're removing it now. Could you sync with Jason and only
>> introduce the bits that are needed for your patches. Also all the
>> comments I made to the Jason's patch apply here.
>>
>> [1]
>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
>>
>>
> OK, I will sync with Jason and modify it.
>
>>> +#define SOUT_TO_MIXER_IN1_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
>>> -#define SOUT_TO_HDR_VDO_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN2_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
>>> -#define SOUT_TO_HDR_GFX_FE0 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN3_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
>>> -#define SOUT_TO_HDR_GFX_FE1 (0
>>> << 0)
>>> +#define SOUT_TO_MIXER_IN4_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
>>> #define MIXER_IN1_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>> @@ -88,7 +88,7 @@
>>> #define MIXER_IN4_SOUT_TO_DISP_MIXER (0
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
>>> -#define MIXER_SOUT_TO_HDR_VDO_BE0 (0
>>> << 0)
>>> +#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
>>> << 0)
>>>
>>> #define
>>> MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
>>> #define MERGE4_SOUT_TO_VDOSYS0 (0
>>> << 0)
>>> @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
>>> mmsys_mt8195_routing_table[] = {
>>> }, {
>>> DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
>>> MT8195_VDO0_SEL_OUT,
>>> SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
>>> VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
>>> VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
>>> VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN2_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN3_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
>>> SOUT_TO_MIXER_IN4_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
>>> MIXER_SOUT_TO_MERGE4_ASYNC_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN1_SEL_IN,
>>> MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN2_SEL_IN,
>>> MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN3_SEL_IN,
>>> MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_IN4_SEL_IN,
>>> MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MIXER_SOUT_SEL_IN,
>>> MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
>>> + },
>>> + {
>>> + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
>>> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
>>> MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_DISP_DPI1_SEL_IN,
>>> DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DPI1_SEL
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
>>> + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> + },
>>> + {
>>> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> + MT8195_VDO1_MERGE4_SOUT_SEL,
>>> MERGE4_SOUT_TO_DP_INTF0_SEL
>>> }
>>> };
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 1fb241750897..9e31aad6c5c8 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys1_driver_data = {
>>> + .clk_driver = "clk-mt8195-vdo1",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> struct mtk_mmsys {
>>> void __iomem *regs;
>>> const struct mtk_mmsys_driver_data *data;
>>> @@ -168,6 +174,10 @@ static const struct of_device_id
>>> of_match_mtk_mmsys[] = {
>>> .compatible = "mediatek,mt8195-vdosys0",
>>> .data = &mt8195_vdosys0_driver_data,
>>> },
>>> + {
>>> + .compatible = "mediatek,mt8195-vdosys1",
>>
>> Why do you need a second compatible, isn't this the same IP block? I
>> mean, I understand that you have 2 mmsys blocks, but both are the
>> same
>> IP block, right? or are they different?
>>
>> Thanks,
>> Enric
>>
> They(vdosys0 and vdosys1) are different IP block.
>
Please explain in what they are different. From what I see, you use the same
routing table for both compatibles and only register another platform device for
a second clock. Is that correct?
Regards,
Matthias
>>> + .data = &mt8195_vdosys1_driver_data,
>>> + },
>>> { }
>>> };
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
>>> b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 34cb605e5df9..338c71570aeb 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_DSC1,
>>> DDP_COMPONENT_DSC1_VIRTUAL0,
>>> DDP_COMPONENT_DP_INTF0,
>>> + DDP_COMPONENT_DP_INTF1,
>>> + DDP_COMPONENT_PSEUDO_OVL,
>>> DDP_COMPONENT_ID_MAX,
>>> };
>>>
>>> --
>>> 2.18.0
>>>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2021-07-22 9:45 ` Nancy.Lin
(?)
@ 2021-08-06 15:30 ` Matthias Brugger
-1 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 15:30 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
On 22/07/2021 11:45, Nancy.Lin wrote:
> Add mmsys config API.
This patch is doing a lot of things, it adds a "config" and it adds cmdq
support. Please explain better in the commit message what the config is for.
Please add comments to the different values of struct mtk_mmsys_config.
I understand that cmdq is optional, so please make addition to cmdq a separate
patch.
I'm a bit puzzled about that fact, can you please explain who you get the HW to
behave the same way when you write the same value and offset to mmsys-regs and
via cmdq.
Thanks,
Matthias
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> 4 files changed, 116 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 104ba575f765..4bdb2087250c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,18 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9e31aad6c5c8..d0f4a407f8f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .clk_driver = "clk-mt8195-vdo1",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> + .config = mmsys_mt8195_config_table,
> + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> };
>
> @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
> + u32 reg_val;
> + u32 mask;
> + u32 offset;
> + int i;
> +
> + if (!mmsys->data->num_configs)
> + return;
> +
> + for (i = 0; i < mmsys->data->num_configs; i++)
> + if (config == mmsys_config[i].config && id == mmsys_config[i].id)
> + break;
> +
> + if (i == mmsys->data->num_configs)
> + return;
> +
> + offset = mmsys_config[i].addr;
> + mask = mmsys_config[i].mask;
> + reg_val = val << mmsys_config[i].shift;
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_pkt && mmsys->cmdq_base.size) {
> + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> + mmsys->cmdq_base.offset + offset, reg_val,
> + mask);
> + } else {
> +#endif
> + u32 tmp = readl(mmsys->regs + offset);
> +
> + tmp = (tmp & ~mask) | reg_val;
> + writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + }
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> + if (ret)
> + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..084b1f5f3c88 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> u32 val;
> };
>
> +struct mtk_mmsys_config {
> + enum mtk_mmsys_config_type config;
> + u32 id;
> + u32 addr;
> + u32 mask;
> + u32 shift;
> +};
> +
> struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + const struct mtk_mmsys_config *config;
> + const unsigned int num_configs;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 338c71570aeb..ba3925661cc9 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
> #ifndef __MTK_MMSYS_H
> #define __MTK_MMSYS_H
>
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> enum mtk_ddp_comp_id;
> struct device;
>
> @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mmsys_config_type {
> + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_ALPHA_SEL,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> +
> #endif /* __MTK_MMSYS_H */
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-06 15:30 ` Matthias Brugger
0 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 15:30 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
On 22/07/2021 11:45, Nancy.Lin wrote:
> Add mmsys config API.
This patch is doing a lot of things, it adds a "config" and it adds cmdq
support. Please explain better in the commit message what the config is for.
Please add comments to the different values of struct mtk_mmsys_config.
I understand that cmdq is optional, so please make addition to cmdq a separate
patch.
I'm a bit puzzled about that fact, can you please explain who you get the HW to
behave the same way when you write the same value and offset to mmsys-regs and
via cmdq.
Thanks,
Matthias
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> 4 files changed, 116 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 104ba575f765..4bdb2087250c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,18 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9e31aad6c5c8..d0f4a407f8f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .clk_driver = "clk-mt8195-vdo1",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> + .config = mmsys_mt8195_config_table,
> + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> };
>
> @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
> + u32 reg_val;
> + u32 mask;
> + u32 offset;
> + int i;
> +
> + if (!mmsys->data->num_configs)
> + return;
> +
> + for (i = 0; i < mmsys->data->num_configs; i++)
> + if (config == mmsys_config[i].config && id == mmsys_config[i].id)
> + break;
> +
> + if (i == mmsys->data->num_configs)
> + return;
> +
> + offset = mmsys_config[i].addr;
> + mask = mmsys_config[i].mask;
> + reg_val = val << mmsys_config[i].shift;
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_pkt && mmsys->cmdq_base.size) {
> + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> + mmsys->cmdq_base.offset + offset, reg_val,
> + mask);
> + } else {
> +#endif
> + u32 tmp = readl(mmsys->regs + offset);
> +
> + tmp = (tmp & ~mask) | reg_val;
> + writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + }
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> + if (ret)
> + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..084b1f5f3c88 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> u32 val;
> };
>
> +struct mtk_mmsys_config {
> + enum mtk_mmsys_config_type config;
> + u32 id;
> + u32 addr;
> + u32 mask;
> + u32 shift;
> +};
> +
> struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + const struct mtk_mmsys_config *config;
> + const unsigned int num_configs;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 338c71570aeb..ba3925661cc9 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
> #ifndef __MTK_MMSYS_H
> #define __MTK_MMSYS_H
>
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> enum mtk_ddp_comp_id;
> struct device;
>
> @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mmsys_config_type {
> + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_ALPHA_SEL,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> +
> #endif /* __MTK_MMSYS_H */
>
_______________________________________________
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-06 15:30 ` Matthias Brugger
0 siblings, 0 replies; 99+ messages in thread
From: Matthias Brugger @ 2021-08-06 15:30 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
On 22/07/2021 11:45, Nancy.Lin wrote:
> Add mmsys config API.
This patch is doing a lot of things, it adds a "config" and it adds cmdq
support. Please explain better in the commit message what the config is for.
Please add comments to the different values of struct mtk_mmsys_config.
I understand that cmdq is optional, so please make addition to cmdq a separate
patch.
I'm a bit puzzled about that fact, can you please explain who you get the HW to
behave the same way when you write the same value and offset to mmsys-regs and
via cmdq.
Thanks,
Matthias
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> 4 files changed, 116 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 104ba575f765..4bdb2087250c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,18 @@
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
>
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
> + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9e31aad6c5c8..d0f4a407f8f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .clk_driver = "clk-mt8195-vdo1",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> + .config = mmsys_mt8195_config_table,
> + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> const struct mtk_mmsys_driver_data *data;
> };
>
> @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
> + u32 reg_val;
> + u32 mask;
> + u32 offset;
> + int i;
> +
> + if (!mmsys->data->num_configs)
> + return;
> +
> + for (i = 0; i < mmsys->data->num_configs; i++)
> + if (config == mmsys_config[i].config && id == mmsys_config[i].id)
> + break;
> +
> + if (i == mmsys->data->num_configs)
> + return;
> +
> + offset = mmsys_config[i].addr;
> + mask = mmsys_config[i].mask;
> + reg_val = val << mmsys_config[i].shift;
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_pkt && mmsys->cmdq_base.size) {
> + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> + mmsys->cmdq_base.offset + offset, reg_val,
> + mask);
> + } else {
> +#endif
> + u32 tmp = readl(mmsys->regs + offset);
> +
> + tmp = (tmp & ~mask) | reg_val;
> + writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + }
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> + if (ret)
> + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..084b1f5f3c88 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> u32 val;
> };
>
> +struct mtk_mmsys_config {
> + enum mtk_mmsys_config_type config;
> + u32 id;
> + u32 addr;
> + u32 mask;
> + u32 shift;
> +};
> +
> struct mtk_mmsys_driver_data {
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> + const struct mtk_mmsys_config *config;
> + const unsigned int num_configs;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 338c71570aeb..ba3925661cc9 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
> #ifndef __MTK_MMSYS_H
> #define __MTK_MMSYS_H
>
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> enum mtk_ddp_comp_id;
> struct device;
>
> @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mmsys_config_type {
> + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> + MMSYS_CONFIG_HDR_ALPHA_SEL,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> +
> #endif /* __MTK_MMSYS_H */
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-08-06 12:20 ` Matthias Brugger
(?)
@ 2021-08-16 2:05 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:05 UTC (permalink / raw)
To: Matthias Brugger, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote:
>
> On 28/07/2021 07:34, Nancy.Lin wrote:
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:45:
> > > >
> > > > Add mt8195 vdosys1 clock driver name and routing table to
> > > > the driver data of mtk-mmsys.
> > > >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > > > ++++++++++++++++++++++++--
> > > > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > > > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > > > 3 files changed, 90 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 73e9e8286d50..104ba575f765 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -64,16 +64,16 @@
> > > > #define
> > > > SOUT_TO_VPP_MERGE0_P1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE0 (0
> > > > << 0)
> > >
> > > This definition was introduced in this patch [1] that didn't land
> > > yet.
> > > And you're removing it now. Could you sync with Jason and only
> > > introduce the bits that are needed for your patches. Also all the
> > > comments I made to the Jason's patch apply here.
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
> > >
> > >
> >
> > OK, I will sync with Jason and modify it.
> >
> > > > +#define
> > > > SOUT_TO_MIXER_IN1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN2_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE0 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN3_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN4_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > > > #define
> > > > MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > > @@ -88,7 +88,7 @@
> > > > #define
> > > > MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > > > -#define
> > > > MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > > > << 0)
> > > > +#define
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > > > #define
> > > > MERGE4_SOUT_TO_VDOSYS0 (0
> > > > << 0)
> > > > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > > > mmsys_mt8195_routing_table[] = {
> > > > }, {
> > > > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > > > MT8195_VDO0_SEL_OUT,
> > > > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > > > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > > > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > > > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN2_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN3_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN4_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > > > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > > > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > > > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > > > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > > > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > > > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > > > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DPI1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > > > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DP_INTF0_SEL
> > > > }
> > > > };
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index 1fb241750897..9e31aad6c5c8 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys0_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > };
> > > >
> > > > +static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > + .clk_driver = "clk-mt8195-vdo1",
> > > > + .routes = mmsys_mt8195_routing_table,
> > > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > +};
> > > > +
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > @@ -168,6 +174,10 @@ static const struct of_device_id
> > > > of_match_mtk_mmsys[] = {
> > > > .compatible = "mediatek,mt8195-vdosys0",
> > > > .data = &mt8195_vdosys0_driver_data,
> > > > },
> > > > + {
> > > > + .compatible = "mediatek,mt8195-vdosys1",
> > >
> > > Why do you need a second compatible, isn't this the same IP
> > > block? I
> > > mean, I understand that you have 2 mmsys blocks, but both are the
> > > same
> > > IP block, right? or are they different?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > They(vdosys0 and vdosys1) are different IP block.
> >
>
> Please explain in what they are different. From what I see, you use
> the same
> routing table for both compatibles and only register another platform
> device for
> a second clock. Is that correct?
>
> Regards,
> Matthias
>
From a hardware point of view, the HW engines of vdosys0 and vdosys1
are different.
1. The components on meiatek-drm of vdosys0 are OVL0, RDMA0, COLOR0,
CCORR, AAL0, GAMMA, DITHER, DSC0, MERGE0, DP_INTF0. Its output panel is
eDP.
2. The components on meiatek-drm of vdosys1 are OVL_ADAPTOR, MERGE5,
DP_INTF1. Its output panel is DP.
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domains.
So I think it is more appropriate to use 2 compatibles to identify
which mmsys represents the pipeline. Another reason for using two
compatibles is that we use different driver
data in mtk-mmsys.c and mtk_drm_drv.c to identify the corresponding
mmsys is vdosys0 or vdosys1.
Their driver data in mtk_drm_drv.c is defined here:
[v7,13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210815145610.2050-14-jason-jh.lin@mediatek.com/
[v2,14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-15-nancy.lin@mediatek.com/
There is another series talking about the two mmsys compatible.
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh.lin@mediatek.com/
Regards,
Nancy
> > > > + .data = &mt8195_vdosys1_driver_data,
> > > > + },
> > > > { }
> > > > };
> > > >
> > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > index 34cb605e5df9..338c71570aeb 100644
> > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > > > DDP_COMPONENT_DSC1,
> > > > DDP_COMPONENT_DSC1_VIRTUAL0,
> > > > DDP_COMPONENT_DP_INTF0,
> > > > + DDP_COMPONENT_DP_INTF1,
> > > > + DDP_COMPONENT_PSEUDO_OVL,
> > > > DDP_COMPONENT_ID_MAX,
> > > > };
> > > >
> > > > --
> > > > 2.18.0
> > > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-16 2:05 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:05 UTC (permalink / raw)
To: Matthias Brugger, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote:
>
> On 28/07/2021 07:34, Nancy.Lin wrote:
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:45:
> > > >
> > > > Add mt8195 vdosys1 clock driver name and routing table to
> > > > the driver data of mtk-mmsys.
> > > >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > > > ++++++++++++++++++++++++--
> > > > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > > > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > > > 3 files changed, 90 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 73e9e8286d50..104ba575f765 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -64,16 +64,16 @@
> > > > #define
> > > > SOUT_TO_VPP_MERGE0_P1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE0 (0
> > > > << 0)
> > >
> > > This definition was introduced in this patch [1] that didn't land
> > > yet.
> > > And you're removing it now. Could you sync with Jason and only
> > > introduce the bits that are needed for your patches. Also all the
> > > comments I made to the Jason's patch apply here.
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
> > >
> > >
> >
> > OK, I will sync with Jason and modify it.
> >
> > > > +#define
> > > > SOUT_TO_MIXER_IN1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN2_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE0 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN3_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN4_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > > > #define
> > > > MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > > @@ -88,7 +88,7 @@
> > > > #define
> > > > MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > > > -#define
> > > > MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > > > << 0)
> > > > +#define
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > > > #define
> > > > MERGE4_SOUT_TO_VDOSYS0 (0
> > > > << 0)
> > > > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > > > mmsys_mt8195_routing_table[] = {
> > > > }, {
> > > > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > > > MT8195_VDO0_SEL_OUT,
> > > > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > > > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > > > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > > > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN2_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN3_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN4_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > > > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > > > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > > > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > > > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > > > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > > > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > > > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DPI1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > > > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DP_INTF0_SEL
> > > > }
> > > > };
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index 1fb241750897..9e31aad6c5c8 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys0_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > };
> > > >
> > > > +static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > + .clk_driver = "clk-mt8195-vdo1",
> > > > + .routes = mmsys_mt8195_routing_table,
> > > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > +};
> > > > +
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > @@ -168,6 +174,10 @@ static const struct of_device_id
> > > > of_match_mtk_mmsys[] = {
> > > > .compatible = "mediatek,mt8195-vdosys0",
> > > > .data = &mt8195_vdosys0_driver_data,
> > > > },
> > > > + {
> > > > + .compatible = "mediatek,mt8195-vdosys1",
> > >
> > > Why do you need a second compatible, isn't this the same IP
> > > block? I
> > > mean, I understand that you have 2 mmsys blocks, but both are the
> > > same
> > > IP block, right? or are they different?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > They(vdosys0 and vdosys1) are different IP block.
> >
>
> Please explain in what they are different. From what I see, you use
> the same
> routing table for both compatibles and only register another platform
> device for
> a second clock. Is that correct?
>
> Regards,
> Matthias
>
From a hardware point of view, the HW engines of vdosys0 and vdosys1
are different.
1. The components on meiatek-drm of vdosys0 are OVL0, RDMA0, COLOR0,
CCORR, AAL0, GAMMA, DITHER, DSC0, MERGE0, DP_INTF0. Its output panel is
eDP.
2. The components on meiatek-drm of vdosys1 are OVL_ADAPTOR, MERGE5,
DP_INTF1. Its output panel is DP.
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domains.
So I think it is more appropriate to use 2 compatibles to identify
which mmsys represents the pipeline. Another reason for using two
compatibles is that we use different driver
data in mtk-mmsys.c and mtk_drm_drv.c to identify the corresponding
mmsys is vdosys0 or vdosys1.
Their driver data in mtk_drm_drv.c is defined here:
[v7,13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210815145610.2050-14-jason-jh.lin@mediatek.com/
[v2,14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-15-nancy.lin@mediatek.com/
There is another series talking about the two mmsys compatible.
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh.lin@mediatek.com/
Regards,
Nancy
> > > > + .data = &mt8195_vdosys1_driver_data,
> > > > + },
> > > > { }
> > > > };
> > > >
> > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > index 34cb605e5df9..338c71570aeb 100644
> > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > > > DDP_COMPONENT_DSC1,
> > > > DDP_COMPONENT_DSC1_VIRTUAL0,
> > > > DDP_COMPONENT_DP_INTF0,
> > > > + DDP_COMPONENT_DP_INTF1,
> > > > + DDP_COMPONENT_PSEUDO_OVL,
> > > > DDP_COMPONENT_ID_MAX,
> > > > };
> > > >
> > > > --
> > > > 2.18.0
> > > >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-08-16 2:05 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:05 UTC (permalink / raw)
To: Matthias Brugger, Enric Balletbo Serra
Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote:
>
> On 28/07/2021 07:34, Nancy.Lin wrote:
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you for your patch.
> > >
> > > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > > jul.
> > > 2021 a les 11:45:
> > > >
> > > > Add mt8195 vdosys1 clock driver name and routing table to
> > > > the driver data of mtk-mmsys.
> > > >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > ---
> > > > drivers/soc/mediatek/mt8195-mmsys.h | 83
> > > > ++++++++++++++++++++++++--
> > > > drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
> > > > include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> > > > 3 files changed, 90 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > index 73e9e8286d50..104ba575f765 100644
> > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > @@ -64,16 +64,16 @@
> > > > #define
> > > > SOUT_TO_VPP_MERGE0_P1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE0 (0
> > > > << 0)
> > >
> > > This definition was introduced in this patch [1] that didn't land
> > > yet.
> > > And you're removing it now. Could you sync with Jason and only
> > > introduce the bits that are needed for your patches. Also all the
> > > comments I made to the Jason's patch apply here.
> > >
> > > [1]
> > >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$
> > >
> > >
> >
> > OK, I will sync with Jason and modify it.
> >
> > > > +#define
> > > > SOUT_TO_MIXER_IN1_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > > > -#define
> > > > SOUT_TO_HDR_VDO_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN2_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE0 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN3_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > > > -#define
> > > > SOUT_TO_HDR_GFX_FE1 (0
> > > > << 0)
> > > > +#define
> > > > SOUT_TO_MIXER_IN4_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> > > > #define
> > > > MIXER_IN1_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > > @@ -88,7 +88,7 @@
> > > > #define
> > > > MIXER_IN4_SOUT_TO_DISP_MIXER (0
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> > > > -#define
> > > > MIXER_SOUT_TO_HDR_VDO_BE0 (0
> > > > << 0)
> > > > +#define
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1
> > > > << 0)
> > > >
> > > > #define
> > > > MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> > > > #define
> > > > MERGE4_SOUT_TO_VDOSYS0 (0
> > > > << 0)
> > > > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes
> > > > mmsys_mt8195_routing_table[] = {
> > > > }, {
> > > > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > > > MT8195_VDO0_SEL_OUT,
> > > > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN,
> > > > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN,
> > > > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN,
> > > > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN2_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN3_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL,
> > > > SOUT_TO_MIXER_IN4_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_OUT_SOUT_SEL,
> > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN1_SEL_IN,
> > > > MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN2_SEL_IN,
> > > > MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN3_SEL_IN,
> > > > MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_IN4_SEL_IN,
> > > > MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MIXER_SOUT_SEL_IN,
> > > > MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5,
> > > > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN,
> > > > MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_DISP_DPI1_SEL_IN,
> > > > DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DPI1_SEL
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
> > > > + DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > > > + },
> > > > + {
> > > > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > > > + MT8195_VDO1_MERGE4_SOUT_SEL,
> > > > MERGE4_SOUT_TO_DP_INTF0_SEL
> > > > }
> > > > };
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index 1fb241750897..9e31aad6c5c8 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys0_driver_data = {
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > };
> > > >
> > > > +static const struct mtk_mmsys_driver_data
> > > > mt8195_vdosys1_driver_data = {
> > > > + .clk_driver = "clk-mt8195-vdo1",
> > > > + .routes = mmsys_mt8195_routing_table,
> > > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > > +};
> > > > +
> > > > struct mtk_mmsys {
> > > > void __iomem *regs;
> > > > const struct mtk_mmsys_driver_data *data;
> > > > @@ -168,6 +174,10 @@ static const struct of_device_id
> > > > of_match_mtk_mmsys[] = {
> > > > .compatible = "mediatek,mt8195-vdosys0",
> > > > .data = &mt8195_vdosys0_driver_data,
> > > > },
> > > > + {
> > > > + .compatible = "mediatek,mt8195-vdosys1",
> > >
> > > Why do you need a second compatible, isn't this the same IP
> > > block? I
> > > mean, I understand that you have 2 mmsys blocks, but both are the
> > > same
> > > IP block, right? or are they different?
> > >
> > > Thanks,
> > > Enric
> > >
> >
> > They(vdosys0 and vdosys1) are different IP block.
> >
>
> Please explain in what they are different. From what I see, you use
> the same
> routing table for both compatibles and only register another platform
> device for
> a second clock. Is that correct?
>
> Regards,
> Matthias
>
From a hardware point of view, the HW engines of vdosys0 and vdosys1
are different.
1. The components on meiatek-drm of vdosys0 are OVL0, RDMA0, COLOR0,
CCORR, AAL0, GAMMA, DITHER, DSC0, MERGE0, DP_INTF0. Its output panel is
eDP.
2. The components on meiatek-drm of vdosys1 are OVL_ADAPTOR, MERGE5,
DP_INTF1. Its output panel is DP.
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domains.
So I think it is more appropriate to use 2 compatibles to identify
which mmsys represents the pipeline. Another reason for using two
compatibles is that we use different driver
data in mtk-mmsys.c and mtk_drm_drv.c to identify the corresponding
mmsys is vdosys0 or vdosys1.
Their driver data in mtk_drm_drv.c is defined here:
[v7,13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210815145610.2050-14-jason-jh.lin@mediatek.com/
[v2,14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-15-nancy.lin@mediatek.com/
There is another series talking about the two mmsys compatible.
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh.lin@mediatek.com/
Regards,
Nancy
> > > > + .data = &mt8195_vdosys1_driver_data,
> > > > + },
> > > > { }
> > > > };
> > > >
> > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > index 34cb605e5df9..338c71570aeb 100644
> > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > > @@ -49,6 +49,8 @@ enum mtk_ddp_comp_id {
> > > > DDP_COMPONENT_DSC1,
> > > > DDP_COMPONENT_DSC1_VIRTUAL0,
> > > > DDP_COMPONENT_DP_INTF0,
> > > > + DDP_COMPONENT_DP_INTF1,
> > > > + DDP_COMPONENT_PSEUDO_OVL,
> > > > DDP_COMPONENT_ID_MAX,
> > > > };
> > > >
> > > > --
> > > > 2.18.0
> > > >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2021-08-06 15:30 ` Matthias Brugger
(?)
@ 2021-08-16 2:59 ` Nancy.Lin
-1 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:59 UTC (permalink / raw)
To: Matthias Brugger, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 17:30 +0200, Matthias Brugger wrote:
>
> On 22/07/2021 11:45, Nancy.Lin wrote:
> > Add mmsys config API.
>
> This patch is doing a lot of things, it adds a "config" and it adds
> cmdq
> support. Please explain better in the commit message what the config
> is for.
> Please add comments to the different values of struct
> mtk_mmsys_config.
>
OK, I will explain in more detail in the commit message.
> I understand that cmdq is optional, so please make addition to cmdq a
> separate
> patch.
OK, I will add cmdq support in another patch.
> I'm a bit puzzled about that fact, can you please explain who you get
> the HW to
> behave the same way when you write the same value and offset to
> mmsys-regs and
> via cmdq.
>
> Thanks,
> Matthias
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet.
The first command in the packet is "wait stream done", and then
following with all the HW settings. After the cmdq packet is flush to
GCE HW.
The GCE waits for the "stream done event" to coming and then starts
flushing all the HW settings. This can guarantee all the settings flush
in the same vblanking.
Regards,
Nancy
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 50
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> > 4 files changed, 116 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 104ba575f765..4bdb2087250c 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,18 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 <<
> > 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 <<
> > 0)
> >
> > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> > +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> > +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> > +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> > +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> > +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> > +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> > +
> > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > {
> > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }
> > };
> >
> > +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] =
> > {
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD,
> > GENMASK(4, 4), 4},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(20, 20), 20},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(21, 21), 21},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(22, 22), 22},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(23, 23), 23},
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9e31aad6c5c8..d0f4a407f8f8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .clk_driver = "clk-mt8195-vdo1",
> > .routes = mmsys_mt8195_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > + .config = mmsys_mt8195_config_table,
> > + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > };
> >
> > @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_config *mmsys_config = mmsys->data-
> > >config;
> > + u32 reg_val;
> > + u32 mask;
> > + u32 offset;
> > + int i;
> > +
> > + if (!mmsys->data->num_configs)
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_configs; i++)
> > + if (config == mmsys_config[i].config && id ==
> > mmsys_config[i].id)
> > + break;
> > +
> > + if (i == mmsys->data->num_configs)
> > + return;
> > +
> > + offset = mmsys_config[i].addr;
> > + mask = mmsys_config[i].mask;
> > + reg_val = val << mmsys_config[i].shift;
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_pkt && mmsys->cmdq_base.size) {
> > + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> > + mmsys->cmdq_base.offset + offset,
> > reg_val,
> > + mask);
> > + } else {
> > +#endif
> > + u32 tmp = readl(mmsys->regs + offset);
> > +
> > + tmp = (tmp & ~mask) | reg_val;
> > + writel(tmp, mmsys->regs + offset);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + }
> > +#endif
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> > + if (ret)
> > + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > +#endif
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index a760a34e6eca..084b1f5f3c88 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> > u32 val;
> > };
> >
> > +struct mtk_mmsys_config {
> > + enum mtk_mmsys_config_type config;
> > + u32 id;
> > + u32 addr;
> > + u32 mask;
> > + u32 shift;
> > +};
> > +
> > struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + const struct mtk_mmsys_config *config;
> > + const unsigned int num_configs;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 338c71570aeb..ba3925661cc9 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -6,6 +6,10 @@
> > #ifndef __MTK_MMSYS_H
> > #define __MTK_MMSYS_H
> >
> > +#include <linux/mailbox_controller.h>
> > +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > enum mtk_ddp_comp_id;
> > struct device;
> >
> > @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mmsys_config_type {
> > + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> > + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> > +
> > #endif /* __MTK_MMSYS_H */
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-16 2:59 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:59 UTC (permalink / raw)
To: Matthias Brugger, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 17:30 +0200, Matthias Brugger wrote:
>
> On 22/07/2021 11:45, Nancy.Lin wrote:
> > Add mmsys config API.
>
> This patch is doing a lot of things, it adds a "config" and it adds
> cmdq
> support. Please explain better in the commit message what the config
> is for.
> Please add comments to the different values of struct
> mtk_mmsys_config.
>
OK, I will explain in more detail in the commit message.
> I understand that cmdq is optional, so please make addition to cmdq a
> separate
> patch.
OK, I will add cmdq support in another patch.
> I'm a bit puzzled about that fact, can you please explain who you get
> the HW to
> behave the same way when you write the same value and offset to
> mmsys-regs and
> via cmdq.
>
> Thanks,
> Matthias
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet.
The first command in the packet is "wait stream done", and then
following with all the HW settings. After the cmdq packet is flush to
GCE HW.
The GCE waits for the "stream done event" to coming and then starts
flushing all the HW settings. This can guarantee all the settings flush
in the same vblanking.
Regards,
Nancy
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 50
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> > 4 files changed, 116 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 104ba575f765..4bdb2087250c 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,18 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 <<
> > 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 <<
> > 0)
> >
> > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> > +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> > +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> > +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> > +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> > +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> > +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> > +
> > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > {
> > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }
> > };
> >
> > +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] =
> > {
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD,
> > GENMASK(4, 4), 4},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(20, 20), 20},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(21, 21), 21},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(22, 22), 22},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(23, 23), 23},
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9e31aad6c5c8..d0f4a407f8f8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .clk_driver = "clk-mt8195-vdo1",
> > .routes = mmsys_mt8195_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > + .config = mmsys_mt8195_config_table,
> > + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > };
> >
> > @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_config *mmsys_config = mmsys->data-
> > >config;
> > + u32 reg_val;
> > + u32 mask;
> > + u32 offset;
> > + int i;
> > +
> > + if (!mmsys->data->num_configs)
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_configs; i++)
> > + if (config == mmsys_config[i].config && id ==
> > mmsys_config[i].id)
> > + break;
> > +
> > + if (i == mmsys->data->num_configs)
> > + return;
> > +
> > + offset = mmsys_config[i].addr;
> > + mask = mmsys_config[i].mask;
> > + reg_val = val << mmsys_config[i].shift;
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_pkt && mmsys->cmdq_base.size) {
> > + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> > + mmsys->cmdq_base.offset + offset,
> > reg_val,
> > + mask);
> > + } else {
> > +#endif
> > + u32 tmp = readl(mmsys->regs + offset);
> > +
> > + tmp = (tmp & ~mask) | reg_val;
> > + writel(tmp, mmsys->regs + offset);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + }
> > +#endif
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> > + if (ret)
> > + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > +#endif
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index a760a34e6eca..084b1f5f3c88 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> > u32 val;
> > };
> >
> > +struct mtk_mmsys_config {
> > + enum mtk_mmsys_config_type config;
> > + u32 id;
> > + u32 addr;
> > + u32 mask;
> > + u32 shift;
> > +};
> > +
> > struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + const struct mtk_mmsys_config *config;
> > + const unsigned int num_configs;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 338c71570aeb..ba3925661cc9 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -6,6 +6,10 @@
> > #ifndef __MTK_MMSYS_H
> > #define __MTK_MMSYS_H
> >
> > +#include <linux/mailbox_controller.h>
> > +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > enum mtk_ddp_comp_id;
> > struct device;
> >
> > @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mmsys_config_type {
> > + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> > + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> > +
> > #endif /* __MTK_MMSYS_H */
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-08-16 2:59 ` Nancy.Lin
0 siblings, 0 replies; 99+ messages in thread
From: Nancy.Lin @ 2021-08-16 2:59 UTC (permalink / raw)
To: Matthias Brugger, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
singo.chang, srv_heupstream
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 17:30 +0200, Matthias Brugger wrote:
>
> On 22/07/2021 11:45, Nancy.Lin wrote:
> > Add mmsys config API.
>
> This patch is doing a lot of things, it adds a "config" and it adds
> cmdq
> support. Please explain better in the commit message what the config
> is for.
> Please add comments to the different values of struct
> mtk_mmsys_config.
>
OK, I will explain in more detail in the commit message.
> I understand that cmdq is optional, so please make addition to cmdq a
> separate
> patch.
OK, I will add cmdq support in another patch.
> I'm a bit puzzled about that fact, can you please explain who you get
> the HW to
> behave the same way when you write the same value and offset to
> mmsys-regs and
> via cmdq.
>
> Thanks,
> Matthias
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet.
The first command in the packet is "wait stream done", and then
following with all the HW settings. After the cmdq packet is flush to
GCE HW.
The GCE waits for the "stream done event" to coming and then starts
flushing all the HW settings. This can guarantee all the settings flush
in the same vblanking.
Regards,
Nancy
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 38 ++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 50
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 10 ++++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
> > 4 files changed, 116 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 104ba575f765..4bdb2087250c 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -154,6 +154,18 @@
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 <<
> > 0)
> > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 <<
> > 0)
> >
> > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> > +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> > +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> > +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
> > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> > +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> > +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> > +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
> > +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
> > +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
> > +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
> > +
> > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > {
> > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > }
> > };
> >
> > +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] =
> > {
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1,
> > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2,
> > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3,
> > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> > + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1,
> > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2,
> > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3,
> > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4,
> > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> > + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD,
> > GENMASK(4, 4), 4},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(20, 20), 20},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(21, 21), 21},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(22, 22), 22},
> > + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG,
> > GENMASK(23, 23), 23},
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9e31aad6c5c8..d0f4a407f8f8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > .clk_driver = "clk-mt8195-vdo1",
> > .routes = mmsys_mt8195_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > + .config = mmsys_mt8195_config_table,
> > + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > const struct mtk_mmsys_driver_data *data;
> > };
> >
> > @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_config *mmsys_config = mmsys->data-
> > >config;
> > + u32 reg_val;
> > + u32 mask;
> > + u32 offset;
> > + int i;
> > +
> > + if (!mmsys->data->num_configs)
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_configs; i++)
> > + if (config == mmsys_config[i].config && id ==
> > mmsys_config[i].id)
> > + break;
> > +
> > + if (i == mmsys->data->num_configs)
> > + return;
> > +
> > + offset = mmsys_config[i].addr;
> > + mask = mmsys_config[i].mask;
> > + reg_val = val << mmsys_config[i].shift;
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_pkt && mmsys->cmdq_base.size) {
> > + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> > + mmsys->cmdq_base.offset + offset,
> > reg_val,
> > + mask);
> > + } else {
> > +#endif
> > + u32 tmp = readl(mmsys->regs + offset);
> > +
> > + tmp = (tmp & ~mask) | reg_val;
> > + writel(tmp, mmsys->regs + offset);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + }
> > +#endif
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> > + if (ret)
> > + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > +#endif
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index a760a34e6eca..084b1f5f3c88 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
> > u32 val;
> > };
> >
> > +struct mtk_mmsys_config {
> > + enum mtk_mmsys_config_type config;
> > + u32 id;
> > + u32 addr;
> > + u32 mask;
> > + u32 shift;
> > +};
> > +
> > struct mtk_mmsys_driver_data {
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > + const struct mtk_mmsys_config *config;
> > + const unsigned int num_configs;
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 338c71570aeb..ba3925661cc9 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -6,6 +6,10 @@
> > #ifndef __MTK_MMSYS_H
> > #define __MTK_MMSYS_H
> >
> > +#include <linux/mailbox_controller.h>
> > +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > enum mtk_ddp_comp_id;
> > struct device;
> >
> > @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mmsys_config_type {
> > + MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> > + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> > + MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> > + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> > + MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_ddp_config(struct device *dev, enum
> > mtk_mmsys_config_type config,
> > + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> > +
> > #endif /* __MTK_MMSYS_H */
> >
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^ permalink raw reply [flat|nested] 99+ messages in thread
end of thread, other threads:[~2021-08-16 3:02 UTC | newest]
Thread overview: 99+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-22 9:45 [PATCH v2 00/14] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 01/14] dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition " Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 02/14] dt-bindings: mediatek: add ethdr " Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 03/14] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-23 11:10 ` Enric Balletbo Serra
2021-07-23 11:10 ` Enric Balletbo Serra
2021-07-23 11:10 ` Enric Balletbo Serra
2021-07-23 11:10 ` Enric Balletbo Serra
2021-07-28 5:21 ` Nancy.Lin
2021-07-28 5:21 ` Nancy.Lin
2021-07-28 5:21 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 05/14] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 06/14] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-23 11:05 ` Enric Balletbo Serra
2021-07-23 11:05 ` Enric Balletbo Serra
2021-07-23 11:05 ` Enric Balletbo Serra
2021-07-28 5:34 ` Nancy.Lin
2021-07-28 5:34 ` Nancy.Lin
2021-07-28 5:34 ` Nancy.Lin
2021-08-06 12:20 ` Matthias Brugger
2021-08-06 12:20 ` Matthias Brugger
2021-08-06 12:20 ` Matthias Brugger
2021-08-16 2:05 ` Nancy.Lin
2021-08-16 2:05 ` Nancy.Lin
2021-08-16 2:05 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-08-06 15:30 ` Matthias Brugger
2021-08-06 15:30 ` Matthias Brugger
2021-08-06 15:30 ` Matthias Brugger
2021-08-16 2:59 ` Nancy.Lin
2021-08-16 2:59 ` Nancy.Lin
2021-08-16 2:59 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-23 10:57 ` Enric Balletbo Serra
2021-07-23 10:57 ` Enric Balletbo Serra
2021-07-23 10:57 ` Enric Balletbo Serra
2021-07-23 10:57 ` Enric Balletbo Serra
2021-07-28 6:00 ` Nancy.Lin
2021-07-28 6:00 ` Nancy.Lin
2021-07-28 6:00 ` Nancy.Lin
2021-07-28 10:31 ` Enric Balletbo Serra
2021-07-28 10:31 ` Enric Balletbo Serra
2021-07-28 10:31 ` Enric Balletbo Serra
2021-07-28 10:31 ` Enric Balletbo Serra
2021-07-30 3:47 ` Nancy.Lin
2021-07-30 3:47 ` Nancy.Lin
2021-07-30 3:47 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 10/14] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 11/14] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH 13/14] drm/mediatek: add pseudo ovl support for MT8195 Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-25 1:57 ` Chun-Kuang Hu
2021-07-25 1:57 ` Chun-Kuang Hu
2021-07-25 1:57 ` Chun-Kuang Hu
2021-07-30 3:28 ` Nancy.Lin
2021-07-30 3:28 ` Nancy.Lin
2021-07-30 3:28 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 13/14] drm/mediatek: add ETHDR " Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-27 23:39 ` Chun-Kuang Hu
2021-07-27 23:39 ` Chun-Kuang Hu
2021-07-27 23:39 ` Chun-Kuang Hu
2021-07-29 5:28 ` Nancy.Lin
2021-07-29 5:28 ` Nancy.Lin
2021-07-29 5:28 ` Nancy.Lin
2021-07-22 9:45 ` [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 " Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-07-22 9:45 ` Nancy.Lin
2021-08-02 3:34 ` CK Hu
2021-08-02 3:34 ` CK Hu
2021-08-02 3:34 ` CK Hu
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