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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thu Jul 22, 2021 at 01:17:13PM -0400, Andrey Grodzovsky wrote: > = > On 2021-07-22 12:47 p.m., Jingwen Chen wrote: > > On Thu Jul 22, 2021 at 06:24:28PM +0200, Christian K=F6nig wrote: > > > Am 22.07.21 um 16:45 schrieb Andrey Grodzovsky: > > > > On 2021-07-22 6:45 a.m., Jingwen Chen wrote: > > > > > On Wed Jul 21, 2021 at 12:53:51PM -0400, Andrey Grodzovsky wrote: > > > > > > On 2021-07-20 11:13 p.m., Jingwen Chen wrote: > > > > > > > [Why] > > > > > > > After embeded hw_fence to amdgpu_job, we need to add tdr supp= ort > > > > > > > for this feature. > > > > > > > = > > > > > > > [How] > > > > > > > 1. Add a resubmit_flag for resubmit jobs. > > > > > > > 2. Clear job fence from RCU and force complete vm flush fence= s in > > > > > > > =A0=A0=A0=A0 pre_asic_reset > > > > > > > 3. skip dma_fence_get for resubmit jobs and add a dma_fence_p= ut > > > > > > > =A0=A0=A0=A0 for guilty jobs. > > > > > > > = > > > > > > > Signed-off-by: Jack Zhang > > > > > > > Signed-off-by: Jingwen Chen > > > > > > > --- > > > > > > > =A0=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++++= ++++++- > > > > > > > =A0=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c=A0 | 16 +++= ++++++++----- > > > > > > > =A0=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c=A0=A0=A0 |=A0= 4 +++- > > > > > > > =A0=A0 drivers/gpu/drm/scheduler/sched_main.c=A0=A0=A0=A0 |= =A0 1 + > > > > > > > =A0=A0 include/drm/gpu_scheduler.h=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0 |=A0 1 + > > > > > > > =A0=A0 5 files changed, 27 insertions(+), 7 deletions(-) > > > > > > > = > > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > > > > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > > > > > > index 40461547701a..fe0237f72a09 100644 > > > > > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > > > > > > @@ -4382,7 +4382,7 @@ int amdgpu_device_mode1_reset(struct > > > > > > > amdgpu_device *adev) > > > > > > > =A0=A0 int amdgpu_device_pre_asic_reset(struct amdgpu_device= *adev, > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 st= ruct amdgpu_reset_context *reset_context) > > > > > > > =A0=A0 { > > > > > > > -=A0=A0=A0 int i, r =3D 0; > > > > > > > +=A0=A0=A0 int i, j, r =3D 0; > > > > > > > =A0=A0=A0=A0=A0=A0 struct amdgpu_job *job =3D NULL; > > > > > > > =A0=A0=A0=A0=A0=A0 bool need_full_reset =3D > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 test_bit(AMDGPU_NEED_FULL_RES= ET, &reset_context->flags); > > > > > > > @@ -4406,6 +4406,16 @@ int > > > > > > > amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (!ring || !ring->sched.thr= ead) > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 continue; > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 /*clear job fence from fence drv to av= oid force_completion > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0 *leave NULL and vm flush fence in f= ence drv */ > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 for (j =3D 0; j <=3D ring->fence_drv.n= um_fences_mask; j ++) { > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct dma_fence *old,**pt= r; > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ptr =3D &ring->fence_drv.f= ences[j]; > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 old =3D rcu_dereference_pr= otected(*ptr, 1); > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (old && test_bit(DMA_FE= NCE_FLAG_USER_BITS, > > > > > > > &old->flags))) { > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 RCU_INIT_POINT= ER(*ptr, NULL); > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 } > > > > > > Is this to avoid premature job free because of dma_fence_put in= side > > > > > > amdgpu_fence_process ? > > > > > > I can't currently remember why but we probably want all the HW = fences > > > > > > currently in the ring to > > > > > > be forced signaled - maybe better to test for DMA_FENCE_FLAG_US= ER_BITS > > > > > > inside amdgpu_fence_process > > > > > > and still do the signaling but not the dma_fence_put part > > > > > > = > > > > > > Andrey > > > > > Hi Andrey, > > > > > = > > > > > This is to avoid signaling the same fence twice. If we still do t= he > > > > > signaling, then the job in the pending list will be signaled firs= t in > > > > > force_completion, and later be signaled in resubmit. This will go= to > > > > > BUG() in amdgpu_fence_process. > > > > = > > > > Oh, i see, how about just adding 'skip' flag to amdgpu_ring and set= ting > > > > it before calling > > > > amdgpu_fence_driver_force_completion and resetting it after, then i= nside > > > > amdgpu_fence_driver_force_completion > > > > you can just skip the signaling part with this flag for fences with > > > > DMA_FENCE_FLAG_USER_BITS set > > > > Less lines of code at least. > > > Still sounds quite a bit hacky. > > > = > > > I would rather suggest to completely drop the approach with > > > amdgpu_fence_driver_force_completion(). I could never see why we woul= d want > > > that in the first place. > > > = > > > Regards, > > > Christian. > > > = > > Hi Christian, > > = > > I keep the amdgpu_fence_driver_force_completion here to make sure the vm > > flush fence is signaled and put. > = > = > Right, so we need to do force completion for the sake of all the fences > without parent jobs since there is code which wait directly on them. > = > = > > So the key question is whether the fence of ib test should be the first > > fence to be signaled after reset. > = > = > What do you mean by 'after reset' - at this point in the code there was > no ASIC reset yet, we just stopped the schedulers and detached the > HW fences from their parent jobs (sched_fence) I mean the ASIC reset. There will be a ib_test for each ring after ASIC reset. > = > = > > If it should be, it means not only fences with DMA_FENCE_FLAG_USER_BITS > > but also vm flush fences should be removed from RCU fence array before > > ib_test. > = > = > Which ib_test is it, the one after ASIC reset ? > = Yes Best Regards, JingWen Chen > Andrey > = > > Then we must do the force_completion here for vm flush > > fence, otherwise there will be a memory leak here as no one will signal > > and put it after we remove it from RCU. > > If not, then the first fence to signal could be vm flush fence. And I'm > > OK with drop amdgpu_fence_driver_force_completion here. > > = > > = > > Best Regards, > > JingWen Chen > > > > Andrey > > > > = > > > > = > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 } > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* after all hw jobs are rese= t, hw fence is > > > > > > > meaningless, so force_completion */ > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 amdgpu_fence_driver_force_com= pletion(ring); > > > > > > > =A0=A0=A0=A0=A0=A0 } > > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c > > > > > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c > > > > > > > index eecf21d8ec33..815776c9a013 100644 > > > > > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c > > > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c > > > > > > > @@ -156,11 +156,17 @@ int amdgpu_fence_emit(struct > > > > > > > amdgpu_ring *ring, struct dma_fence **f, struct amd > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 job->ring =3D ring; > > > > > > > =A0=A0=A0=A0=A0=A0 } > > > > > > > -=A0=A0=A0 seq =3D ++ring->fence_drv.sync_seq; > > > > > > > -=A0=A0=A0 dma_fence_init(fence, &amdgpu_fence_ops, > > > > > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 &ring->fence_drv.= lock, > > > > > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 adev->fence_conte= xt + ring->idx, > > > > > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 seq); > > > > > > > +=A0=A0=A0 if (job !=3D NULL && job->base.resubmit_flag =3D= =3D 1) { > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 /* reinit seq for resubmitted jobs */ > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 seq =3D ++ring->fence_drv.sync_seq; > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 fence->seqno =3D seq; > > > > > > > +=A0=A0=A0 } else { > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 seq =3D ++ring->fence_drv.sync_seq; > > > > > > Seems like you could do the above line only once above if-else > > > > > > as it was > > > > > > before > > > > > Sure, I will modify this. > > > > > = > > > > > = > > > > > Best Regards, > > > > > JingWen Chen > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 dma_fence_init(fence, &amdgpu_fence_op= s, > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 &ring->fence_d= rv.lock, > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 adev->fence_co= ntext + ring->idx, > > > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 seq); > > > > > > > +=A0=A0=A0 } > > > > > > > =A0=A0=A0=A0=A0=A0 if (job !=3D NULL) { > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* mark this fence has a pare= nt job */ > > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c > > > > > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c > > > > > > > index 7c426e225b24..d6f848adc3f4 100644 > > > > > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c > > > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c > > > > > > > @@ -241,6 +241,7 @@ static struct dma_fence > > > > > > > *amdgpu_job_run(struct drm_sched_job *sched_job) > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 dma_fence_set_error(finished,= -ECANCELED);/* skip > > > > > > > IB as well if VRAM lost */ > > > > > > > =A0=A0=A0=A0=A0=A0 if (finished->error < 0) { > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 dma_fence_put(&job->hw_fence); > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 DRM_INFO("Skip scheduling IBs= !\n"); > > > > > > > =A0=A0=A0=A0=A0=A0 } else { > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 r =3D amdgpu_ib_schedule(ring= , job->num_ibs, job->ibs, job, > > > > > > > @@ -249,7 +250,8 @@ static struct dma_fence > > > > > > > *amdgpu_job_run(struct drm_sched_job *sched_job) > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 DRM_ERROR("Error = scheduling IBs (%d)\n", r); > > > > > > > =A0=A0=A0=A0=A0=A0 } > > > > > > > -=A0=A0=A0 dma_fence_get(fence); > > > > > > > +=A0=A0=A0 if (!job->base.resubmit_flag) > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 dma_fence_get(fence); > > > > > > > =A0=A0=A0=A0=A0=A0 amdgpu_job_free_resources(job); > > > > > > > =A0=A0=A0=A0=A0=A0 fence =3D r ? ERR_PTR(r) : fence; > > > > > > > diff --git a/drivers/gpu/drm/scheduler/sched_main.c > > > > > > > b/drivers/gpu/drm/scheduler/sched_main.c > > > > > > > index f4f474944169..5a36ab5aea2d 100644 > > > > > > > --- a/drivers/gpu/drm/scheduler/sched_main.c > > > > > > > +++ b/drivers/gpu/drm/scheduler/sched_main.c > > > > > > > @@ -544,6 +544,7 @@ void drm_sched_resubmit_jobs_ext(struct > > > > > > > drm_gpu_scheduler *sched, int max) > > > > > > > dma_fence_set_error(&s_fence->finished, -ECANCELED); > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 dma_fence_put(s_job->s_fence-= >parent); > > > > > > > +=A0=A0=A0=A0=A0=A0=A0 s_job->resubmit_flag =3D 1; > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 fence =3D sched->ops->run_job= (s_job); > > > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 i++; > > > > > > > diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_sc= heduler.h > > > > > > > index 4ea8606d91fe..06c101af1f71 100644 > > > > > > > --- a/include/drm/gpu_scheduler.h > > > > > > > +++ b/include/drm/gpu_scheduler.h > > > > > > > @@ -198,6 +198,7 @@ struct drm_sched_job { > > > > > > > =A0=A0=A0=A0=A0=A0 enum drm_sched_priority=A0=A0=A0=A0=A0=A0= =A0 s_priority; > > > > > > > =A0=A0=A0=A0=A0=A0 struct drm_sched_entity=A0=A0=A0=A0=A0=A0= =A0=A0 *entity; > > > > > > > =A0=A0=A0=A0=A0=A0 struct dma_fence_cb=A0=A0=A0=A0=A0=A0=A0 = cb; > > > > > > > +=A0=A0=A0 int resubmit_flag; > > > > > > > =A0=A0 }; > > > > > > > =A0=A0 static inline bool drm_sched_invalidate_job(struct > > > > > > > drm_sched_job *s_job, > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flis= ts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D04%7C01%7Candr= ey.grodzovsky%40amd.com%7C9749ced7ce6645bd832408d94d305aaa%7C3dd8961fe4884e= 608e11a82d994e183d%7C0%7C0%7C637625692355112825%7CUnknown%7CTWFpbGZsb3d8eyJ= WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&= sdata=3DOhLndCUDlWcrhg%2FA0QQ%2FoONxdmQ46CT7P%2F8uvSTGnQ8%3D&reserved= =3D0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx