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* [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus
@ 2021-07-14 21:06 Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Christoph Niedermaier
                   ` (15 more replies)
  0 siblings, 16 replies; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:06 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Add the parallel system bus provided by the i.MX6 WEIM interface via an
address latch. The OE pin of the latch is controlled by a fixed regulator.
The pin is low active. This is ensured by omitting the regulators property
enable-active-high. The flags value of the gpio property (3rd value), which
is also use to define active high/low, is set to 0 because it is ignored
by gpiolib-of.c.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rework of the commit message
    - Add a comment to the regulator
    - Replace GPIO_ACTIVE_HIGH with 0 at the gpio property of the regulator
    - Remove spaces from the ranges property of the weim node
    - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 57 ++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 4bf51f3ce003..921a695b79fb 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -46,6 +46,14 @@
 		vin-supply = <&sw2_reg>;
 	};
 
+	/* OE pin of the latch is low active */
+	reg_latch_oe_on: regulator-latch-oe-on {
+		compatible = "regulator-fixed";
+		gpio = <&gpio3 22 0>;
+		regulator-always-on;
+		regulator-name = "latch_oe_on";
+	};
+
 	reg_usb_otg_vbus: regulator-usb-otg-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb_otg_vbus";
@@ -455,6 +463,43 @@
 			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
 		>;
 	};
+
+	pinctrl_weim: weim-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0a6
+			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0a6 /* WE */
+			MX6QDL_PAD_EIM_LBA__EIM_LBA_B		0xb060 /* LE */
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
+			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0a6
+			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0a6
+			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0a6
+			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0a6
+			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0a6
+			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0a6
+			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0a6
+			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0a6
+			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0a6
+			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0a6
+			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0a6
+			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0a6
+			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0a6
+			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0a6
+			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0a6
+			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0a6
+		>;
+	};
+
+	pinctrl_weim_cs0: weim-cs0-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
+		>;
+	};
+
+	pinctrl_weim_cs1: weim-cs1-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_CS1__EIM_CS1_B		0xb0b1
+		>;
+	};
 };
 
 &reg_arm {
@@ -544,3 +589,15 @@
 	keep-power-in-suspend;
 	status = "okay";
 };
+
+&weim {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	fsl,weim-cs-gpr = <&gpr>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+	/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
+	ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
+		 <1 0 0x0c000000 0x04000000>; /* CS1 */
+	status = "disabled";
+};
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  3:59   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM Christoph Niedermaier
                   ` (14 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Enable the interrupt mode for the ethernet PHY by adding the
necessary property and a separate pinctrl for the PHY. Also
add the compatible property for it.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 921a695b79fb..0b318d42fe71 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -124,8 +124,13 @@
 		#size-cells = <0>;
 
 		ethphy0: ethernet-phy@0 {	/* SMSC LAN8710Ai */
-			reg = <0>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio4>;
+			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 			max-speed = <100>;
+			pinctrl-0 = <&pinctrl_ethphy0>;
+			pinctrl-names = "default";
+			reg = <0>;
 			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
@@ -299,8 +304,6 @@
 			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
 			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
-			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x000b0
-			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x000b1
 		>;
 	};
 
@@ -310,6 +313,13 @@
 		>;
 	};
 
+	pinctrl_ethphy0: ethphy0-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0xb0 /* Reset */
+			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0xb1 /* Int */
+		>;
+	};
+
 	pinctrl_flexcan1: flexcan1-grp {
 		fsl,pins = <
 			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  4:01   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl Christoph Niedermaier
                   ` (13 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Fill in the custom GPIO line names used by DH on the DHCOM SoM.
The GPIO line names are in accordance to DHCOM Design Guide R04
available at [1], section 3.9 GPIO. Adding also GPIO line names
for the hardware and memory coding.

[1] https://wiki.dh-electronics.com/images/5/52/DOC_DHCOM-Design-Guide_R04_2018-06-28.pdf

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 56 ++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 0b318d42fe71..d4a761b6b6aa 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -139,6 +139,62 @@
 	};
 };
 
+&gpio1 {
+	gpio-line-names =
+		"", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
+		"", "", "", "", "", "", "", "",
+		"DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "DHCOM-G", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
+		"DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
+		"", "", "", "", "DHCOM-F", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
+		"", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio7 {
+	gpio-line-names =
+		"DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
+		"", "", "", "", "", "DHCOM-P", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default", "gpio";
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  4:03   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs Christoph Niedermaier
                   ` (12 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to
the SoM devicetree. Add PCIe Reset GPIO to the board devicetree.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts |  7 +++----
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 11 +++++++++++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index a685b1c3208f..6c5eaeefa22e 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -232,9 +232,9 @@
 		>;
 	};
 
-	pinctrl_pcie: pcie-grp {
+	pinctrl_pcie_reset: pcie-reset-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
 		>;
 	};
 };
@@ -244,8 +244,7 @@
 };
 
 &pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie>;
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
 	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index d4a761b6b6aa..c5c060c6b9bf 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -450,6 +450,12 @@
 		>;
 	};
 
+	pinctrl_pcie: pcie-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
+		>;
+	};
+
 	pinctrl_uart1: uart1-grp {
 		fsl,pins = <
 			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
@@ -568,6 +574,11 @@
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+};
+
 &reg_arm {
 	vin-supply = <&sw3_reg>;
 };
-- 
2.11.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (2 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  4:06   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board Christoph Niedermaier
                   ` (11 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Set stdout-path to "serial0:15200n8" to align it with other DHCOM
SoMs like the DHCOM STM32MP1.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 6c5eaeefa22e..6bb7129d0498 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -13,7 +13,7 @@
 	compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
 
 	chosen {
-		stdout-path = &uart1;
+		stdout-path = "serial0:115200n8";
 	};
 
 	clk_ext_audio_codec: clock-codec {
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (3 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  4:07   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on " Christoph Niedermaier
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

On the PDK2 there are 4 keys and 4 leds. DHCOM GPIOs are
used for that, but one led isn't useable, because the GPIO
is already used as touch interrupt.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Fix typo in commit message
    - Replace the property label with the
      properties color and function
V4: - Include dt-bindings/leds/common.h file
V5: - Move the dt-bindings/leds/common.h include
      from the SoM to the carrier board file
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 93 ++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 6bb7129d0498..4d455831b3ca 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "imx6q-dhcom-som.dtsi"
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
@@ -57,6 +58,80 @@
 		};
 	};
 
+	gpio-keys {
+		#size-cells = <0>;
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_keys_pdk2>;
+
+		button-0 {
+			label = "TA1-GPIO-A";
+			linux,code = <KEY_A>;
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-1 {
+			label = "TA2-GPIO-B";
+			linux,code = <KEY_B>;
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-2 {
+			label = "TA3-GPIO-C";
+			linux,code = <KEY_C>;
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-3 {
+			label = "TA4-GPIO-D";
+			linux,code = <KEY_D>;
+			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
+	led {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_leds_pdk2>;
+
+		/*
+		 * Disable led-5, because GPIO E is
+		 * already used as touch interrupt.
+		 */
+		led-5 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
+			default-state = "off";
+			status = "disabled";
+		};
+
+		led-6 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
+			default-state = "off";
+		};
+
+		led-7 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
+			default-state = "off";
+		};
+
+		led-8 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			default-state = "off";
+		};
+	};
+
 	panel {
 		compatible = "edt,etm0700g0edh6";
 		ddc-i2c-bus = <&i2c2>;
@@ -237,6 +312,24 @@
 			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
 		>;
 	};
+
+	pinctrl_keys_pdk2: keys-pdk2-grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x120b0 /* TA1 */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x120b0 /* TA2 */
+			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x120b0 /* TA3 */
+			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x120b0 /* TA4 */
+		>;
+	};
+
+	pinctrl_leds_pdk2: leds-pdk2-grp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x120b0 /* led6 */
+			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0 /* led7 */
+			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x120b0 /* led8 */
+		>;
+	};
+
 };
 
 &ipu1_di0_disp0 {
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (4 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  6:30   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls Christoph Niedermaier
                   ` (9 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.

This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Rework of the commit message
    - Remove superfluous property max-speed
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 51 ++++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 4d455831b3ca..3b0276de41f9 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -173,6 +173,46 @@
 	status = "disabled";
 };
 
+/* 1G ethernet */
+/delete-node/ &ethphy0;
+&fec {
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy7>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_1G>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy7: ethernet-phy@7 { /* KSZ 9021 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio1>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy7>;
+			pinctrl-names = "default";
+			reg = <7>;
+			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+
+			rxc-skew-ps = <3000>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			txc-skew-ps = <3000>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
 &hdmi {
 	ddc-i2c-bus = <&i2c2>;
 	status = "okay";
@@ -255,9 +295,14 @@
 			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
 			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x000b0
-			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x000b1
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x000b1
+		>;
+	};
+
+	pinctrl_ethphy7: ethphy7-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 		>;
 	};
 
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (5 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on " Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  6:40   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property Christoph Niedermaier
                   ` (8 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Define each DHCOM GPIO as a separate pinctrl. So on board layer it is
possible to easily add an used DHCOM GPIO by moving &pinctrl_dhcom_X
from the gpio hog list to the appropriate driver pinctrl.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - No changes
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 105 ++++++++++++-------------------
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 109 ++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 66 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 3b0276de41f9..8122db759880 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -38,7 +38,7 @@
 		#size-cells = <0>;
 		interface-pix-fmt = "rgb24";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
 		status = "okay";
 
 		port@0 {
@@ -61,13 +61,13 @@
 	gpio-keys {
 		#size-cells = <0>;
 		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_keys_pdk2>;
 
 		button-0 {
 			label = "TA1-GPIO-A";
 			linux,code = <KEY_A>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_a>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -75,6 +75,8 @@
 			label = "TA2-GPIO-B";
 			linux,code = <KEY_B>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_b>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -82,6 +84,8 @@
 			label = "TA3-GPIO-C";
 			linux,code = <KEY_C>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_c>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -89,14 +93,14 @@
 			label = "TA4-GPIO-D";
 			linux,code = <KEY_D>;
 			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_d>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 	};
 
 	led {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_leds_pdk2>;
 
 		/*
 		 * Disable led-5, because GPIO E is
@@ -107,6 +111,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_e>;
+			pinctrl-names = "default";
 			status = "disabled";
 		};
 
@@ -115,6 +121,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_f>;
+			pinctrl-names = "default";
 		};
 
 		led-7 {
@@ -122,6 +130,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_h>;
+			pinctrl-names = "default";
 		};
 
 		led-8 {
@@ -129,6 +139,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
 		};
 	};
 
@@ -230,7 +242,7 @@
 
 	touchscreen@38 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_touchscreen>;
+		pinctrl-0 = <&pinctrl_dhcom_e>;
 		compatible = "edt,edt-ft5406";
 		reg = <0x38>;
 		interrupt-parent = <&gpio4>;
@@ -240,34 +252,28 @@
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
-
-	pinctrl_hog: hog-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x400120b0
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x400120b0
-			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x400120b0
-			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x400120b0
-			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0
-			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x400120b0
-			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0
-			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x400120b0
-			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x400120b0
-			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x400120b0
-			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0
-			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x400120b0
-			MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0x400120b0
-			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16		0x400120b0
-			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17		0x400120b0
-			MX6QDL_PAD_SD1_DAT2__GPIO1_IO19		0x400120b0
-			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x400120b0
-			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0
-			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0
-			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x400120b0
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * A: key TA1
+			 * B: key TA2
+			 * C: key TA3
+			 * D: key TA4
+			 * E: touchscreen
+			 * F: led6
+			 * G: backlight enable
+			 * H: led7
+			 * I: led8
+			 * J: PCIe reset
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
-	};
 
 	pinctrl_audmux_ext: audmux-ext-grp {
 		fsl,pins = <
@@ -336,7 +342,6 @@
 			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38
 			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38
 			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38
-			MX6QDL_PAD_EIM_D27__GPIO3_IO27			0x120b0
 		>;
 	};
 
@@ -345,36 +350,6 @@
 			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
 		>;
 	};
-
-	pinctrl_touchscreen: touchscreen-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b1
-		>;
-	};
-
-	pinctrl_pcie_reset: pcie-reset-grp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
-		>;
-	};
-
-	pinctrl_keys_pdk2: keys-pdk2-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x120b0 /* TA1 */
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x120b0 /* TA2 */
-			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x120b0 /* TA3 */
-			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x120b0 /* TA4 */
-		>;
-	};
-
-	pinctrl_leds_pdk2: leds-pdk2-grp {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x120b0 /* led6 */
-			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0 /* led7 */
-			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x120b0 /* led8 */
-		>;
-	};
-
 };
 
 &ipu1_di0_disp0 {
@@ -382,7 +357,7 @@
 };
 
 &pcie {
-	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
 	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index c5c060c6b9bf..9fd48ab9b3d0 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -317,7 +317,17 @@
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog_base>;
+	pinctrl-0 = <
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
 
 	pinctrl_hog_base: hog-base-grp {
 		fsl,pins = <
@@ -329,6 +339,103 @@
 		>;
 	};
 
+	/* DHCOM GPIOs */
+	pinctrl_dhcom_a: dhcom-a-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x400120b0>;
+	};
+
+	pinctrl_dhcom_b: dhcom-b-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04	0x400120b0>;
+	};
+
+	pinctrl_dhcom_c: dhcom-c-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x400120b0>;
+	};
+
+	pinctrl_dhcom_d: dhcom-d-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0>;
+	};
+
+	pinctrl_dhcom_e: dhcom-e-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05	0x400120b0>;
+	};
+
+	pinctrl_dhcom_f: dhcom-f-grp {
+		fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20	0x400120b0>;
+	};
+
+	pinctrl_dhcom_g: dhcom-g-grp {
+		fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x400120b0>;
+	};
+
+	pinctrl_dhcom_h: dhcom-h-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07	0x400120b0>;
+	};
+
+	pinctrl_dhcom_i: dhcom-i-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08	0x400120b0>;
+	};
+
+	pinctrl_dhcom_j: dhcom-j-grp {
+		fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0>;
+	};
+
+	pinctrl_dhcom_k: dhcom-k-grp {
+		fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0>;
+	};
+
+	pinctrl_dhcom_l: dhcom-l-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09	0x400120b0>;
+	};
+
+	pinctrl_dhcom_m: dhcom-m-grp {
+		fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x400120b0>;
+	};
+
+	pinctrl_dhcom_n: dhcom-n-grp {
+		fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01	0x400120b0>;
+	};
+
+	pinctrl_dhcom_o: dhcom-o-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0>;
+	};
+
+	pinctrl_dhcom_p: dhcom-p-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13	0x400120b0>;
+	};
+
+	pinctrl_dhcom_q: dhcom-q-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18	0x400120b0>;
+	};
+
+	pinctrl_dhcom_r: dhcom-r-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16	0x400120b0>;
+	};
+
+	pinctrl_dhcom_s: dhcom-s-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17	0x400120b0>;
+	};
+
+	pinctrl_dhcom_t: dhcom-t-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19	0x400120b0>;
+	};
+
+	pinctrl_dhcom_u: dhcom-u-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20	0x400120b0>;
+	};
+
+	pinctrl_dhcom_v: dhcom-v-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0>;
+	};
+
+	pinctrl_dhcom_w: dhcom-w-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0>;
+	};
+
+	pinctrl_dhcom_int: dhcom-int-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06	0x400120b0>;
+	};
+
 	pinctrl_ecspi1: ecspi1-grp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (6 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  6:41   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants Christoph Niedermaier
                   ` (7 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

An EDID lookup is not needed with this panel.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 8122db759880..e7fae54a97fa 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -146,7 +146,6 @@
 
 	panel {
 		compatible = "edt,etm0700g0edh6";
-		ddc-i2c-bus = <&i2c2>;
 		backlight = <&display_bl>;
 
 		port {
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (7 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-23  6:48   ` Shawn Guo
  2021-07-14 21:07 ` [PATCH V6 11/15] ARM: dts: imx6q-dhcom: Rearrange of iomux Christoph Niedermaier
                   ` (6 subsequent siblings)
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

The minimum available memory size of all DHCOM i.MX6 variants is 512 MB.
Set this value for the memory node. If U-Boot fails to fill the memory
size, at least all DHCOM i.MX6 variants should run without problems.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - No changes
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 9fd48ab9b3d0..a361e161fba1 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -30,7 +30,7 @@
 
 	memory@10000000 {
 		device_type = "memory";
-		reg = <0x10000000 0x40000000>;
+		reg = <0x10000000 0x20000000>;
 	};
 
 	reg_eth_vio: regulator-eth-vio {
-- 
2.11.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 11/15] ARM: dts: imx6q-dhcom: Rearrange of iomux
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (8 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 12/15] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees Christoph Niedermaier
                   ` (5 subsequent siblings)
  15 siblings, 0 replies; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Move iomux to the end, no change in function.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts |  56 ++++-----
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 210 ++++++++++++++++-----------------
 2 files changed, 133 insertions(+), 133 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index e7fae54a97fa..2b157c5eb0ce 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -249,6 +249,34 @@
 	};
 };
 
+&ipu1_di0_disp0 {
+	remote-endpoint = <&lcd_display_in>;
+};
+
+&pcie {
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
+	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&usdhc3 {
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <
@@ -350,31 +378,3 @@
 		>;
 	};
 };
-
-&ipu1_di0_disp0 {
-	remote-endpoint = <&lcd_display_in>;
-};
-
-&pcie {
-	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
-	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
-
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm1>;
-	status = "okay";
-};
-
-&ssi1 {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&usdhc3 {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index a361e161fba1..829f31bc569d 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -315,6 +315,111 @@
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+};
+
+&reg_arm {
+	vin-supply = <&sw3_reg>;
+};
+
+&reg_soc {
+	vin-supply = <&sw1_reg>;
+};
+
+&reg_pu {
+	vin-supply = <&sw1_reg>;
+};
+
+&reg_vdd1p1 {
+	vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd2p5 {
+	vin-supply = <&sw2_reg>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	uart-has-rtscts;
+	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+	rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbh1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
+	vbus-supply = <&reg_usb_h1_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+	fsl,wp-controller;
+	keep-power-in-suspend;
+	status = "disabled";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	non-removable;
+	bus-width = <8>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&weim {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	fsl,weim-cs-gpr = <&gpr>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+	/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
+	ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
+		 <1 0 0x0c000000 0x04000000>; /* CS1 */
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <
@@ -680,108 +785,3 @@
 		>;
 	};
 };
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie>;
-};
-
-&reg_arm {
-	vin-supply = <&sw3_reg>;
-};
-
-&reg_soc {
-	vin-supply = <&sw1_reg>;
-};
-
-&reg_pu {
-	vin-supply = <&sw1_reg>;
-};
-
-&reg_vdd1p1 {
-	vin-supply = <&sw2_reg>;
-};
-
-&reg_vdd2p5 {
-	vin-supply = <&sw2_reg>;
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	uart-has-rtscts;
-	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
-	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
-	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
-	rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usbh1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbh1>;
-	vbus-supply = <&reg_usb_h1_vbus>;
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
-	disable-over-current;
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
-	keep-power-in-suspend;
-	status = "okay";
-};
-
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
-	fsl,wp-controller;
-	keep-power-in-suspend;
-	status = "disabled";
-};
-
-&usdhc4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc4>;
-	non-removable;
-	bus-width = <8>;
-	no-1-8-v;
-	keep-power-in-suspend;
-	status = "okay";
-};
-
-&weim {
-	#address-cells = <2>;
-	#size-cells = <1>;
-	fsl,weim-cs-gpr = <&gpr>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
-	/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
-	ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
-		 <1 0 0x0c000000 0x04000000>; /* CS1 */
-	status = "disabled";
-};
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 12/15] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (9 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 11/15] ARM: dts: imx6q-dhcom: Rearrange of iomux Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 13/15] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2 Christoph Niedermaier
                   ` (4 subsequent siblings)
  15 siblings, 0 replies; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Following cleanups of the devicetrees done, no change in function:
- Remove parentheses from the license
- Update copyright date
- Alphabetical sorting
- Add comments
- Update pinctrl names
- Hex values in lower case
- Set 3rd values of fixed regulators gpio property to 0
- Replace interrupt type with a define
- Remove superfluous property max-speed from the fec node

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Set 3rd values of fixed regulators gpio property to 0
    - Rebase on Shawn Guos branch for-next
V3: - Remove superfluous property max-speed from the fec node
    - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts |  90 +++++-----
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 302 +++++++++++++++++----------------
 2 files changed, 204 insertions(+), 188 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 2b157c5eb0ce..81d78041daa3 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  */
 
@@ -18,27 +18,27 @@
 	};
 
 	clk_ext_audio_codec: clock-codec {
-		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <24000000>;
+		compatible = "fixed-clock";
 	};
 
 	display_bl: display-bl {
-		compatible = "pwm-backlight";
-		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
 		brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+		compatible = "pwm-backlight";
 		default-brightness-level = <8>;
-		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
+		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
 		status = "okay";
 	};
 
 	lcd_display: disp0 {
-		compatible = "fsl,imx-parallel-display";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		compatible = "fsl,imx-parallel-display";
 		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
+		pinctrl-names = "default";
 		status = "okay";
 
 		port@0 {
@@ -63,36 +63,36 @@
 		compatible = "gpio-keys";
 
 		button-0 {
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
 			label = "TA1-GPIO-A";
 			linux,code = <KEY_A>;
-			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_a>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-1 {
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
 			label = "TA2-GPIO-B";
 			linux,code = <KEY_B>;
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_b>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-2 {
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
 			label = "TA3-GPIO-C";
 			linux,code = <KEY_C>;
-			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_c>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-3 {
+			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
 			label = "TA4-GPIO-D";
 			linux,code = <KEY_D>;
-			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_d>;
 			pinctrl-names = "default";
 			wakeup-source;
@@ -108,9 +108,9 @@
 		 */
 		led-5 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_e>;
 			pinctrl-names = "default";
 			status = "disabled";
@@ -118,35 +118,35 @@
 
 		led-6 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_f>;
 			pinctrl-names = "default";
 		};
 
 		led-7 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_h>;
 			pinctrl-names = "default";
 		};
 
 		led-8 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_i>;
 			pinctrl-names = "default";
 		};
 	};
 
 	panel {
-		compatible = "edt,etm0700g0edh6";
 		backlight = <&display_bl>;
+		compatible = "edt,etm0700g0edh6";
 
 		port {
 			lcd_panel_in: endpoint {
@@ -156,23 +156,23 @@
 	};
 
 	sound {
-		compatible = "fsl,imx-audio-sgtl5000";
-		model = "imx-sgtl5000";
-		ssi-controller = <&ssi1>;
 		audio-codec = <&sgtl5000>;
 		audio-routing =
 			"MIC_IN", "Mic Jack",
 			"Mic Jack", "Mic Bias",
 			"LINE_IN", "Line In Jack",
 			"Headphone Jack", "HP_OUT";
-		mux-int-port = <1>;
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx-sgtl5000";
 		mux-ext-port = <3>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
 	};
 };
 
 &audmux {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_audmux_ext>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -189,8 +189,8 @@
 &fec {
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy7>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_1G>;
+	pinctrl-names = "default";
 	status = "okay";
 
 	mdio {
@@ -204,21 +204,21 @@
 			pinctrl-0 = <&pinctrl_ethphy7>;
 			pinctrl-names = "default";
 			reg = <7>;
-			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 
 			rxc-skew-ps = <3000>;
 			rxd0-skew-ps = <0>;
 			rxd1-skew-ps = <0>;
 			rxd2-skew-ps = <0>;
 			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
 			txc-skew-ps = <3000>;
 			txd0-skew-ps = <0>;
 			txd1-skew-ps = <0>;
 			txd2-skew-ps = <0>;
 			txd3-skew-ps = <0>;
-			rxdv-skew-ps = <0>;
 			txen-skew-ps = <0>;
 		};
 	};
@@ -231,21 +231,21 @@
 
 &i2c2 {
 	sgtl5000: codec@a {
-		compatible = "fsl,sgtl5000";
-		reg = <0x0a>;
 		#sound-dai-cells = <0>;
 		clocks = <&clk_ext_audio_codec>;
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
 		VDDA-supply = <&reg_3p3v>;
 		VDDIO-supply = <&sw2_reg>;
 	};
 
 	touchscreen@38 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_dhcom_e>;
 		compatible = "edt,edt-ft5406";
-		reg = <0x38>;
 		interrupt-parent = <&gpio4>;
 		interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+		pinctrl-0 = <&pinctrl_dhcom_e>;
+		pinctrl-names = "default";
+		reg = <0x38>;
 	};
 };
 
@@ -255,13 +255,13 @@
 
 &pcie {
 	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
-	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
 	status = "okay";
 };
 
 &pwm1 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -273,12 +273,11 @@
 	status = "okay";
 };
 
-&usdhc3 {
+&usdhc3 { /* Micro SD card on module */
 	status = "okay";
 };
 
 &iomuxc {
-	pinctrl-names = "default";
 	pinctrl-0 = <
 			/*
 			 * The following DHCOM GPIOs are used on this board.
@@ -301,50 +300,51 @@
 			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
 			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
+	pinctrl-names = "default";
 
 	pinctrl_audmux_ext: audmux-ext-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
 			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
 			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
 			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
 		>;
 	};
 
 	pinctrl_enet_1G: enet-1G-grp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
 			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
 			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
 			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
 			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
 		>;
 	};
 
 	pinctrl_ethphy7: ethphy7-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
 			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 		>;
 	};
 
 	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
 		fsl,pins = <
 			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
 			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38
 			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
 			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38
 			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38
 			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 829f31bc569d..99a275e06643 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  */
 
@@ -28,14 +28,22 @@
 		serial4 = &uart3;
 	};
 
-	memory@10000000 {
+	memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
 		device_type = "memory";
 		reg = <0x10000000 0x20000000>;
 	};
 
+	reg_3p3v: regulator-3P3V {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "3P3V";
+	};
+
 	reg_eth_vio: regulator-eth-vio {
 		compatible = "regulator-fixed";
-		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+		gpio = <&gpio1 7 0>;
 		pinctrl-0 = <&pinctrl_enet_vio>;
 		pinctrl-names = "default";
 		regulator-always-on;
@@ -54,86 +62,84 @@
 		regulator-name = "latch_oe_on";
 	};
 
-	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
 		compatible = "regulator-fixed";
-		regulator-name = "usb_otg_vbus";
+		enable-active-high;
+		gpio = <&gpio3 31 0>;
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-name = "usb_h1_vbus";
 	};
 
-	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
 		compatible = "regulator-fixed";
-		regulator-name = "usb_h1_vbus";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_3p3v: regulator-3P3V {
-		compatible = "regulator-fixed";
-		regulator-name = "3P3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		regulator-name = "usb_otg_vbus";
 	};
 };
 
 &can1 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan1>;
+	pinctrl-names = "default";
 };
 
+/*
+ * Special hardware required which uses the pins from micro SD card. The pins
+ * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx
+ * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board
+ * device tree file, you also need to disable the micro SD card and the uart1
+ * rts/cts have to be disabled or output on other DHCOM pins.
+ */
 &can2 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;
+	pinctrl-names = "default";
 };
 
 &ecspi1 {
 	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
+	pinctrl-names = "default";
 	status = "okay";
 
-	flash@0 {	/* S25FL116K */
+	flash@0 { /* S25FL116K */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
 		m25p,fast-read;
+		reg = <0>;
+		spi-max-frequency = <50000000>;
 	};
 };
 
 &ecspi2 {
 	cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi2>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
 &fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet_100M>;
 	phy-mode = "rmii";
 	phy-handle = <&ethphy0>;
+	pinctrl-0 = <&pinctrl_enet_100M>;
+	pinctrl-names = "default";
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy0: ethernet-phy@0 {	/* SMSC LAN8710Ai */
+		ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
 			compatible = "ethernet-phy-ieee802.3-c22";
 			interrupt-parent = <&gpio4>;
 			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
-			max-speed = <100>;
 			pinctrl-0 = <&pinctrl_ethphy0>;
 			pinctrl-names = "default";
 			reg = <0>;
-			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			smsc,disable-energy-detect; /* Make plugin detection reliable */
 		};
 	};
@@ -196,139 +202,147 @@
 };
 
 &i2c1 {
+	/*
+	 * Info: According to erratum ERR007805 clock frequency limit is 375000.
+	 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
+	 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
+	 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+	 */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
 &i2c2 {
+	/* Info: Clock frequency limit is 375000 (for details see i2c1) */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
 &i2c3 {
+	/* Info: Clock frequency limit is 375000 (for details see i2c1) */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
 	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	ltc3676: pmic@3c {
 		compatible = "lltc,ltc3676";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic_hw300>;
-		reg = <0x3c>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		pinctrl-names = "default";
+		reg = <0x3c>;
 
 		regulators {
 			sw1_reg: sw1 {
-				regulator-min-microvolt = <787500>;
-				regulator-max-microvolt = <1527272>;
 				lltc,fb-voltage-divider = <100000 110000>;
-				regulator-suspend-mem-microvolt = <1040000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1527272>;
+				regulator-min-microvolt = <787500>;
+				regulator-ramp-delay = <7000>;
+				regulator-suspend-mem-microvolt = <1040000>;
 			};
 
 			sw2_reg: sw2 {
-				regulator-min-microvolt = <1885714>;
-				regulator-max-microvolt = <3657142>;
 				lltc,fb-voltage-divider = <100000 28000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3657142>;
+				regulator-min-microvolt = <1885714>;
+				regulator-ramp-delay = <7000>;
 			};
 
 			sw3_reg: sw3 {
-				regulator-min-microvolt = <787500>;
-				regulator-max-microvolt = <1527272>;
 				lltc,fb-voltage-divider = <100000 110000>;
-				regulator-suspend-mem-microvolt = <980000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1527272>;
+				regulator-min-microvolt = <787500>;
+				regulator-ramp-delay = <7000>;
+				regulator-suspend-mem-microvolt = <980000>;
 			};
 
 			sw4_reg: sw4 {
-				regulator-min-microvolt = <855571>;
-				regulator-max-microvolt = <1659291>;
 				lltc,fb-voltage-divider = <100000 93100>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1659291>;
+				regulator-min-microvolt = <855571>;
+				regulator-ramp-delay = <7000>;
 			};
 
 			ldo1_reg: ldo1 {
-				regulator-min-microvolt = <3240306>;
-				regulator-max-microvolt = <3240306>;
 				lltc,fb-voltage-divider = <102000 29400>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3240306>;
+				regulator-min-microvolt = <3240306>;
 			};
 
 			ldo2_reg: ldo2 {
-				regulator-min-microvolt = <2484708>;
-				regulator-max-microvolt = <2484708>;
 				lltc,fb-voltage-divider = <100000 41200>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2484708>;
+				regulator-min-microvolt = <2484708>;
 			};
 		};
 	};
 
-	touchscreen@49 {	/* TSC2004 */
+	touchscreen@49 { /* TSC2004 */
 		compatible = "ti,tsc2004";
+		interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_tsc2004>;
+		pinctrl-names = "default";
 		reg = <0x49>;
 		vio-supply = <&reg_3p3v>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_tsc2004_hw300>;
-		interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
 		status = "disabled";
 	};
 
 	eeprom@50 {
 		compatible = "atmel,24c02";
-		reg = <0x50>;
 		pagesize = <16>;
+		reg = <0x50>;
 	};
 
 	rtc_i2c: rtc@56 {
 		compatible = "microcrystal,rv3029";
+		interrupt-parent = <&gpio7>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_rtc>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_rtc_hw300>;
 		reg = <0x56>;
-		interrupt-parent = <&gpio7>;
-		interrupts = <12 2>;
 	};
 };
 
 &pcie {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
+	pinctrl-names = "default";
 };
 
 &reg_arm {
 	vin-supply = <&sw3_reg>;
 };
 
-&reg_soc {
+&reg_pu {
 	vin-supply = <&sw1_reg>;
 };
 
-&reg_pu {
+&reg_soc {
 	vin-supply = <&sw1_reg>;
 };
 
@@ -340,71 +354,71 @@
 	vin-supply = <&sw2_reg>;
 };
 
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	uart-has-rtscts;
-	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
-	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+&uart1 { /* DHCOM UART1 */
 	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
 	rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
 	status = "okay";
 };
 
-&uart4 {
-	pinctrl-names = "default";
+&uart4 { /* DHCOM UART3 */
 	pinctrl-0 = <&pinctrl_uart4>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
-&uart5 {
-	pinctrl-names = "default";
+&uart5 { /* DHCOM UART2 */
 	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
 	uart-has-rtscts;
 	status = "okay";
 };
 
 &usbh1 {
-	pinctrl-names = "default";
+	dr_mode = "host";
 	pinctrl-0 = <&pinctrl_usbh1>;
+	pinctrl-names = "default";
 	vbus-supply = <&reg_usb_h1_vbus>;
-	dr_mode = "host";
 	status = "okay";
 };
 
 &usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
 	disable-over-current;
 	dr_mode = "otg";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	pinctrl-names = "default";
+	vbus-supply = <&reg_usb_otg_vbus>;
 	status = "okay";
 };
 
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
+&usdhc2 { /* External SD card via DHCOM */
 	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
 	keep-power-in-suspend;
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
+&usdhc3 { /* Micro SD card on module */
 	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
 	fsl,wp-controller;
 	keep-power-in-suspend;
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-names = "default";
 	status = "disabled";
 };
 
-&usdhc4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc4>;
-	non-removable;
+&usdhc4 { /* eMMC on module */
 	bus-width = <8>;
-	no-1-8-v;
 	keep-power-in-suspend;
+	no-1-8-v;
+	non-removable;
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -412,8 +426,8 @@
 	#address-cells = <2>;
 	#size-cells = <1>;
 	fsl,weim-cs-gpr = <&gpr>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+	pinctrl-names = "default";
 	/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
 	ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
 		 <1 0 0x0c000000 0x04000000>; /* CS1 */
@@ -421,7 +435,6 @@
 };
 
 &iomuxc {
-	pinctrl-names = "default";
 	pinctrl-0 = <
 			&pinctrl_hog_base
 			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
@@ -433,14 +446,17 @@
 			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
 			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
+	pinctrl-names = "default";
 
 	pinctrl_hog_base: hog-base-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0x120b0
-			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x120b0
-			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x120b0
+			/* GPIOs for memory coding */
 			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x120b0
 			MX6QDL_PAD_EIM_A17__GPIO2_IO21		0x120b0
+			/* GPIOs for hardware coding */
+			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0x120b0
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x120b0
+			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x120b0
 		>;
 	};
 
@@ -543,9 +559,9 @@
 
 	pinctrl_ecspi1: ecspi1-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
 			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
 			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
 			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
 			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
 		>;
@@ -553,18 +569,18 @@
 
 	pinctrl_ecspi2: ecspi2-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO	0x100b1
-			MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI	0x100b1
 			MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK	0x100b1
+			MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI	0x100b1
+			MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO	0x100b1
 			MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29	0x1b0b0
 		>;
 	};
 
 	pinctrl_enet_100M: enet-100M-grp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
 			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
 			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
 			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
@@ -590,8 +606,8 @@
 
 	pinctrl_flexcan1: flexcan1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
 			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
+			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
 		>;
 	};
 
@@ -644,40 +660,40 @@
 		>;
 	};
 
-	pinctrl_pmic_hw300: pmic-hw300-grp {
+	pinctrl_pcie: pcie-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1B0B0
+			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
 		>;
 	};
 
-	pinctrl_rtc_hw300: rtc-hw300-grp {
+	pinctrl_pmic: pmic-grp {
 		fsl,pins = <
-			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120B0
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b0
 		>;
 	};
 
-	pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
+	pinctrl_rtc: rtc-grp {
 		fsl,pins = <
-			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x120B0
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120b0
 		>;
 	};
 
-	pinctrl_pcie: pcie-grp {
+	pinctrl_tsc2004: tsc2004-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
+			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x120b0
 		>;
 	};
 
 	pinctrl_uart1: uart1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
-			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
-			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
 			MX6QDL_PAD_EIM_D19__UART1_CTS_B		0x4001b0b1
+			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
 			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x4001b0b1
 			MX6QDL_PAD_EIM_D24__GPIO3_IO24		0x4001b0b1
 			MX6QDL_PAD_EIM_D25__GPIO3_IO25		0x4001b0b1
 			MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x4001b0b1
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
 		>;
 	};
 
@@ -699,7 +715,7 @@
 
 	pinctrl_usbh1: usbh1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x120B0
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x120b0
 		>;
 	};
 
@@ -711,32 +727,32 @@
 
 	pinctrl_usdhc2: usdhc2-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x120b0
 			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
 			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
 			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
 			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
 			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
-			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x120B0
 		>;
 	};
 
 	pinctrl_usdhc3: usdhc3-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
 			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
 			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
 			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
 			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x120B0
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x120b0
 		>;
 	};
 
 	pinctrl_usdhc4: usdhc4-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
 			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
 			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
 			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
 			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
@@ -750,26 +766,26 @@
 
 	pinctrl_weim: weim-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0a6
+			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0a6
+			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0a6
+			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0a6
+			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0a6
+			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0a6
+			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0a6
+			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0a6
+			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0a6
+			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0a6
+			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0a6
+			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0a6
+			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0a6
+			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0a6
+			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0a6
+			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0a6
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
+			MX6QDL_PAD_EIM_LBA__EIM_LBA_B		0xb060 /* LE */
 			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0a6
 			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0a6 /* WE */
-			MX6QDL_PAD_EIM_LBA__EIM_LBA_B		0xb060 /* LE */
-			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
-			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0a6
-			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0a6
-			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0a6
-			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0a6
-			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0a6
-			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0a6
-			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0a6
-			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0a6
-			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0a6
-			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0a6
-			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0a6
-			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0a6
-			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0a6
-			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0a6
-			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0a6
-			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0a6
 		>;
 	};
 
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 13/15] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (10 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 12/15] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 14/15] ARM: dts: imx6qdl-dhcom: Add DHCOM based PicoITX board Christoph Niedermaier
                   ` (3 subsequent siblings)
  15 siblings, 0 replies; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

The DH electronics PDK2 can be populated with SoM with i.MX6S/DL/D/Q
variants. Split the SoC-independent parts of the SoM and PDK2 into the
imx6qdl-dhcom-*.dtsi and reduce imx6q-dhcom-pdk2.dts to example of
adding i.MX6S/DL/D/Q variants of the SoM into a PDK2 carrier board.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Fix typo in commit message
    - Rebase on Shawn Guos branch for-next
V3: - No changes
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts             | 377 +--------------------
 arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi          | 362 ++++++++++++++++++++
 ...imx6q-dhcom-som.dtsi => imx6qdl-dhcom-som.dtsi} |  30 +-
 3 files changed, 394 insertions(+), 375 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
 rename arch/arm/boot/dts/{imx6q-dhcom-som.dtsi => imx6qdl-dhcom-som.dtsi} (97%)

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 81d78041daa3..d4d57370615d 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -2,379 +2,24 @@
 /*
  * Copyright (C) 2015-2021 DH electronics GmbH
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PDK2 PCB number: 516-400 or newer
  */
-
 /dts-v1/;
 
-#include "imx6q-dhcom-som.dtsi"
-#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-pdk2.dtsi"
 
 / {
-	model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
-	compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	clk_ext_audio_codec: clock-codec {
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		compatible = "fixed-clock";
-	};
-
-	display_bl: display-bl {
-		brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
-		compatible = "pwm-backlight";
-		default-brightness-level = <8>;
-		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
-		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
-		status = "okay";
-	};
-
-	lcd_display: disp0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx-parallel-display";
-		interface-pix-fmt = "rgb24";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
-		pinctrl-names = "default";
-		status = "okay";
-
-		port@0 {
-			reg = <0>;
-
-			lcd_display_in: endpoint {
-				remote-endpoint = <&ipu1_di0_disp0>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			lcd_display_out: endpoint {
-				remote-endpoint = <&lcd_panel_in>;
-			};
-		};
-	};
-
-	gpio-keys {
-		#size-cells = <0>;
-		compatible = "gpio-keys";
-
-		button-0 {
-			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
-			label = "TA1-GPIO-A";
-			linux,code = <KEY_A>;
-			pinctrl-0 = <&pinctrl_dhcom_a>;
-			pinctrl-names = "default";
-			wakeup-source;
-		};
-
-		button-1 {
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
-			label = "TA2-GPIO-B";
-			linux,code = <KEY_B>;
-			pinctrl-0 = <&pinctrl_dhcom_b>;
-			pinctrl-names = "default";
-			wakeup-source;
-		};
-
-		button-2 {
-			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
-			label = "TA3-GPIO-C";
-			linux,code = <KEY_C>;
-			pinctrl-0 = <&pinctrl_dhcom_c>;
-			pinctrl-names = "default";
-			wakeup-source;
-		};
-
-		button-3 {
-			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
-			label = "TA4-GPIO-D";
-			linux,code = <KEY_D>;
-			pinctrl-0 = <&pinctrl_dhcom_d>;
-			pinctrl-names = "default";
-			wakeup-source;
-		};
-	};
-
-	led {
-		compatible = "gpio-leds";
-
-		/*
-		 * Disable led-5, because GPIO E is
-		 * already used as touch interrupt.
-		 */
-		led-5 {
-			color = <LED_COLOR_ID_GREEN>;
-			default-state = "off";
-			function = LED_FUNCTION_INDICATOR;
-			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
-			pinctrl-0 = <&pinctrl_dhcom_e>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		led-6 {
-			color = <LED_COLOR_ID_GREEN>;
-			default-state = "off";
-			function = LED_FUNCTION_INDICATOR;
-			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
-			pinctrl-0 = <&pinctrl_dhcom_f>;
-			pinctrl-names = "default";
-		};
-
-		led-7 {
-			color = <LED_COLOR_ID_GREEN>;
-			default-state = "off";
-			function = LED_FUNCTION_INDICATOR;
-			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
-			pinctrl-0 = <&pinctrl_dhcom_h>;
-			pinctrl-names = "default";
-		};
-
-		led-8 {
-			color = <LED_COLOR_ID_GREEN>;
-			default-state = "off";
-			function = LED_FUNCTION_INDICATOR;
-			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
-			pinctrl-0 = <&pinctrl_dhcom_i>;
-			pinctrl-names = "default";
-		};
-	};
-
-	panel {
-		backlight = <&display_bl>;
-		compatible = "edt,etm0700g0edh6";
-
-		port {
-			lcd_panel_in: endpoint {
-				remote-endpoint = <&lcd_display_out>;
-			};
-		};
-	};
-
-	sound {
-		audio-codec = <&sgtl5000>;
-		audio-routing =
-			"MIC_IN", "Mic Jack",
-			"Mic Jack", "Mic Bias",
-			"LINE_IN", "Line In Jack",
-			"Headphone Jack", "HP_OUT";
-		compatible = "fsl,imx-audio-sgtl5000";
-		model = "imx-sgtl5000";
-		mux-ext-port = <3>;
-		mux-int-port = <1>;
-		ssi-controller = <&ssi1>;
-	};
-};
-
-&audmux {
-	pinctrl-0 = <&pinctrl_audmux_ext>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&can1 {
-	status = "okay";
-};
-
-&can2 {
-	status = "disabled";
-};
-
-/* 1G ethernet */
-/delete-node/ &ethphy0;
-&fec {
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy7>;
-	pinctrl-0 = <&pinctrl_enet_1G>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy7: ethernet-phy@7 { /* KSZ 9021 */
-			compatible = "ethernet-phy-ieee802.3-c22";
-			interrupt-parent = <&gpio1>;
-			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-			pinctrl-0 = <&pinctrl_ethphy7>;
-			pinctrl-names = "default";
-			reg = <7>;
-			reset-assert-us = <1000>;
-			reset-deassert-us = <1000>;
-			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
-
-			rxc-skew-ps = <3000>;
-			rxd0-skew-ps = <0>;
-			rxd1-skew-ps = <0>;
-			rxd2-skew-ps = <0>;
-			rxd3-skew-ps = <0>;
-			rxdv-skew-ps = <0>;
-			txc-skew-ps = <3000>;
-			txd0-skew-ps = <0>;
-			txd1-skew-ps = <0>;
-			txd2-skew-ps = <0>;
-			txd3-skew-ps = <0>;
-			txen-skew-ps = <0>;
-		};
-	};
-};
-
-&hdmi {
-	ddc-i2c-bus = <&i2c2>;
-	status = "okay";
-};
-
-&i2c2 {
-	sgtl5000: codec@a {
-		#sound-dai-cells = <0>;
-		clocks = <&clk_ext_audio_codec>;
-		compatible = "fsl,sgtl5000";
-		reg = <0x0a>;
-		VDDA-supply = <&reg_3p3v>;
-		VDDIO-supply = <&sw2_reg>;
-	};
-
-	touchscreen@38 {
-		compatible = "edt,edt-ft5406";
-		interrupt-parent = <&gpio4>;
-		interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
-		pinctrl-0 = <&pinctrl_dhcom_e>;
-		pinctrl-names = "default";
-		reg = <0x38>;
-	};
-};
-
-&ipu1_di0_disp0 {
-	remote-endpoint = <&lcd_display_in>;
-};
-
-&pcie {
-	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
-	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
-	status = "okay";
-};
-
-&pwm1 {
-	pinctrl-0 = <&pinctrl_pwm1>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&ssi1 {
-	status = "okay";
+	model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)";
+	compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
+		     "fsl,imx6q";
 };
 
 &sata {
 	status = "okay";
 };
-
-&usdhc3 { /* Micro SD card on module */
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl-0 = <
-			/*
-			 * The following DHCOM GPIOs are used on this board.
-			 * Therefore, they have been removed from the list below.
-			 * A: key TA1
-			 * B: key TA2
-			 * C: key TA3
-			 * D: key TA4
-			 * E: touchscreen
-			 * F: led6
-			 * G: backlight enable
-			 * H: led7
-			 * I: led8
-			 * J: PCIe reset
-			 */
-			&pinctrl_hog_base
-			&pinctrl_dhcom_k &pinctrl_dhcom_l
-			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
-			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
-			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
-			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
-		>;
-	pinctrl-names = "default";
-
-	pinctrl_audmux_ext: audmux-ext-grp {
-		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
-			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
-			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
-			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
-		>;
-	};
-
-	pinctrl_enet_1G: enet-1G-grp {
-		fsl,pins = <
-			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
-			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-		>;
-	};
-
-	pinctrl_ethphy7: ethphy7-grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
-			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
-		>;
-	};
-
-	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38
-			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38
-			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
-			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38
-			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38
-			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38
-			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x38
-			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x38
-			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x38
-			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x38
-			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x38
-			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x38
-			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x38
-			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x38
-			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x38
-			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x38
-			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x38
-			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x38
-			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x38
-			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x38
-			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x38
-			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x38
-			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x38
-			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x38
-			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38
-			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38
-			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38
-		>;
-	};
-
-	pinctrl_pwm1: pwm1-grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
-		>;
-	};
-};
diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
new file mode 100644
index 000000000000..9586ca249003
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2021 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clk_ext_audio_codec: clock-codec {
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		compatible = "fixed-clock";
+	};
+
+	display_bl: display-bl {
+		brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+		compatible = "pwm-backlight";
+		default-brightness-level = <8>;
+		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
+		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
+		status = "okay";
+	};
+
+	lcd_display: disp0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx-parallel-display";
+		interface-pix-fmt = "rgb24";
+		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		port@0 {
+			reg = <0>;
+
+			lcd_display_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp0>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			lcd_display_out: endpoint {
+				remote-endpoint = <&lcd_panel_in>;
+			};
+		};
+	};
+
+	gpio-keys {
+		#size-cells = <0>;
+		compatible = "gpio-keys";
+
+		button-0 {
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
+			label = "TA1-GPIO-A";
+			linux,code = <KEY_A>;
+			pinctrl-0 = <&pinctrl_dhcom_a>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-1 {
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
+			label = "TA2-GPIO-B";
+			linux,code = <KEY_B>;
+			pinctrl-0 = <&pinctrl_dhcom_b>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-2 {
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
+			label = "TA3-GPIO-C";
+			linux,code = <KEY_C>;
+			pinctrl-0 = <&pinctrl_dhcom_c>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-3 {
+			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
+			label = "TA4-GPIO-D";
+			linux,code = <KEY_D>;
+			pinctrl-0 = <&pinctrl_dhcom_d>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		/*
+		 * Disable led-5, because GPIO E is
+		 * already used as touch interrupt.
+		 */
+		led-5 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
+			pinctrl-0 = <&pinctrl_dhcom_e>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		led-6 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
+			pinctrl-0 = <&pinctrl_dhcom_f>;
+			pinctrl-names = "default";
+		};
+
+		led-7 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
+			pinctrl-0 = <&pinctrl_dhcom_h>;
+			pinctrl-names = "default";
+		};
+
+		led-8 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
+		};
+	};
+
+	panel {
+		backlight = <&display_bl>;
+		compatible = "edt,etm0700g0edh6";
+
+		port {
+			lcd_panel_in: endpoint {
+				remote-endpoint = <&lcd_display_out>;
+			};
+		};
+	};
+
+	sound {
+		audio-codec = <&sgtl5000>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"LINE_IN", "Line In Jack",
+			"Headphone Jack", "HP_OUT";
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx-sgtl5000";
+		mux-ext-port = <3>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
+	};
+};
+
+&audmux {
+	pinctrl-0 = <&pinctrl_audmux_ext>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&can2 {
+	status = "disabled";
+};
+
+/* 1G ethernet */
+/delete-node/ &ethphy0;
+&fec {
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy7>;
+	pinctrl-0 = <&pinctrl_enet_1G>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy7: ethernet-phy@7 { /* KSZ 9021 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio1>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy7>;
+			pinctrl-names = "default";
+			reg = <7>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+
+			rxc-skew-ps = <3000>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txc-skew-ps = <3000>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c2 {
+	sgtl5000: codec@a {
+		#sound-dai-cells = <0>;
+		clocks = <&clk_ext_audio_codec>;
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		VDDA-supply = <&reg_3p3v>;
+		VDDIO-supply = <&sw2_reg>;
+	};
+
+	touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		interrupt-parent = <&gpio4>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+		pinctrl-0 = <&pinctrl_dhcom_e>;
+		pinctrl-names = "default";
+		reg = <0x38>;
+	};
+};
+
+&ipu1_di0_disp0 {
+	remote-endpoint = <&lcd_display_in>;
+};
+
+&pcie {
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
+	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&usdhc2 { /* SD card */
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * A: key TA1
+			 * B: key TA2
+			 * C: key TA3
+			 * D: key TA4
+			 * E: touchscreen
+			 * F: led6
+			 * G: backlight enable
+			 * H: led7
+			 * I: led8
+			 * J: PCIe reset
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
+	pinctrl-names = "default";
+
+	pinctrl_audmux_ext: audmux-ext-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+		>;
+	};
+
+	pinctrl_enet_1G: enet-1G-grp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
+		>;
+	};
+
+	pinctrl_ethphy7: ethphy7-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38
+			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38
+			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
+			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38
+			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38
+			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38
+			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x38
+			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x38
+			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x38
+			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x38
+			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x38
+			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x38
+			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x38
+			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x38
+			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x38
+			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x38
+			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x38
+			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x38
+			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x38
+			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x38
+			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x38
+			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x38
+			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x38
+			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x38
+			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38
+			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38
+			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
similarity index 97%
rename from arch/arm/boot/dts/imx6q-dhcom-som.dtsi
rename to arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
index 99a275e06643..5d10c40313cb 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
@@ -4,7 +4,6 @@
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  */
 
-#include "imx6q.dtsi"
 #include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/imx6qdl-clock.h>
@@ -82,18 +81,20 @@
 &can1 {
 	pinctrl-0 = <&pinctrl_flexcan1>;
 	pinctrl-names = "default";
+	status = "okay";
 };
 
 /*
- * Special hardware required which uses the pins from micro SD card. The pins
- * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx
- * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board
- * device tree file, you also need to disable the micro SD card and the uart1
- * rts/cts have to be disabled or output on other DHCOM pins.
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
+ * the board device tree file, the micro SD card must be disabled and the uart1
+ * rts/cts must be disabled or output on other DHCOM pins.
  */
 &can2 {
 	pinctrl-0 = <&pinctrl_flexcan2>;
 	pinctrl-names = "default";
+	status = "disabled";
 };
 
 &ecspi1 {
@@ -116,7 +117,7 @@
 	cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
 	pinctrl-0 = <&pinctrl_ecspi2>;
 	pinctrl-names = "default";
-	status = "okay";
+	status = "disabled";
 };
 
 &fec {
@@ -334,6 +335,11 @@
 	pinctrl-names = "default";
 };
 
+&pwm1 {
+	pinctrl-0 = <&pinctrl_pwm1>;
+	pinctrl-names = "default";
+};
+
 &reg_arm {
 	vin-supply = <&sw3_reg>;
 };
@@ -400,7 +406,7 @@
 	keep-power-in-suspend;
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	pinctrl-names = "default";
-	status = "okay";
+	status = "disabled";
 };
 
 &usdhc3 { /* Micro SD card on module */
@@ -409,7 +415,7 @@
 	keep-power-in-suspend;
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-names = "default";
-	status = "disabled";
+	status = "okay";
 };
 
 &usdhc4 { /* eMMC on module */
@@ -672,6 +678,12 @@
 		>;
 	};
 
+	pinctrl_pwm1: pwm1-grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
+		>;
+	};
+
 	pinctrl_rtc: rtc-grp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120b0
-- 
2.11.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 14/15] ARM: dts: imx6qdl-dhcom: Add DHCOM based PicoITX board
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (11 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 13/15] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2 Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-14 21:07 ` [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board Christoph Niedermaier
                   ` (2 subsequent siblings)
  15 siblings, 0 replies; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Add DT for DH PicoITX unit, which is a bare-bones carrier board for
the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom
board-to-board expansion connector.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Replace the property label with the
      properties color and function
V4: - No changes
V5: - Include dt-bindings/leds/common.h file to carrier board file
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/Makefile                   |  1 +
 arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts   | 20 ++++++++
 arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi | 69 ++++++++++++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts
 create mode 100644 arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 863347b6b65e..ddca707019a5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -429,6 +429,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-cubox-i-emmc-som-v15.dtb \
 	imx6dl-cubox-i-som-v15.dtb \
 	imx6dl-dfi-fs700-m60.dtb \
+	imx6dl-dhcom-picoitx.dtb \
 	imx6dl-eckelmann-ci4x10.dtb \
 	imx6dl-emcon-avari.dtb \
 	imx6dl-gw51xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts
new file mode 100644
index 000000000000..038bb0025556
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PicoITX PCB number: 487-600 or newer
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-picoitx.dtsi"
+
+/ {
+	model = "DH electronics i.MX6DL DHCOM on PicoITX";
+	compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
+		     "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi
new file mode 100644
index 000000000000..4cd4cb9543c8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_YELLOW>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+&gpio1 {
+	gpio-line-names =
+		"", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
+		"", "", "", "", "", "", "", "",
+		"DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
+		"DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "",
+		"", "", "", "", "PicoITX-Out1", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "",
+		"", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&iomuxc {
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * I: yellow led
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
+	pinctrl-names = "default";
+};
-- 
2.11.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 30+ messages in thread

* [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (12 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 14/15] ARM: dts: imx6qdl-dhcom: Add DHCOM based PicoITX board Christoph Niedermaier
@ 2021-07-14 21:07 ` Christoph Niedermaier
  2021-07-18 15:33   ` Fabio Estevam
  2021-07-18 15:31 ` [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Fabio Estevam
  2021-07-23  3:56 ` Shawn Guo
  15 siblings, 1 reply; 30+ messages in thread
From: Christoph Niedermaier @ 2021-07-14 21:07 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Christoph Niedermaier, Shawn Guo, Fabio Estevam, Marek Vasut,
	NXP Linux Team, kernel

Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - No changes
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
---
 arch/arm/boot/dts/Makefile                 |   3 +-
 arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi | 139 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6s-dhcom-drc02.dts    |  32 +++++++
 3 files changed, 173 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi
 create mode 100644 arch/arm/boot/dts/imx6s-dhcom-drc02.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ddca707019a5..08a941836e84 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -608,7 +608,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6qp-tx6qp-8137-mb7.dtb \
 	imx6qp-vicutp.dtb \
 	imx6qp-wandboard-revd1.dtb \
-	imx6qp-zii-rdu2.dtb
+	imx6qp-zii-rdu2.dtb \
+	imx6s-dhcom-drc02.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
 	imx6sl-evk.dtb \
 	imx6sl-tolino-shine2hd.dtb \
diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi
new file mode 100644
index 000000000000..3d0a50a9ab21
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
+ * card must be disabled and the uart1 rts/cts must be output on other DHCOM
+ * pins, see uart1 and usdhc3 node below.
+ */
+&can2 {
+	status = "okay";
+};
+
+&gpio1 {
+	/*
+	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+	 * GPIO line, however the i.MX6 UART driver assumes RX happens
+	 * during TX anyway and that it only controls drive enable DE
+	 * line. Hence, the RX is always enabled here.
+	 */
+	rs485-rx-en-hog {
+		gpio-hog;
+		gpios = <18 0>; /* GPIO Q */
+		line-name = "rs485-rx-en";
+		output-low;
+	};
+};
+
+&gpio3 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "DRC02-In1", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
+		"DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
+		"", "", "", "", "DRC02-Out1", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
+		"", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&uart1 {
+	/*
+	 * Due to the use of can2 the signals for can2 Tx and Rx are routed to
+	 * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
+	 * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
+	 */
+	/delete-property/ uart-has-rtscts;
+	cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
+	pinctrl-names = "default";
+	rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+&uart5 {
+	/*
+	 * On DRC02 this UART is used as RS485 interface and RS485_TX_En is
+	 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
+	 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
+	 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
+	 * node above.
+	 */
+	/delete-property/ uart-has-rtscts;
+	linux,rs485-enabled-at-boot-time;
+	pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>;
+	pinctrl-names = "default";
+	rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+&usdhc2 { /* SD card */
+	status = "okay";
+};
+
+&usdhc3 {
+	/*
+	 * Due to the use of can2 the micro SD card on module have to be
+	 * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
+	 * can2 Tx and Rx.
+	 */
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * I: uart1 rts
+			 * M: uart1 cts
+			 * P: uart5 rs485-tx-en
+			 * Q: uart5 rs485-rx-en
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
+	pinctrl-names = "default";
+
+	pinctrl_uart5_core: uart5-core-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/imx6s-dhcom-drc02.dts b/arch/arm/boot/dts/imx6s-dhcom-drc02.dts
new file mode 100644
index 000000000000..e4daebbd4703
--- /dev/null
+++ b/arch/arm/boot/dts/imx6s-dhcom-drc02.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 493-400 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+/dts-v1/;
+
+/*
+ * The kernel only distinguishes between i.MX6 Quad and DualLite,
+ * but the Solo is actually a DualLite with only one CPU. So use
+ * DualLite for the Solo and disable one CPU node.
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-drc02.dtsi"
+
+/ {
+	model = "DH electronics i.MX6S DHCOM on DRC02";
+	compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
+		     "fsl,imx6dl";
+
+	cpus {
+		cpu@1 {
+			status = "disabled";
+		};
+	};
+};
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (13 preceding siblings ...)
  2021-07-14 21:07 ` [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board Christoph Niedermaier
@ 2021-07-18 15:31 ` Fabio Estevam
  2021-07-18 16:21   ` Marek Vasut
  2021-07-23  3:56 ` Shawn Guo
  15 siblings, 1 reply; 30+ messages in thread
From: Fabio Estevam @ 2021-07-18 15:31 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Shawn Guo, Marek Vasut, NXP Linux Team, kernel

Hi Christoph,

On 14/07/2021 18:06, Christoph Niedermaier wrote:

> +	/* OE pin of the latch is low active */
> +	reg_latch_oe_on: regulator-latch-oe-on {
> +		compatible = "regulator-fixed";
> +		gpio = <&gpio3 22 0>;

I understand that the GPIO polarity is ignored, but it would be better 
to
just describe the real polarity in the devicetree:

gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board
  2021-07-14 21:07 ` [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board Christoph Niedermaier
@ 2021-07-18 15:33   ` Fabio Estevam
  2021-07-18 16:04     ` Marek Vasut
  0 siblings, 1 reply; 30+ messages in thread
From: Fabio Estevam @ 2021-07-18 15:33 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Shawn Guo, Marek Vasut, NXP Linux Team, kernel

Hi Christoph,

On 14/07/2021 18:07, Christoph Niedermaier wrote:

> +/*
> + * The kernel only distinguishes between i.MX6 Quad and DualLite,
> + * but the Solo is actually a DualLite with only one CPU. So use
> + * DualLite for the Solo and disable one CPU node.
> + */
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-dhcom-som.dtsi"
> +#include "imx6qdl-dhcom-drc02.dtsi"
> +
> +/ {
> +	model = "DH electronics i.MX6S DHCOM on DRC02";
> +	compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
> +		     "fsl,imx6dl";
> +
> +	cpus {
> +		cpu@1 {
> +			status = "disabled";

There is no need for disabling cpu1 here. The kernel will read the
number of cores from the fuse and will bring-up the correct
number of CPU cores.

Other i.MX6Solo boards do not do this either.

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board
  2021-07-18 15:33   ` Fabio Estevam
@ 2021-07-18 16:04     ` Marek Vasut
  2021-07-23  7:08       ` Shawn Guo
  0 siblings, 1 reply; 30+ messages in thread
From: Marek Vasut @ 2021-07-18 16:04 UTC (permalink / raw)
  To: Fabio Estevam, Christoph Niedermaier
  Cc: linux-arm-kernel, Shawn Guo, NXP Linux Team, kernel

On 7/18/21 5:33 PM, Fabio Estevam wrote:
> Hi Christoph,
> 
> On 14/07/2021 18:07, Christoph Niedermaier wrote:
> 
>> +/*
>> + * The kernel only distinguishes between i.MX6 Quad and DualLite,
>> + * but the Solo is actually a DualLite with only one CPU. So use
>> + * DualLite for the Solo and disable one CPU node.
>> + */
>> +
>> +#include "imx6dl.dtsi"
>> +#include "imx6qdl-dhcom-som.dtsi"
>> +#include "imx6qdl-dhcom-drc02.dtsi"
>> +
>> +/ {
>> +    model = "DH electronics i.MX6S DHCOM on DRC02";
>> +    compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
>> +             "fsl,imx6dl";
>> +
>> +    cpus {
>> +        cpu@1 {
>> +            status = "disabled";
> 
> There is no need for disabling cpu1 here. The kernel will read the
> number of cores from the fuse and will bring-up the correct
> number of CPU cores.
> 
> Other i.MX6Solo boards do not do this either.

I would argue the above is more accurate, since this thing is supposed 
to be populated only with MX6 Solo. Even better might be to 
/delete-node/ cpu@1 in fact.

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus
  2021-07-18 15:31 ` [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Fabio Estevam
@ 2021-07-18 16:21   ` Marek Vasut
  0 siblings, 0 replies; 30+ messages in thread
From: Marek Vasut @ 2021-07-18 16:21 UTC (permalink / raw)
  To: Fabio Estevam, Christoph Niedermaier
  Cc: linux-arm-kernel, Shawn Guo, NXP Linux Team, kernel,
	Linus Walleij, Mark Brown

On 7/18/21 5:31 PM, Fabio Estevam wrote:
> Hi Christoph,
> 
> On 14/07/2021 18:06, Christoph Niedermaier wrote:
> 
>> +    /* OE pin of the latch is low active */
>> +    reg_latch_oe_on: regulator-latch-oe-on {
>> +        compatible = "regulator-fixed";
>> +        gpio = <&gpio3 22 0>;
> 
> I understand that the GPIO polarity is ignored, but it would be better to
> just describe the real polarity in the devicetree:
> 
> gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;

The 0 is correct as the field is ignored, please keep it.

Any other variants (like GPIO_ACTIVE_LOW = 1) interact badly with
drivers/gpio/gpiolib-of.c of_gpio_flags_quirks()
which is already a total compatibility attempt mess and lead to odd 
misbehavior of the regulator where the polarity of the GPIO is randomly 
interpreted as low or high dependent on the kernel version.

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus
  2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
                   ` (14 preceding siblings ...)
  2021-07-18 15:31 ` [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Fabio Estevam
@ 2021-07-23  3:56 ` Shawn Guo
  15 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  3:56 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:06:59PM +0200, Christoph Niedermaier wrote:
> Add the parallel system bus provided by the i.MX6 WEIM interface via an
> address latch. The OE pin of the latch is controlled by a fixed regulator.
> The pin is low active. This is ensured by omitting the regulators property
> enable-active-high. The flags value of the gpio property (3rd value), which
> is also use to define active high/low, is set to 0 because it is ignored
> by gpiolib-of.c.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY
  2021-07-14 21:07 ` [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Christoph Niedermaier
@ 2021-07-23  3:59   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  3:59 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:00PM +0200, Christoph Niedermaier wrote:
> Enable the interrupt mode for the ethernet PHY by adding the
> necessary property and a separate pinctrl for the PHY. Also
> add the compatible property for it.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM
  2021-07-14 21:07 ` [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM Christoph Niedermaier
@ 2021-07-23  4:01   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  4:01 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:01PM +0200, Christoph Niedermaier wrote:
> Fill in the custom GPIO line names used by DH on the DHCOM SoM.
> The GPIO line names are in accordance to DHCOM Design Guide R04
> available at [1], section 3.9 GPIO. Adding also GPIO line names
> for the hardware and memory coding.
> 
> [1] https://wiki.dh-electronics.com/images/5/52/DOC_DHCOM-Design-Guide_R04_2018-06-28.pdf
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl
  2021-07-14 21:07 ` [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl Christoph Niedermaier
@ 2021-07-23  4:03   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  4:03 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:02PM +0200, Christoph Niedermaier wrote:
> The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to
> the SoM devicetree. Add PCIe Reset GPIO to the board devicetree.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs
  2021-07-14 21:07 ` [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs Christoph Niedermaier
@ 2021-07-23  4:06   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  4:06 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:03PM +0200, Christoph Niedermaier wrote:
> Set stdout-path to "serial0:15200n8" to align it with other DHCOM
> SoMs like the DHCOM STM32MP1.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board
  2021-07-14 21:07 ` [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board Christoph Niedermaier
@ 2021-07-23  4:07   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  4:07 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:04PM +0200, Christoph Niedermaier wrote:
> On the PDK2 there are 4 keys and 4 leds. DHCOM GPIOs are
> used for that, but one led isn't useable, because the GPIO
> is already used as touch interrupt.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
  2021-07-14 21:07 ` [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on " Christoph Niedermaier
@ 2021-07-23  6:30   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  6:30 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:05PM +0200, Christoph Niedermaier wrote:
> The PDK2 board is capable of running both 100M and 1G ethernet. However,
> the i.MX6 has only one ethernet MAC, so it is possible to configure
> either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
> SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
> the PDK2 board with another RJ45 port. 100M and 1G ethernet use
> different signal pins from the i.MX6, but share the MDIO bus.
> 
> This SoM board combination is used to demonstrate how to enable 1G
> ethernet configuration.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Rebase on Shawn Guos branch for-next
> V3: - Rework of the commit message
>     - Remove superfluous property max-speed
> V4: - No changes
> V5: - No changes
> V6: - Rebase on 5.14-rc1
> ---
>  arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 51 ++++++++++++++++++++++++++++++++--
>  1 file changed, 48 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> index 4d455831b3ca..3b0276de41f9 100644
> --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> @@ -173,6 +173,46 @@
>  	status = "disabled";
>  };
>  
> +/* 1G ethernet */
> +/delete-node/ &ethphy0;
> +&fec {
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy7>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet_1G>;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy7: ethernet-phy@7 { /* KSZ 9021 */
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			interrupt-parent = <&gpio1>;
> +			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> +			pinctrl-0 = <&pinctrl_ethphy7>;
> +			pinctrl-names = "default";
> +			reg = <7>;
> +			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <1000>;
> +			reset-deassert-us = <1000>;
> +

Unnecessary newline in property list.

Shawn

> +			rxc-skew-ps = <3000>;
> +			rxd0-skew-ps = <0>;
> +			rxd1-skew-ps = <0>;
> +			rxd2-skew-ps = <0>;
> +			rxd3-skew-ps = <0>;
> +			txc-skew-ps = <3000>;
> +			txd0-skew-ps = <0>;
> +			txd1-skew-ps = <0>;
> +			txd2-skew-ps = <0>;
> +			txd3-skew-ps = <0>;
> +			rxdv-skew-ps = <0>;
> +			txen-skew-ps = <0>;
> +		};
> +	};
> +};
> +
>  &hdmi {
>  	ddc-i2c-bus = <&i2c2>;
>  	status = "okay";
> @@ -255,9 +295,14 @@
>  			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
>  			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
>  			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
> -			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x000b0
> -			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x000b1
> -			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x000b1
> +		>;
> +	};
> +
> +	pinctrl_ethphy7: ethphy7-grp {
> +		fsl,pins = <
> +			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
> +			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
> +			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
>  		>;
>  	};
>  
> -- 
> 2.11.0
> 

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls
  2021-07-14 21:07 ` [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls Christoph Niedermaier
@ 2021-07-23  6:40   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  6:40 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:06PM +0200, Christoph Niedermaier wrote:
> Define each DHCOM GPIO as a separate pinctrl. So on board layer it is
> possible to easily add an used DHCOM GPIO by moving &pinctrl_dhcom_X
> from the gpio hog list to the appropriate driver pinctrl.

I'm not sure this is a good idea. Each board should define the pinctrl
for GPIO as per how it's used on the board.

Shawn

> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Rebase on Shawn Guos branch for-next
> V3: - No changes
> V4: - No changes
> V5: - No changes
> V6: - Rebase on 5.14-rc1
> ---
>  arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 105 ++++++++++++-------------------
>  arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 109 ++++++++++++++++++++++++++++++++-
>  2 files changed, 148 insertions(+), 66 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> index 3b0276de41f9..8122db759880 100644
> --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
> @@ -38,7 +38,7 @@
>  		#size-cells = <0>;
>  		interface-pix-fmt = "rgb24";
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
> +		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
>  		status = "okay";
>  
>  		port@0 {
> @@ -61,13 +61,13 @@
>  	gpio-keys {
>  		#size-cells = <0>;
>  		compatible = "gpio-keys";
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_keys_pdk2>;
>  
>  		button-0 {
>  			label = "TA1-GPIO-A";
>  			linux,code = <KEY_A>;
>  			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
> +			pinctrl-0 = <&pinctrl_dhcom_a>;
> +			pinctrl-names = "default";
>  			wakeup-source;
>  		};
>  
> @@ -75,6 +75,8 @@
>  			label = "TA2-GPIO-B";
>  			linux,code = <KEY_B>;
>  			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> +			pinctrl-0 = <&pinctrl_dhcom_b>;
> +			pinctrl-names = "default";
>  			wakeup-source;
>  		};
>  
> @@ -82,6 +84,8 @@
>  			label = "TA3-GPIO-C";
>  			linux,code = <KEY_C>;
>  			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
> +			pinctrl-0 = <&pinctrl_dhcom_c>;
> +			pinctrl-names = "default";
>  			wakeup-source;
>  		};
>  
> @@ -89,14 +93,14 @@
>  			label = "TA4-GPIO-D";
>  			linux,code = <KEY_D>;
>  			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
> +			pinctrl-0 = <&pinctrl_dhcom_d>;
> +			pinctrl-names = "default";
>  			wakeup-source;
>  		};
>  	};
>  
>  	led {
>  		compatible = "gpio-leds";
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_leds_pdk2>;
>  
>  		/*
>  		 * Disable led-5, because GPIO E is
> @@ -107,6 +111,8 @@
>  			function = LED_FUNCTION_INDICATOR;
>  			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
>  			default-state = "off";
> +			pinctrl-0 = <&pinctrl_dhcom_e>;
> +			pinctrl-names = "default";
>  			status = "disabled";
>  		};
>  
> @@ -115,6 +121,8 @@
>  			function = LED_FUNCTION_INDICATOR;
>  			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
>  			default-state = "off";
> +			pinctrl-0 = <&pinctrl_dhcom_f>;
> +			pinctrl-names = "default";
>  		};
>  
>  		led-7 {
> @@ -122,6 +130,8 @@
>  			function = LED_FUNCTION_INDICATOR;
>  			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
>  			default-state = "off";
> +			pinctrl-0 = <&pinctrl_dhcom_h>;
> +			pinctrl-names = "default";
>  		};
>  
>  		led-8 {
> @@ -129,6 +139,8 @@
>  			function = LED_FUNCTION_INDICATOR;
>  			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
>  			default-state = "off";
> +			pinctrl-0 = <&pinctrl_dhcom_i>;
> +			pinctrl-names = "default";
>  		};
>  	};
>  
> @@ -230,7 +242,7 @@
>  
>  	touchscreen@38 {
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_touchscreen>;
> +		pinctrl-0 = <&pinctrl_dhcom_e>;
>  		compatible = "edt,edt-ft5406";
>  		reg = <0x38>;
>  		interrupt-parent = <&gpio4>;
> @@ -240,34 +252,28 @@
>  
>  &iomuxc {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
> -
> -	pinctrl_hog: hog-grp {
> -		fsl,pins = <
> -			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x400120b0
> -			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x400120b0
> -			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x400120b0
> -			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0
> -			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x400120b0
> -			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0
> -			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x400120b0
> -			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0
> -			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0
> -			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x400120b0
> -			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x400120b0
> -			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x400120b0
> -			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0
> -			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x400120b0
> -			MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0x400120b0
> -			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16		0x400120b0
> -			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17		0x400120b0
> -			MX6QDL_PAD_SD1_DAT2__GPIO1_IO19		0x400120b0
> -			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x400120b0
> -			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0
> -			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0
> -			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x400120b0
> +	pinctrl-0 = <
> +			/*
> +			 * The following DHCOM GPIOs are used on this board.
> +			 * Therefore, they have been removed from the list below.
> +			 * A: key TA1
> +			 * B: key TA2
> +			 * C: key TA3
> +			 * D: key TA4
> +			 * E: touchscreen
> +			 * F: led6
> +			 * G: backlight enable
> +			 * H: led7
> +			 * I: led8
> +			 * J: PCIe reset
> +			 */
> +			&pinctrl_hog_base
> +			&pinctrl_dhcom_k &pinctrl_dhcom_l
> +			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
> +			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
> +			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
> +			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>  		>;
> -	};
>  
>  	pinctrl_audmux_ext: audmux-ext-grp {
>  		fsl,pins = <
> @@ -336,7 +342,6 @@
>  			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38
>  			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38
>  			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38
> -			MX6QDL_PAD_EIM_D27__GPIO3_IO27			0x120b0
>  		>;
>  	};
>  
> @@ -345,36 +350,6 @@
>  			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
>  		>;
>  	};
> -
> -	pinctrl_touchscreen: touchscreen-grp {
> -		fsl,pins = <
> -			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b1
> -		>;
> -	};
> -
> -	pinctrl_pcie_reset: pcie-reset-grp {
> -		fsl,pins = <
> -			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
> -		>;
> -	};
> -
> -	pinctrl_keys_pdk2: keys-pdk2-grp {
> -		fsl,pins = <
> -			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x120b0 /* TA1 */
> -			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x120b0 /* TA2 */
> -			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x120b0 /* TA3 */
> -			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x120b0 /* TA4 */
> -		>;
> -	};
> -
> -	pinctrl_leds_pdk2: leds-pdk2-grp {
> -		fsl,pins = <
> -			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x120b0 /* led6 */
> -			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0 /* led7 */
> -			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x120b0 /* led8 */
> -		>;
> -	};
> -
>  };
>  
>  &ipu1_di0_disp0 {
> @@ -382,7 +357,7 @@
>  };
>  
>  &pcie {
> -	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
> +	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
>  	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
> index c5c060c6b9bf..9fd48ab9b3d0 100644
> --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
> +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
> @@ -317,7 +317,17 @@
>  
>  &iomuxc {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_hog_base>;
> +	pinctrl-0 = <
> +			&pinctrl_hog_base
> +			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
> +			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
> +			&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
> +			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
> +			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
> +			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
> +			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
> +			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
> +		>;
>  
>  	pinctrl_hog_base: hog-base-grp {
>  		fsl,pins = <
> @@ -329,6 +339,103 @@
>  		>;
>  	};
>  
> +	/* DHCOM GPIOs */
> +	pinctrl_dhcom_a: dhcom-a-grp {
> +		fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_b: dhcom-b-grp {
> +		fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_c: dhcom-c-grp {
> +		fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_d: dhcom-d-grp {
> +		fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_e: dhcom-e-grp {
> +		fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_f: dhcom-f-grp {
> +		fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_g: dhcom-g-grp {
> +		fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_h: dhcom-h-grp {
> +		fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_i: dhcom-i-grp {
> +		fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_j: dhcom-j-grp {
> +		fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_k: dhcom-k-grp {
> +		fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_l: dhcom-l-grp {
> +		fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_m: dhcom-m-grp {
> +		fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_n: dhcom-n-grp {
> +		fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_o: dhcom-o-grp {
> +		fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_p: dhcom-p-grp {
> +		fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_q: dhcom-q-grp {
> +		fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_r: dhcom-r-grp {
> +		fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_s: dhcom-s-grp {
> +		fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_t: dhcom-t-grp {
> +		fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_u: dhcom-u-grp {
> +		fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_v: dhcom-v-grp {
> +		fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_w: dhcom-w-grp {
> +		fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0>;
> +	};
> +
> +	pinctrl_dhcom_int: dhcom-int-grp {
> +		fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06	0x400120b0>;
> +	};
> +
>  	pinctrl_ecspi1: ecspi1-grp {
>  		fsl,pins = <
>  			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
> -- 
> 2.11.0
> 

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property
  2021-07-14 21:07 ` [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property Christoph Niedermaier
@ 2021-07-23  6:41   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  6:41 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:07PM +0200, Christoph Niedermaier wrote:
> An EDID lookup is not needed with this panel.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants
  2021-07-14 21:07 ` [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants Christoph Niedermaier
@ 2021-07-23  6:48   ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  6:48 UTC (permalink / raw)
  To: Christoph Niedermaier
  Cc: linux-arm-kernel, Fabio Estevam, Marek Vasut, NXP Linux Team, kernel

On Wed, Jul 14, 2021 at 11:07:08PM +0200, Christoph Niedermaier wrote:
> The minimum available memory size of all DHCOM i.MX6 variants is 512 MB.
> Set this value for the memory node. If U-Boot fails to fill the memory
> size, at least all DHCOM i.MX6 variants should run without problems.
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!

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^ permalink raw reply	[flat|nested] 30+ messages in thread

* Re: [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board
  2021-07-18 16:04     ` Marek Vasut
@ 2021-07-23  7:08       ` Shawn Guo
  0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2021-07-23  7:08 UTC (permalink / raw)
  To: Marek Vasut
  Cc: Fabio Estevam, Christoph Niedermaier, linux-arm-kernel,
	NXP Linux Team, kernel

On Sun, Jul 18, 2021 at 06:04:13PM +0200, Marek Vasut wrote:
> On 7/18/21 5:33 PM, Fabio Estevam wrote:
> > Hi Christoph,
> > 
> > On 14/07/2021 18:07, Christoph Niedermaier wrote:
> > 
> > > +/*
> > > + * The kernel only distinguishes between i.MX6 Quad and DualLite,
> > > + * but the Solo is actually a DualLite with only one CPU. So use
> > > + * DualLite for the Solo and disable one CPU node.
> > > + */
> > > +
> > > +#include "imx6dl.dtsi"
> > > +#include "imx6qdl-dhcom-som.dtsi"
> > > +#include "imx6qdl-dhcom-drc02.dtsi"
> > > +
> > > +/ {
> > > +    model = "DH electronics i.MX6S DHCOM on DRC02";
> > > +    compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
> > > +             "fsl,imx6dl";
> > > +
> > > +    cpus {
> > > +        cpu@1 {
> > > +            status = "disabled";
> > 
> > There is no need for disabling cpu1 here. The kernel will read the
> > number of cores from the fuse and will bring-up the correct
> > number of CPU cores.
> > 
> > Other i.MX6Solo boards do not do this either.
> 
> I would argue the above is more accurate, since this thing is supposed to be
> populated only with MX6 Solo. Even better might be to /delete-node/ cpu@1 in
> fact.

Yes, if you want to get the description accurate, /delete-node/ might be
the right choice.

Shawn

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^ permalink raw reply	[flat|nested] 30+ messages in thread

end of thread, other threads:[~2021-07-23  7:09 UTC | newest]

Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-14 21:06 [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Christoph Niedermaier
2021-07-14 21:07 ` [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Christoph Niedermaier
2021-07-23  3:59   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 03/15] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM Christoph Niedermaier
2021-07-23  4:01   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl Christoph Niedermaier
2021-07-23  4:03   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 05/15] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs Christoph Niedermaier
2021-07-23  4:06   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 06/15] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board Christoph Niedermaier
2021-07-23  4:07   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 07/15] ARM: dts: imx6q-dhcom: Use 1G ethernet on " Christoph Niedermaier
2021-07-23  6:30   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 08/15] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls Christoph Niedermaier
2021-07-23  6:40   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 09/15] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property Christoph Niedermaier
2021-07-23  6:41   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 10/15] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants Christoph Niedermaier
2021-07-23  6:48   ` Shawn Guo
2021-07-14 21:07 ` [PATCH V6 11/15] ARM: dts: imx6q-dhcom: Rearrange of iomux Christoph Niedermaier
2021-07-14 21:07 ` [PATCH V6 12/15] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees Christoph Niedermaier
2021-07-14 21:07 ` [PATCH V6 13/15] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2 Christoph Niedermaier
2021-07-14 21:07 ` [PATCH V6 14/15] ARM: dts: imx6qdl-dhcom: Add DHCOM based PicoITX board Christoph Niedermaier
2021-07-14 21:07 ` [PATCH V6 15/15] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board Christoph Niedermaier
2021-07-18 15:33   ` Fabio Estevam
2021-07-18 16:04     ` Marek Vasut
2021-07-23  7:08       ` Shawn Guo
2021-07-18 15:31 ` [PATCH V6 01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus Fabio Estevam
2021-07-18 16:21   ` Marek Vasut
2021-07-23  3:56 ` Shawn Guo

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