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From: Peter Maydell <>
Subject: [PATCH for-6.1 3/6] target/arm: Report M-profile alignment faults correctly to the guest
Date: Fri, 23 Jul 2021 17:21:43 +0100	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

For M-profile, we weren't reporting alignment faults triggered by the
generic TCG code correctly to the guest.  These get passed into
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
style exception.fsr value of 1.  We didn't check for this, and so
they fell through into the default of "assume this is an MPU fault"
and were reported to the guest as a data access violation MPU fault.

Report these alignment faults as UsageFaults which set the UNALIGNED
bit in the UFSR.

Signed-off-by: Peter Maydell <>
The other approach would be to have arm_cpu_do_unaligned_access()
raise the EXCP_UNALIGNED which we already use for Unaligned
UsageFaults which are raised by m-profile specific helper code,
but I think this way is in line with the current design that
generally prefers to report exception information in an A-profile
format and then re-arrange that into the M-profile information
in arm_v7m_cpu_do_interrupt().
 target/arm/m_helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index f352346a964..20761c94877 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2248,6 +2248,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
         env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
+        /* Unaligned faults reported by M-profile aware code */
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->;
         env->v7m.cfsr[env->] |= R_V7M_CFSR_UNALIGNED_MASK;
@@ -2320,6 +2321,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
             armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
+        case 0x1: /* Alignment fault reported by generic code */
+            qemu_log_mask(CPU_LOG_INT,
+                          "...really UsageFault with UFSR.UNALIGNED\n");
+            env->v7m.cfsr[env->] |= R_V7M_CFSR_UNALIGNED_MASK;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+                                    env->;
+            break;
              * All other FSR values are either MPU faults or "can't happen

  parent reply	other threads:[~2021-07-23 16:26 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-23 16:21 [PATCH for-6.1 0/6] arm: Fix a handful of M-profile bugs Peter Maydell
2021-07-23 16:21 ` [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero Peter Maydell
2021-07-25 18:14   ` Richard Henderson
2021-07-23 16:21 ` [PATCH for-6.1 2/6] target/arm: Add missing 'return's after calling v7m_exception_taken() Peter Maydell
2021-07-25 18:15   ` Richard Henderson
2021-07-23 16:21 ` Peter Maydell [this message]
2021-07-25 18:16   ` [PATCH for-6.1 3/6] target/arm: Report M-profile alignment faults correctly to the guest Richard Henderson
2021-07-23 16:21 ` [PATCH for-6.1 4/6] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts Peter Maydell
2021-07-25 18:18   ` Richard Henderson
2021-07-23 16:21 ` [PATCH for-6.1 5/6] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING Peter Maydell
2021-07-25 18:18   ` Richard Henderson
2021-07-23 16:21 ` [PATCH for-6.1 6/6] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS Peter Maydell
2021-07-25 18:23   ` Richard Henderson

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