From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FB29C4338F for ; Fri, 23 Jul 2021 22:51:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B61960F36 for ; Fri, 23 Jul 2021 22:51:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233205AbhGWWKc (ORCPT ); Fri, 23 Jul 2021 18:10:32 -0400 Received: from mail-il1-f170.google.com ([209.85.166.170]:35689 "EHLO mail-il1-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233064AbhGWWKa (ORCPT ); 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Fri, 23 Jul 2021 15:51:03 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id m184sm18795821ioa.17.2021.07.23.15.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 15:51:02 -0700 (PDT) Received: (nullmailer pid 2750265 invoked by uid 1000); Fri, 23 Jul 2021 22:50:59 -0000 Date: Fri, 23 Jul 2021 16:50:59 -0600 From: Rob Herring To: Mauro Carvalho Chehab Cc: Vinod Koul , Bjorn Helgaas , linuxarm@huawei.com, mauro.chehab@huawei.com, Kishon Vijay Abraham I , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v7 06/10] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Message-ID: <20210723225059.GA2727093@robh.at.kernel.org> References: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 21, 2021 at 10:39:08AM +0200, Mauro Carvalho Chehab wrote: > Document the bindings for HiKey 970 (hi3670) PCIe PHY > interface, supported via the pcie-kirin driver. > > Signed-off-by: Mauro Carvalho Chehab > --- > .../phy/hisilicon,phy-hi3670-pcie.yaml | 95 +++++++++++++++++++ > 1 file changed, 95 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > new file mode 100644 > index 000000000000..a5ea13332cac > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > @@ -0,0 +1,95 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: HiSilicon Kirin970 PCIe PHY > + > +maintainers: > + - Mauro Carvalho Chehab > + > +description: |+ > + Bindings for PCIe PHY on HiSilicon Kirin 970. > + > +properties: > + compatible: > + const: hisilicon,hi970-pcie-phy > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + description: PHY Control registers > + > + phy-supply: > + description: The PCIe PHY power supply > + > + clocks: > + items: > + - description: PCIe PHY clock > + - description: PCIe AUX clock > + - description: PCIe APB PHY clock > + - description: PCIe APB SYS clock > + - description: PCIe ACLK clock > + > + clock-names: > + items: > + - const: phy_ref > + - const: aux > + - const: apb_phy > + - const: apb_sys > + - const: aclk > + > + reset-gpios: > + description: PCI PERST reset GPIOs > + maxItems: 4 > + > + clkreq-gpios: > + description: Clock request GPIOs > + maxItems: 3 Again, this will not work. It boils down to this fails to describe how the GPIOs are connected which is the point of GPIOs in DT. This in no way captures the hierarchy of devices. While you may be lucky that you can just assert or deassert all the lines at one time, that's not likely to work in a more complicated case (such as having to power up/down each device). I realize the right solution is more complex, but that's the only way to handle this in a host bridge and board independent way. If you want the simple solution, just configure all these GPIOs in firmware before Linux boots. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 361FCC4338F for ; Fri, 23 Jul 2021 22:51:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EFE7D60F41 for ; Fri, 23 Jul 2021 22:51:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EFE7D60F41 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; 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Fri, 23 Jul 2021 15:51:03 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id m184sm18795821ioa.17.2021.07.23.15.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 15:51:02 -0700 (PDT) Received: (nullmailer pid 2750265 invoked by uid 1000); Fri, 23 Jul 2021 22:50:59 -0000 Date: Fri, 23 Jul 2021 16:50:59 -0600 From: Rob Herring To: Mauro Carvalho Chehab Cc: Vinod Koul , Bjorn Helgaas , linuxarm@huawei.com, mauro.chehab@huawei.com, Kishon Vijay Abraham I , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v7 06/10] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Message-ID: <20210723225059.GA2727093@robh.at.kernel.org> References: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210723_155103_704745_0F03199D X-CRM114-Status: GOOD ( 18.54 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Wed, Jul 21, 2021 at 10:39:08AM +0200, Mauro Carvalho Chehab wrote: > Document the bindings for HiKey 970 (hi3670) PCIe PHY > interface, supported via the pcie-kirin driver. > > Signed-off-by: Mauro Carvalho Chehab > --- > .../phy/hisilicon,phy-hi3670-pcie.yaml | 95 +++++++++++++++++++ > 1 file changed, 95 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > new file mode 100644 > index 000000000000..a5ea13332cac > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml > @@ -0,0 +1,95 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: HiSilicon Kirin970 PCIe PHY > + > +maintainers: > + - Mauro Carvalho Chehab > + > +description: |+ > + Bindings for PCIe PHY on HiSilicon Kirin 970. > + > +properties: > + compatible: > + const: hisilicon,hi970-pcie-phy > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + description: PHY Control registers > + > + phy-supply: > + description: The PCIe PHY power supply > + > + clocks: > + items: > + - description: PCIe PHY clock > + - description: PCIe AUX clock > + - description: PCIe APB PHY clock > + - description: PCIe APB SYS clock > + - description: PCIe ACLK clock > + > + clock-names: > + items: > + - const: phy_ref > + - const: aux > + - const: apb_phy > + - const: apb_sys > + - const: aclk > + > + reset-gpios: > + description: PCI PERST reset GPIOs > + maxItems: 4 > + > + clkreq-gpios: > + description: Clock request GPIOs > + maxItems: 3 Again, this will not work. It boils down to this fails to describe how the GPIOs are connected which is the point of GPIOs in DT. This in no way captures the hierarchy of devices. While you may be lucky that you can just assert or deassert all the lines at one time, that's not likely to work in a more complicated case (such as having to power up/down each device). I realize the right solution is more complex, but that's the only way to handle this in a host bridge and board independent way. If you want the simple solution, just configure all these GPIOs in firmware before Linux boots. Rob -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy