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MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 24 Jul 2021 16:18:54 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 24 Jul 2021 16:18:53 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 3/5] pwm: mtk_disp: implement atomic API .apply() Date: Sat, 24 Jul 2021 16:18:47 +0800 Message-ID: <20210724081849.182108-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com> References: <20210724081849.182108-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 84B648C66343D480554DDA935607FA7ECB21D8A66B80C5C70D1FDDEB5C1E63982000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org U3dpdGNoIHRoZSBkcml2ZXIgdG8gc3VwcG9ydCB0aGUgLmFwcGx5KCkgbWV0aG9kLg0KDQpTaWdu ZWQtb2ZmLWJ5OiBKaXRhbyBTaGkgPGppdGFvLnNoaUBtZWRpYXRlay5jb20+DQotLS0NCiBkcml2 ZXJzL3B3bS9wd20tbXRrLWRpc3AuYyB8IDkzICsrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0t LS0tLS0tLS0tDQogMSBmaWxlIGNoYW5nZWQsIDM4IGluc2VydGlvbnMoKyksIDU1IGRlbGV0aW9u cygtKQ0KDQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9wd20vcHdtLW10ay1kaXNwLmMgYi9kcml2ZXJz L3B3bS9wd20tbXRrLWRpc3AuYw0KaW5kZXggMTA3MGQ3OGQ0OTQwLi41OTlkN2RkOGVjYWIgMTAw NjQ0DQotLS0gYS9kcml2ZXJzL3B3bS9wd20tbXRrLWRpc3AuYw0KKysrIGIvZHJpdmVycy9wd20v cHdtLW10ay1kaXNwLmMNCkBAIC00Nyw2ICs0Nyw3IEBAIHN0cnVjdCBtdGtfZGlzcF9wd20gew0K IAlzdHJ1Y3QgY2xrICpjbGtfbWFpbjsNCiAJc3RydWN0IGNsayAqY2xrX21tOw0KIAl2b2lkIF9f aW9tZW0gKmJhc2U7DQorCWJvb2wgZW5hYmxlZDsNCiB9Ow0KIA0KIHN0YXRpYyBpbmxpbmUgc3Ry dWN0IG10a19kaXNwX3B3bSAqdG9fbXRrX2Rpc3BfcHdtKHN0cnVjdCBwd21fY2hpcCAqY2hpcCkN CkBAIC02NiwyNSArNjcsNDIgQEAgc3RhdGljIHZvaWQgbXRrX2Rpc3BfcHdtX3VwZGF0ZV9iaXRz KHN0cnVjdCBtdGtfZGlzcF9wd20gKm1kcCwgdTMyIG9mZnNldCwNCiAJd3JpdGVsKHZhbHVlLCBh ZGRyZXNzKTsNCiB9DQogDQotc3RhdGljIGludCBtdGtfZGlzcF9wd21fY29uZmlnKHN0cnVjdCBw d21fY2hpcCAqY2hpcCwgc3RydWN0IHB3bV9kZXZpY2UgKnB3bSwNCi0JCQkgICAgICAgaW50IGR1 dHlfbnMsIGludCBwZXJpb2RfbnMpDQorc3RhdGljIGludCBtdGtfZGlzcF9wd21fYXBwbHkoc3Ry dWN0IHB3bV9jaGlwICpjaGlwLCBzdHJ1Y3QgcHdtX2RldmljZSAqcHdtLA0KKwkJCSAgICAgIGNv bnN0IHN0cnVjdCBwd21fc3RhdGUgKnN0YXRlKQ0KIHsNCiAJc3RydWN0IG10a19kaXNwX3B3bSAq bWRwID0gdG9fbXRrX2Rpc3BfcHdtKGNoaXApOw0KIAl1MzIgY2xrX2RpdiwgcGVyaW9kLCBoaWdo X3dpZHRoLCB2YWx1ZTsNCiAJdTY0IGRpdiwgcmF0ZTsNCiAJaW50IGVycjsNCiANCi0JZXJyID0g Y2xrX3ByZXBhcmVfZW5hYmxlKG1kcC0+Y2xrX21haW4pOw0KLQlpZiAoZXJyIDwgMCkgew0KLQkJ ZGV2X2VycihjaGlwLT5kZXYsICJDYW4ndCBlbmFibGUgbWRwLT5jbGtfbWFpbjogJXBlXG4iLCBF UlJfUFRSKGVycikpOw0KLQkJcmV0dXJuIGVycjsNCisJaWYgKHN0YXRlLT5wb2xhcml0eSAhPSBQ V01fUE9MQVJJVFlfTk9STUFMKQ0KKwkJcmV0dXJuIC1FSU5WQUw7DQorDQorCWlmICghc3RhdGUt PmVuYWJsZWQpIHsNCisJCW10a19kaXNwX3B3bV91cGRhdGVfYml0cyhtZHAsIERJU1BfUFdNX0VO LCBtZHAtPmRhdGEtPmVuYWJsZV9tYXNrLA0KKwkJCQkJIDB4MCk7DQorCQlpZiAobWRwLT5lbmFi bGVkKSB7DQorCQkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKG1kcC0+Y2xrX21tKTsNCisJCQljbGtf ZGlzYWJsZV91bnByZXBhcmUobWRwLT5jbGtfbWFpbik7DQorCQl9DQorCQltZHAtPmVuYWJsZWQg PSBmYWxzZTsNCisJCXJldHVybiAwOw0KIAl9DQogDQotCWVyciA9IGNsa19wcmVwYXJlX2VuYWJs ZShtZHAtPmNsa19tbSk7DQotCWlmIChlcnIgPCAwKSB7DQotCQlkZXZfZXJyKGNoaXAtPmRldiwg IkNhbid0IGVuYWJsZSBtZHAtPmNsa19tbTogJXBlXG4iLCBFUlJfUFRSKGVycikpOw0KLQkJY2xr X2Rpc2FibGVfdW5wcmVwYXJlKG1kcC0+Y2xrX21haW4pOw0KLQkJcmV0dXJuIGVycjsNCisJaWYg KCFtZHAtPmVuYWJsZWQpIHsNCisJCWVyciA9IGNsa19wcmVwYXJlX2VuYWJsZShtZHAtPmNsa19t YWluKTsNCisJCWlmIChlcnIgPCAwKSB7DQorCQkJZGV2X2VycihjaGlwLT5kZXYsICJDYW4ndCBl bmFibGUgbWRwLT5jbGtfbWFpbjogJXBlXG4iLA0KKwkJCQlFUlJfUFRSKGVycikpOw0KKwkJCXJl dHVybiBlcnI7DQorCQl9DQorCQllcnIgPSBjbGtfcHJlcGFyZV9lbmFibGUobWRwLT5jbGtfbW0p Ow0KKwkJaWYgKGVyciA8IDApIHsNCisJCQlkZXZfZXJyKGNoaXAtPmRldiwgIkNhbid0IGVuYWJs ZSBtZHAtPmNsa19tbTogJXBlXG4iLA0KKwkJCQlFUlJfUFRSKGVycikpOw0KKwkJCWNsa19kaXNh YmxlX3VucHJlcGFyZShtZHAtPmNsa19tYWluKTsNCisJCQlyZXR1cm4gZXJyOw0KKwkJfQ0KIAl9 DQogDQogCS8qDQpAQCAtOTgsMjAgKzExNiwyMiBAQCBzdGF0aWMgaW50IG10a19kaXNwX3B3bV9j b25maWcoc3RydWN0IHB3bV9jaGlwICpjaGlwLCBzdHJ1Y3QgcHdtX2RldmljZSAqcHdtLA0KIAkg KiBoaWdoX3dpZHRoID0gKFBXTV9DTEtfUkFURSAqIGR1dHlfbnMpIC8gKDEwXjkgKiAoY2xrX2Rp diArIDEpKQ0KIAkgKi8NCiAJcmF0ZSA9IGNsa19nZXRfcmF0ZShtZHAtPmNsa19tYWluKTsNCi0J Y2xrX2RpdiA9IGRpdl91NjQocmF0ZSAqIHBlcmlvZF9ucywgTlNFQ19QRVJfU0VDKSA+Pg0KKwlj bGtfZGl2ID0gZGl2X3U2NChyYXRlICogc3RhdGUtPnBlcmlvZCwgTlNFQ19QRVJfU0VDKSA+Pg0K IAkJCSAgUFdNX1BFUklPRF9CSVRfV0lEVEg7DQogCWlmIChjbGtfZGl2ID4gUFdNX0NMS0RJVl9N QVgpIHsNCi0JCWNsa19kaXNhYmxlX3VucHJlcGFyZShtZHAtPmNsa19tbSk7DQotCQljbGtfZGlz YWJsZV91bnByZXBhcmUobWRwLT5jbGtfbWFpbik7DQorCQlpZiAoIW1kcC0+ZW5hYmxlZCkgew0K KwkJCWNsa19kaXNhYmxlX3VucHJlcGFyZShtZHAtPmNsa19tbSk7DQorCQkJY2xrX2Rpc2FibGVf dW5wcmVwYXJlKG1kcC0+Y2xrX21haW4pOw0KKwkJfQ0KIAkJcmV0dXJuIC1FSU5WQUw7DQogCX0N CiANCiAJZGl2ID0gTlNFQ19QRVJfU0VDICogKGNsa19kaXYgKyAxKTsNCi0JcGVyaW9kID0gZGl2 NjRfdTY0KHJhdGUgKiBwZXJpb2RfbnMsIGRpdik7DQorCXBlcmlvZCA9IGRpdjY0X3U2NChyYXRl ICogc3RhdGUtPnBlcmlvZCwgZGl2KTsNCiAJaWYgKHBlcmlvZCA+IDApDQogCQlwZXJpb2QtLTsN CiANCi0JaGlnaF93aWR0aCA9IGRpdjY0X3U2NChyYXRlICogZHV0eV9ucywgZGl2KTsNCisJaGln aF93aWR0aCA9IGRpdjY0X3U2NChyYXRlICogc3RhdGUtPmR1dHlfY3ljbGUsIGRpdik7DQogCXZh bHVlID0gcGVyaW9kIHwgKGhpZ2hfd2lkdGggPDwgUFdNX0hJR0hfV0lEVEhfU0hJRlQpOw0KIA0K IAltdGtfZGlzcF9wd21fdXBkYXRlX2JpdHMobWRwLCBtZHAtPmRhdGEtPmNvbjAsDQpAQCAtMTQw LDUyICsxNjAsMTUgQEAgc3RhdGljIGludCBtdGtfZGlzcF9wd21fY29uZmlnKHN0cnVjdCBwd21f Y2hpcCAqY2hpcCwgc3RydWN0IHB3bV9kZXZpY2UgKnB3bSwNCiAJCQkJCSBtZHAtPmRhdGEtPmNv bjBfc2VsLA0KIAkJCQkJIG1kcC0+ZGF0YS0+Y29uMF9zZWwpOw0KIAl9DQotDQotCWNsa19kaXNh YmxlX3VucHJlcGFyZShtZHAtPmNsa19tbSk7DQotCWNsa19kaXNhYmxlX3VucHJlcGFyZShtZHAt PmNsa19tYWluKTsNCi0NCi0JcmV0dXJuIDA7DQotfQ0KLQ0KLXN0YXRpYyBpbnQgbXRrX2Rpc3Bf cHdtX2VuYWJsZShzdHJ1Y3QgcHdtX2NoaXAgKmNoaXAsIHN0cnVjdCBwd21fZGV2aWNlICpwd20p DQotew0KLQlzdHJ1Y3QgbXRrX2Rpc3BfcHdtICptZHAgPSB0b19tdGtfZGlzcF9wd20oY2hpcCk7 DQotCWludCBlcnI7DQotDQotCWVyciA9IGNsa19wcmVwYXJlX2VuYWJsZShtZHAtPmNsa19tYWlu KTsNCi0JaWYgKGVyciA8IDApIHsNCi0JCWRldl9lcnIoY2hpcC0+ZGV2LCAiQ2FuJ3QgZW5hYmxl IG1kcC0+Y2xrX21haW46ICVwZVxuIiwgRVJSX1BUUihlcnIpKTsNCi0JCXJldHVybiBlcnI7DQot CX0NCi0NCi0JZXJyID0gY2xrX3ByZXBhcmVfZW5hYmxlKG1kcC0+Y2xrX21tKTsNCi0JaWYgKGVy ciA8IDApIHsNCi0JCWRldl9lcnIoY2hpcC0+ZGV2LCAiQ2FuJ3QgZW5hYmxlIG1kcC0+Y2xrX21t OiAlcGVcbiIsIEVSUl9QVFIoZXJyKSk7DQotCQljbGtfZGlzYWJsZV91bnByZXBhcmUobWRwLT5j bGtfbWFpbik7DQotCQlyZXR1cm4gZXJyOw0KLQl9DQotDQogCW10a19kaXNwX3B3bV91cGRhdGVf Yml0cyhtZHAsIERJU1BfUFdNX0VOLCBtZHAtPmRhdGEtPmVuYWJsZV9tYXNrLA0KIAkJCQkgbWRw LT5kYXRhLT5lbmFibGVfbWFzayk7DQorCW1kcC0+ZW5hYmxlZCA9IHRydWU7DQogDQogCXJldHVy biAwOw0KIH0NCiANCi1zdGF0aWMgdm9pZCBtdGtfZGlzcF9wd21fZGlzYWJsZShzdHJ1Y3QgcHdt X2NoaXAgKmNoaXAsIHN0cnVjdCBwd21fZGV2aWNlICpwd20pDQotew0KLQlzdHJ1Y3QgbXRrX2Rp c3BfcHdtICptZHAgPSB0b19tdGtfZGlzcF9wd20oY2hpcCk7DQotDQotCW10a19kaXNwX3B3bV91 cGRhdGVfYml0cyhtZHAsIERJU1BfUFdNX0VOLCBtZHAtPmRhdGEtPmVuYWJsZV9tYXNrLA0KLQkJ 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mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 24 Jul 2021 16:18:53 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 3/5] pwm: mtk_disp: implement atomic API .apply() Date: Sat, 24 Jul 2021 16:18:47 +0800 Message-ID: <20210724081849.182108-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com> References: <20210724081849.182108-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 84B648C66343D480554DDA935607FA7ECB21D8A66B80C5C70D1FDDEB5C1E63982000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210724_011906_781836_EB631DC4 X-CRM114-Status: GOOD ( 15.16 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Switch the driver to support the .apply() method. Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 93 ++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 55 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 1070d78d4940..599d7dd8ecab 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -47,6 +47,7 @@ struct mtk_disp_pwm { struct clk *clk_main; struct clk *clk_mm; void __iomem *base; + bool enabled; }; static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) @@ -66,25 +67,42 @@ static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, writel(value, address); } -static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) +static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); u32 clk_div, period, high_width, value; u64 div, rate; int err; - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!state->enabled) { + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, + 0x0); + if (mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } + mdp->enabled = false; + return 0; } - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; + if (!mdp->enabled) { + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", + ERR_PTR(err)); + return err; + } + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", + ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); + return err; + } } /* @@ -98,20 +116,22 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) */ rate = clk_get_rate(mdp->clk_main); - clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> + clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; if (clk_div > PWM_CLKDIV_MAX) { - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); + if (!mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } return -EINVAL; } div = NSEC_PER_SEC * (clk_div + 1); - period = div64_u64(rate * period_ns, div); + period = div64_u64(rate * state->period, div); if (period > 0) period--; - high_width = div64_u64(rate * duty_ns, div); + high_width = div64_u64(rate * state->duty_cycle, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); mtk_disp_pwm_update_bits(mdp, mdp->data->con0, @@ -140,52 +160,15 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mdp->data->con0_sel, mdp->data->con0_sel); } - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); - - return 0; -} - -static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - int err; - - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; - } - - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; - } - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, mdp->data->enable_mask); + mdp->enabled = true; return 0; } -static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, - 0x0); - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); -} - static const struct pwm_ops mtk_disp_pwm_ops = { - .config = mtk_disp_pwm_config, - .enable = mtk_disp_pwm_enable, - .disable = mtk_disp_pwm_disable, + .apply = mtk_disp_pwm_apply, .owner = THIS_MODULE, }; -- 2.25.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51783C4338F for ; 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Sat, 24 Jul 2021 16:18:53 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 3/5] pwm: mtk_disp: implement atomic API .apply() Date: Sat, 24 Jul 2021 16:18:47 +0800 Message-ID: <20210724081849.182108-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com> References: <20210724081849.182108-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 84B648C66343D480554DDA935607FA7ECB21D8A66B80C5C70D1FDDEB5C1E63982000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210724_011906_781836_EB631DC4 X-CRM114-Status: GOOD ( 15.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Switch the driver to support the .apply() method. Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 93 ++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 55 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 1070d78d4940..599d7dd8ecab 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -47,6 +47,7 @@ struct mtk_disp_pwm { struct clk *clk_main; struct clk *clk_mm; void __iomem *base; + bool enabled; }; static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) @@ -66,25 +67,42 @@ static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, writel(value, address); } -static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) +static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); u32 clk_div, period, high_width, value; u64 div, rate; int err; - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!state->enabled) { + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, + 0x0); + if (mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } + mdp->enabled = false; + return 0; } - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; + if (!mdp->enabled) { + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", + ERR_PTR(err)); + return err; + } + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", + ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); + return err; + } } /* @@ -98,20 +116,22 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) */ rate = clk_get_rate(mdp->clk_main); - clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> + clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; if (clk_div > PWM_CLKDIV_MAX) { - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); + if (!mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } return -EINVAL; } div = NSEC_PER_SEC * (clk_div + 1); - period = div64_u64(rate * period_ns, div); + period = div64_u64(rate * state->period, div); if (period > 0) period--; - high_width = div64_u64(rate * duty_ns, div); + high_width = div64_u64(rate * state->duty_cycle, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); mtk_disp_pwm_update_bits(mdp, mdp->data->con0, @@ -140,52 +160,15 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mdp->data->con0_sel, mdp->data->con0_sel); } - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); - - return 0; -} - -static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - int err; - - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; - } - - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; - } - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, mdp->data->enable_mask); + mdp->enabled = true; return 0; } -static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, - 0x0); - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); -} - static const struct pwm_ops mtk_disp_pwm_ops = { - .config = mtk_disp_pwm_config, - .enable = mtk_disp_pwm_enable, - .disable = mtk_disp_pwm_disable, + .apply = mtk_disp_pwm_apply, .owner = THIS_MODULE, }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel