From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94848C4338F for ; Mon, 26 Jul 2021 08:00:24 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C126160F5B for ; Mon, 26 Jul 2021 08:00:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C126160F5B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C19E8832B0; Mon, 26 Jul 2021 10:00:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B288B832DC; Mon, 26 Jul 2021 10:00:17 +0200 (CEST) Received: from ATCSQR.andestech.com (atcsqr.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7370682D49 for ; Mon, 26 Jul 2021 10:00:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 16Q7xCs8091585; Mon, 26 Jul 2021 15:59:12 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from andestech.com (10.0.15.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 26 Jul 2021 15:59:12 +0800 Date: Mon, 26 Jul 2021 15:59:13 +0800 From: Leo Liang To: Sean Anderson CC: Heinrich Schuchardt , Rick Jian-Zhi =?utf-8?B?Q2hlbijpmbPlu7rlv5cp?= , Alexander Graf , Bin Meng , Green Wan , Marek =?utf-8?B?QmVow7pu?= , Pragnesh Patel , Atish Patra , Ley Foon Tan , Chee Hong Ang , Simon Glass , Siew Chin Lim , Sebastian Reichel , "u-boot@lists.denx.de" Subject: Re: [PATCH v2 1/3] risv: add missing SBI extension definitions Message-ID: <20210726075913.GE983@andestech.com> References: <20210721163305.74945-1-xypron.glpk@gmx.de> <20210721163305.74945-2-xypron.glpk@gmx.de> <985b44a4-7634-245c-70eb-aba1ae541a2e@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <985b44a4-7634-245c-70eb-aba1ae541a2e@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.0.15.65] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 16Q7xCs8091585 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Heinrich, On Thu, Jul 22, 2021 at 01:02:10AM +0800, Sean Anderson wrote: > On 7/21/21 12:33 PM, Heinrich Schuchardt wrote: > > Add the System Reset Extension and the Hart State Management Extension > > definitions. > > > > Add missing RFENCE Extension enum values. > > > > The SBI 0.1 extension constants are needed for for the sbi command. Remove > > an #ifdef. > > > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > > > Signed-off-by: Heinrich Schuchardt > > --- > > v2: > > correct constants that were blindly copied from Linux > > --- > > arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- > > 1 file changed, 34 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > > index 53ca316180..39d5a022e0 100644 > > --- a/arch/riscv/include/asm/sbi.h > > +++ b/arch/riscv/include/asm/sbi.h > > @@ -12,7 +12,6 @@ > > #include > > > > enum sbi_ext_id { > > -#ifdef CONFIG_SBI_V01 > > SBI_EXT_0_1_SET_TIMER = 0x0, > > SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, > > SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, > > @@ -22,11 +21,12 @@ enum sbi_ext_id { > > SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, > > SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, > > SBI_EXT_0_1_SHUTDOWN = 0x8, > > -#endif > > SBI_EXT_BASE = 0x10, > > SBI_EXT_TIME = 0x54494D45, > > SBI_EXT_IPI = 0x735049, > > SBI_EXT_RFENCE = 0x52464E43, > > + SBI_EXT_HSM = 0x48534D, > > + SBI_EXT_SRST = 0x53525354, > > }; > > > > enum sbi_ext_base_fid { > > @@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid { > > SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, > > +}; > > + > > +enum sbi_ext_hsm_fid { > > + SBI_EXT_HSM_HART_START = 0, > > + SBI_EXT_HSM_HART_STOP, > > + SBI_EXT_HSM_HART_STATUS, > > +}; > > + > > +enum sbi_hsm_hart_status { > > + SBI_HSM_HART_STATUS_STARTED = 0, > > + SBI_HSM_HART_STATUS_STOPPED, > > + SBI_HSM_HART_STATUS_START_PENDING, > > + SBI_HSM_HART_STATUS_STOP_PENDING, > > Perhaps add the suspend states from https://github.com/riscv/riscv-sbi-doc/pull/66 +1 > > > +}; > > + > > +enum sbi_ext_srst_fid { > > + SBI_EXT_SRST_RESET = 0, > > +}; > > + > > +enum sbi_srst_reset_type { > > + SBI_SRST_RESET_TYPE_SHUTDOWN = 0, > > + SBI_SRST_RESET_TYPE_COLD_REBOOT, > > + SBI_SRST_RESET_TYPE_WARM_REBOOT, > > +}; > > + > > +enum sbi_srst_reset_reason { > > + SBI_SRST_RESET_REASON_NONE = 0, > > + SBI_SRST_RESET_REASON_SYS_FAILURE, > > }; > > > > #ifdef CONFIG_SBI_V01 > > -- > > 2.30.2 > > > > Reviewed-by: Sean Anderson Best regards, Leo