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* [gustavoars-linux:for-next/clang-fallthrough 4/4] arch/mips/kernel/idle.c:206:3: warning: fallthrough annotation in unreachable code
@ 2021-07-27  2:39 ` kernel test robot
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-07-27  2:39 UTC (permalink / raw)
  To: Gustavo A. R. Silva
  Cc: clang-built-linux, kbuild-all, Gustavo A. R. Silva, LKML

[-- Attachment #1: Type: text/plain, Size: 11460 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git for-next/clang-fallthrough
head:   6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
commit: 6a8c3492420661bf905f0f1f4cddde0ec8bde6d8 [4/4] Revert "Revert "Makefile: Enable -Wimplicit-fallthrough for Clang""
config: mips-randconfig-r036-20210726 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project c658b472f3e61e1818e1909bf02f3d65470018a5)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install mips cross compiling tool for clang build
        # apt-get install binutils-mips-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git/commit/?id=6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
        git remote add gustavoars-linux https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git
        git fetch --no-tags gustavoars-linux for-next/clang-fallthrough
        git checkout 6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> arch/mips/kernel/idle.c:206:3: warning: fallthrough annotation in unreachable code [-Wimplicit-fallthrough]
                   fallthrough;
                   ^
   include/linux/compiler_attributes.h:210:41: note: expanded from macro 'fallthrough'
   # define fallthrough                    __attribute__((__fallthrough__))
                                           ^
   1 warning generated.


vim +206 arch/mips/kernel/idle.c

49f2ec91e14ce9 Ralf Baechle     2013-05-21  125  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  126  void __init check_wait(void)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  127  {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  128  	struct cpuinfo_mips *c = &current_cpu_data;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  129  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  130  	if (nowait) {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  131  		printk("Wait instruction disabled.\n");
49f2ec91e14ce9 Ralf Baechle     2013-05-21  132  		return;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  133  	}
49f2ec91e14ce9 Ralf Baechle     2013-05-21  134  
5b10a0e84b4ebe Paul Burton      2015-09-22  135  	/*
5b10a0e84b4ebe Paul Burton      2015-09-22  136  	 * MIPSr6 specifies that masked interrupts should unblock an executing
5b10a0e84b4ebe Paul Burton      2015-09-22  137  	 * wait instruction, and thus that it is safe for us to use
5b10a0e84b4ebe Paul Burton      2015-09-22  138  	 * r4k_wait_irqoff. Yippee!
5b10a0e84b4ebe Paul Burton      2015-09-22  139  	 */
5b10a0e84b4ebe Paul Burton      2015-09-22  140  	if (cpu_has_mips_r6) {
5b10a0e84b4ebe Paul Burton      2015-09-22  141  		cpu_wait = r4k_wait_irqoff;
5b10a0e84b4ebe Paul Burton      2015-09-22  142  		return;
5b10a0e84b4ebe Paul Burton      2015-09-22  143  	}
5b10a0e84b4ebe Paul Burton      2015-09-22  144  
69f24d1784b631 Ralf Baechle     2013-09-17  145  	switch (current_cpu_type()) {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  146  	case CPU_R3081:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  147  	case CPU_R3081E:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  148  		cpu_wait = r3081_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  149  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  150  	case CPU_TX3927:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  151  		cpu_wait = r39xx_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  152  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  153  	case CPU_R4200:
65ce6197ed403b Lauri Kasanen    2021-01-13  154  /*	case CPU_R4300: */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  155  	case CPU_R4600:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  156  	case CPU_R4640:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  157  	case CPU_R4650:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  158  	case CPU_R4700:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  159  	case CPU_R5000:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  160  	case CPU_R5500:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  161  	case CPU_NEVADA:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  162  	case CPU_4KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  163  	case CPU_4KEC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  164  	case CPU_4KSC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  165  	case CPU_5KC:
bf463f2f751077 Aurelien Jarno   2015-09-05  166  	case CPU_5KE:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  167  	case CPU_25KF:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  168  	case CPU_PR4450:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  169  	case CPU_BMIPS3300:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  170  	case CPU_BMIPS4350:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  171  	case CPU_BMIPS4380:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  172  	case CPU_CAVIUM_OCTEON:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  173  	case CPU_CAVIUM_OCTEON_PLUS:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  174  	case CPU_CAVIUM_OCTEON2:
4122af0ab02a4b David Daney      2013-07-29  175  	case CPU_CAVIUM_OCTEON3:
3b25b763116482 Paul Cercueil    2019-05-08  176  	case CPU_XBURST:
b2afb64cccd243 Huacai Chen      2019-11-04  177  	case CPU_LOONGSON32:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  178  	case CPU_XLR:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  179  	case CPU_XLP:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  180  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  181  		break;
268a2d60013049 Jiaxun Yang      2019-10-20  182  	case CPU_LOONGSON64:
7507445b199308 Huacai Chen      2019-09-21  183  		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
0cf2ea1121aa14 Jiaxun Yang      2020-04-22  184  				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
0cf2ea1121aa14 Jiaxun Yang      2020-04-22  185  				(c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
b2edcfc814017e Huacai Chen      2016-03-03  186  			cpu_wait = r4k_wait;
b2edcfc814017e Huacai Chen      2016-03-03  187  		break;
b2edcfc814017e Huacai Chen      2016-03-03  188  
adaa0b6c497955 Petri Gynther    2015-10-19  189  	case CPU_BMIPS5000:
adaa0b6c497955 Petri Gynther    2015-10-19  190  		cpu_wait = r4k_wait_irqoff;
adaa0b6c497955 Petri Gynther    2015-10-19  191  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  192  	case CPU_RM7000:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  193  		cpu_wait = rm7k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  194  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  195  
e38df288a9db56 James Hogan      2015-01-29  196  	case CPU_PROAPTIV:
e38df288a9db56 James Hogan      2015-01-29  197  	case CPU_P5600:
e38df288a9db56 James Hogan      2015-01-29  198  		/*
e38df288a9db56 James Hogan      2015-01-29  199  		 * Incoming Fast Debug Channel (FDC) data during a wait
e38df288a9db56 James Hogan      2015-01-29  200  		 * instruction causes the wait never to resume, even if an
e38df288a9db56 James Hogan      2015-01-29  201  		 * interrupt is received. Avoid using wait at all if FDC data is
e38df288a9db56 James Hogan      2015-01-29  202  		 * likely to be received.
e38df288a9db56 James Hogan      2015-01-29  203  		 */
e38df288a9db56 James Hogan      2015-01-29  204  		if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
e38df288a9db56 James Hogan      2015-01-29  205  			break;
c9b0299034665d Liangliang Huang 2020-05-04 @206  		fallthrough;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  207  	case CPU_M14KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  208  	case CPU_M14KEC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  209  	case CPU_24K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  210  	case CPU_34K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  211  	case CPU_1004K:
442e14a2c55e55 Steven J. Hill   2014-01-17  212  	case CPU_1074K:
26ab96dfa9f98d Leonid Yegoshin  2013-11-27  213  	case CPU_INTERAPTIV:
f36c4720fca325 Leonid Yegoshin  2014-03-04  214  	case CPU_M5150:
4695089f03929c Leonid Yegoshin  2014-11-24  215  	case CPU_QEMU_GENERIC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  216  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  217  		if (read_c0_config7() & MIPS_CONF7_WII)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  218  			cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  219  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  220  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  221  	case CPU_74K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  222  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  223  		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
49f2ec91e14ce9 Ralf Baechle     2013-05-21  224  			cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  225  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  226  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  227  	case CPU_TX49XX:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  228  		cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  229  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  230  	case CPU_ALCHEMY:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  231  		cpu_wait = au1k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  232  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  233  	case CPU_20KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  234  		/*
49f2ec91e14ce9 Ralf Baechle     2013-05-21  235  		 * WAIT on Rev1.0 has E1, E2, E3 and E16.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  236  		 * WAIT on Rev2.0 and Rev3.0 has E16.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  237  		 * Rev3.1 WAIT is nop, why bother
49f2ec91e14ce9 Ralf Baechle     2013-05-21  238  		 */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  239  		if ((c->processor_id & 0xff) <= 0x64)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  240  			break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  241  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  242  		/*
49f2ec91e14ce9 Ralf Baechle     2013-05-21  243  		 * Another rev is incremeting c0_count at a reduced clock
49f2ec91e14ce9 Ralf Baechle     2013-05-21  244  		 * rate while in WAIT mode.  So we basically have the choice
49f2ec91e14ce9 Ralf Baechle     2013-05-21  245  		 * between using the cp0 timer as clocksource or avoiding
49f2ec91e14ce9 Ralf Baechle     2013-05-21  246  		 * the WAIT instruction.  Until more details are known,
49f2ec91e14ce9 Ralf Baechle     2013-05-21  247  		 * disable the use of WAIT for 20Kc entirely.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  248  		   cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  249  		 */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  250  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  251  	default:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  252  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  253  	}
49f2ec91e14ce9 Ralf Baechle     2013-05-21  254  }
49f2ec91e14ce9 Ralf Baechle     2013-05-21  255  

:::::: The code at line 206 was first introduced by commit
:::::: c9b0299034665d594e56ee343f28033d1b24de6d MIPS: Use fallthrough for arch/mips

:::::: TO: Liangliang Huang <huanglllzu@gmail.com>
:::::: CC: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37031 bytes --]

^ permalink raw reply	[flat|nested] 2+ messages in thread
* [gustavoars-linux:for-next/clang-fallthrough 4/4] arch/mips/kernel/idle.c:206:3: warning: fallthrough annotation in unreachable code
@ 2021-07-27  2:39 ` kernel test robot
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-07-27  2:39 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 11633 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git for-next/clang-fallthrough
head:   6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
commit: 6a8c3492420661bf905f0f1f4cddde0ec8bde6d8 [4/4] Revert "Revert "Makefile: Enable -Wimplicit-fallthrough for Clang""
config: mips-randconfig-r036-20210726 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project c658b472f3e61e1818e1909bf02f3d65470018a5)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install mips cross compiling tool for clang build
        # apt-get install binutils-mips-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git/commit/?id=6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
        git remote add gustavoars-linux https://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git
        git fetch --no-tags gustavoars-linux for-next/clang-fallthrough
        git checkout 6a8c3492420661bf905f0f1f4cddde0ec8bde6d8
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> arch/mips/kernel/idle.c:206:3: warning: fallthrough annotation in unreachable code [-Wimplicit-fallthrough]
                   fallthrough;
                   ^
   include/linux/compiler_attributes.h:210:41: note: expanded from macro 'fallthrough'
   # define fallthrough                    __attribute__((__fallthrough__))
                                           ^
   1 warning generated.


vim +206 arch/mips/kernel/idle.c

49f2ec91e14ce9 Ralf Baechle     2013-05-21  125  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  126  void __init check_wait(void)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  127  {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  128  	struct cpuinfo_mips *c = &current_cpu_data;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  129  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  130  	if (nowait) {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  131  		printk("Wait instruction disabled.\n");
49f2ec91e14ce9 Ralf Baechle     2013-05-21  132  		return;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  133  	}
49f2ec91e14ce9 Ralf Baechle     2013-05-21  134  
5b10a0e84b4ebe Paul Burton      2015-09-22  135  	/*
5b10a0e84b4ebe Paul Burton      2015-09-22  136  	 * MIPSr6 specifies that masked interrupts should unblock an executing
5b10a0e84b4ebe Paul Burton      2015-09-22  137  	 * wait instruction, and thus that it is safe for us to use
5b10a0e84b4ebe Paul Burton      2015-09-22  138  	 * r4k_wait_irqoff. Yippee!
5b10a0e84b4ebe Paul Burton      2015-09-22  139  	 */
5b10a0e84b4ebe Paul Burton      2015-09-22  140  	if (cpu_has_mips_r6) {
5b10a0e84b4ebe Paul Burton      2015-09-22  141  		cpu_wait = r4k_wait_irqoff;
5b10a0e84b4ebe Paul Burton      2015-09-22  142  		return;
5b10a0e84b4ebe Paul Burton      2015-09-22  143  	}
5b10a0e84b4ebe Paul Burton      2015-09-22  144  
69f24d1784b631 Ralf Baechle     2013-09-17  145  	switch (current_cpu_type()) {
49f2ec91e14ce9 Ralf Baechle     2013-05-21  146  	case CPU_R3081:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  147  	case CPU_R3081E:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  148  		cpu_wait = r3081_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  149  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  150  	case CPU_TX3927:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  151  		cpu_wait = r39xx_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  152  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  153  	case CPU_R4200:
65ce6197ed403b Lauri Kasanen    2021-01-13  154  /*	case CPU_R4300: */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  155  	case CPU_R4600:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  156  	case CPU_R4640:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  157  	case CPU_R4650:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  158  	case CPU_R4700:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  159  	case CPU_R5000:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  160  	case CPU_R5500:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  161  	case CPU_NEVADA:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  162  	case CPU_4KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  163  	case CPU_4KEC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  164  	case CPU_4KSC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  165  	case CPU_5KC:
bf463f2f751077 Aurelien Jarno   2015-09-05  166  	case CPU_5KE:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  167  	case CPU_25KF:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  168  	case CPU_PR4450:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  169  	case CPU_BMIPS3300:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  170  	case CPU_BMIPS4350:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  171  	case CPU_BMIPS4380:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  172  	case CPU_CAVIUM_OCTEON:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  173  	case CPU_CAVIUM_OCTEON_PLUS:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  174  	case CPU_CAVIUM_OCTEON2:
4122af0ab02a4b David Daney      2013-07-29  175  	case CPU_CAVIUM_OCTEON3:
3b25b763116482 Paul Cercueil    2019-05-08  176  	case CPU_XBURST:
b2afb64cccd243 Huacai Chen      2019-11-04  177  	case CPU_LOONGSON32:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  178  	case CPU_XLR:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  179  	case CPU_XLP:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  180  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  181  		break;
268a2d60013049 Jiaxun Yang      2019-10-20  182  	case CPU_LOONGSON64:
7507445b199308 Huacai Chen      2019-09-21  183  		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
0cf2ea1121aa14 Jiaxun Yang      2020-04-22  184  				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
0cf2ea1121aa14 Jiaxun Yang      2020-04-22  185  				(c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
b2edcfc814017e Huacai Chen      2016-03-03  186  			cpu_wait = r4k_wait;
b2edcfc814017e Huacai Chen      2016-03-03  187  		break;
b2edcfc814017e Huacai Chen      2016-03-03  188  
adaa0b6c497955 Petri Gynther    2015-10-19  189  	case CPU_BMIPS5000:
adaa0b6c497955 Petri Gynther    2015-10-19  190  		cpu_wait = r4k_wait_irqoff;
adaa0b6c497955 Petri Gynther    2015-10-19  191  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  192  	case CPU_RM7000:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  193  		cpu_wait = rm7k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  194  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  195  
e38df288a9db56 James Hogan      2015-01-29  196  	case CPU_PROAPTIV:
e38df288a9db56 James Hogan      2015-01-29  197  	case CPU_P5600:
e38df288a9db56 James Hogan      2015-01-29  198  		/*
e38df288a9db56 James Hogan      2015-01-29  199  		 * Incoming Fast Debug Channel (FDC) data during a wait
e38df288a9db56 James Hogan      2015-01-29  200  		 * instruction causes the wait never to resume, even if an
e38df288a9db56 James Hogan      2015-01-29  201  		 * interrupt is received. Avoid using wait at all if FDC data is
e38df288a9db56 James Hogan      2015-01-29  202  		 * likely to be received.
e38df288a9db56 James Hogan      2015-01-29  203  		 */
e38df288a9db56 James Hogan      2015-01-29  204  		if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
e38df288a9db56 James Hogan      2015-01-29  205  			break;
c9b0299034665d Liangliang Huang 2020-05-04 @206  		fallthrough;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  207  	case CPU_M14KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  208  	case CPU_M14KEC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  209  	case CPU_24K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  210  	case CPU_34K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  211  	case CPU_1004K:
442e14a2c55e55 Steven J. Hill   2014-01-17  212  	case CPU_1074K:
26ab96dfa9f98d Leonid Yegoshin  2013-11-27  213  	case CPU_INTERAPTIV:
f36c4720fca325 Leonid Yegoshin  2014-03-04  214  	case CPU_M5150:
4695089f03929c Leonid Yegoshin  2014-11-24  215  	case CPU_QEMU_GENERIC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  216  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  217  		if (read_c0_config7() & MIPS_CONF7_WII)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  218  			cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  219  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  220  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  221  	case CPU_74K:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  222  		cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  223  		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
49f2ec91e14ce9 Ralf Baechle     2013-05-21  224  			cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  225  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  226  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  227  	case CPU_TX49XX:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  228  		cpu_wait = r4k_wait_irqoff;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  229  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  230  	case CPU_ALCHEMY:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  231  		cpu_wait = au1k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  232  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  233  	case CPU_20KC:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  234  		/*
49f2ec91e14ce9 Ralf Baechle     2013-05-21  235  		 * WAIT on Rev1.0 has E1, E2, E3 and E16.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  236  		 * WAIT on Rev2.0 and Rev3.0 has E16.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  237  		 * Rev3.1 WAIT is nop, why bother
49f2ec91e14ce9 Ralf Baechle     2013-05-21  238  		 */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  239  		if ((c->processor_id & 0xff) <= 0x64)
49f2ec91e14ce9 Ralf Baechle     2013-05-21  240  			break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  241  
49f2ec91e14ce9 Ralf Baechle     2013-05-21  242  		/*
49f2ec91e14ce9 Ralf Baechle     2013-05-21  243  		 * Another rev is incremeting c0_count at a reduced clock
49f2ec91e14ce9 Ralf Baechle     2013-05-21  244  		 * rate while in WAIT mode.  So we basically have the choice
49f2ec91e14ce9 Ralf Baechle     2013-05-21  245  		 * between using the cp0 timer as clocksource or avoiding
49f2ec91e14ce9 Ralf Baechle     2013-05-21  246  		 * the WAIT instruction.  Until more details are known,
49f2ec91e14ce9 Ralf Baechle     2013-05-21  247  		 * disable the use of WAIT for 20Kc entirely.
49f2ec91e14ce9 Ralf Baechle     2013-05-21  248  		   cpu_wait = r4k_wait;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  249  		 */
49f2ec91e14ce9 Ralf Baechle     2013-05-21  250  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  251  	default:
49f2ec91e14ce9 Ralf Baechle     2013-05-21  252  		break;
49f2ec91e14ce9 Ralf Baechle     2013-05-21  253  	}
49f2ec91e14ce9 Ralf Baechle     2013-05-21  254  }
49f2ec91e14ce9 Ralf Baechle     2013-05-21  255  

:::::: The code@line 206 was first introduced by commit
:::::: c9b0299034665d594e56ee343f28033d1b24de6d MIPS: Use fallthrough for arch/mips

:::::: TO: Liangliang Huang <huanglllzu@gmail.com>
:::::: CC: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
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