From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F35ADC4338F for ; Wed, 28 Jul 2021 16:46:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD0D160F01 for ; Wed, 28 Jul 2021 16:46:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230401AbhG1Qqg (ORCPT ); Wed, 28 Jul 2021 12:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbhG1Qqa (ORCPT ); Wed, 28 Jul 2021 12:46:30 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C144C0613C1 for ; Wed, 28 Jul 2021 09:46:28 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id mz5-20020a17090b3785b0290176ecf64922so10950697pjb.3 for ; Wed, 28 Jul 2021 09:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4EzQ3N+ODDdvnvVDTZIarWyD37aI4tmhSikXWpjiVUY=; b=EU3iKiBW+M2JHYQkK//DzPmyuUiY16zfe/dyPa7qUUIzTsMOSUFAQqW+N3JQg9VrZV lxB6ABgl/2kluHAMzNN7nuczUvBQAC8xM0Hlqgvi1CKjFMqyKjVWklc0uTuuRZWZYd7d lBabA3MxS6WKG0Rzb7zJLZ8vf1u1osWdifZ1Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4EzQ3N+ODDdvnvVDTZIarWyD37aI4tmhSikXWpjiVUY=; b=genFdTAkt7Kw3LUjy/pd00KS8muzanhXUTC5Y3E6Ia5ymQHD2iL4juzhbyhSKY//ZO ajM5N9+2z1q4RJrPJotsL3q4f7e9UbHwLhOE3w7nbFt4DnyOITSDRXU5dOy9b3uMf8cC ylxjBGYCBuG1gDwnkBf0CgQ8HUjlXaA/8FRIPHUlNlG+Wup/Nrsbe4uPa+0RPP1FYDd1 yxxqpiA2Ez4lofj9YhtYYrZnWy6SvdnpLPxrfQCuKWjIgx01EcsnQ5KPENOObX/81Lpv f2HqWU6Khy3BHIwIGv3DntRBNCfeFeidHvJdwln0ngXELeIU91YsCyFwsE2uY+mUIy7U YifA== X-Gm-Message-State: AOAM532X2VmWytBWgrPbwljHfPAS8pk6KpoeE+FZr3QAFQHYLjeVYtoE EBv7dMZ44ydZzrFGI+jxC40X5w== X-Google-Smtp-Source: ABdhPJwFA6ekQGuPWzWt4zMkZMwPi7juaMmH8xgdIcduykGrCB8inwPTTU0kSK3K8ZC4aCdmzv8rUg== X-Received: by 2002:a17:90b:2286:: with SMTP id kx6mr1613944pjb.11.1627490788164; Wed, 28 Jul 2021 09:46:28 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:9f1e:e713:1a5e:89dc]) by smtp.gmail.com with ESMTPSA id l12sm474075pff.182.2021.07.28.09.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 09:46:27 -0700 (PDT) From: Douglas Anderson To: dri-devel@lists.freedesktop.org Cc: tzimmermann@suse.de, linux-arm-msm@vger.kernel.org, a.hajda@samsung.com, sam@ravnborg.org, airlied@linux.ie, bjorn.andersson@linaro.org, daniel@ffwll.ch, devicetree@vger.kernel.org, rodrigo.vivi@intel.com, jonas@kwiboo.se, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, robert.foss@linaro.org, jernej.skrabec@gmail.com, mripard@kernel.org, linus.walleij@linaro.org, maarten.lankhorst@linux.intel.com, rajeevny@codeaurora.org, lyude@redhat.com, thierry.reding@gmail.com, steev@kali.org, Douglas Anderson , Sandeep Panda , linux-kernel@vger.kernel.org Subject: [PATCH 2/6] drm/bridge: ti-sn65dsi86: Fix power off sequence Date: Wed, 28 Jul 2021 09:45:53 -0700 Message-Id: <20210728094511.2.If8a8ec3bf1855cf0dbb62c005a71d6698c99c125@changeid> X-Mailer: git-send-email 2.32.0.432.gabb21c7263-goog In-Reply-To: <20210728164557.1882787-1-dianders@chromium.org> References: <20210728164557.1882787-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When testing with a panel that's apparently a little more persnickety about the correct power sequence (specifically Samsung ATNA33XC20), we found that the ti-sn65dsi86 was doing things just slightly wrong. Looking closely at the ti-sn65dsi86's datasheet, the power off sequence is supposed to be: 1. Clear VSTREAM_ENABLE bit 2. Stop DSI stream from GPU. DSI lanes must be placed in LP11 state. 3. Program the ML_TX_MODE to 0x0 (OFF) 4. Program the DP_NUM_LANES register to 0x0 5. Clear the DP_PLL_EN bit. 6. Deassert the EN pin. 7. Remove power from supply pins Since we were doing the whole sequence in the "disable", I believe that step #2 (stopping the DSI stream from the GPU) wasn't happening. We also weren't setting DP_NUM_LANES to 0. Let's fix this. NOTE: things are a little asymmetric now. For instance, we turn the PLL on in "enable" but now we're not turning it off until "post_disable". It would seem to make sense to move the PLL turning on to "pre_enable" to match. Unfortunately, I don't believe that's allowed. It looks as if (in the non-refclk mode which probably nobody is using) we have to wait until the MIPI clock is there before we can enable the PLL. In any case, the way it is here won't really hurt--it'll just leave the PLL on a little longer. Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver") Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 9bf889302bcc..5e932070a1c3 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -766,10 +766,6 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge) /* disable video stream */ regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); - /* semi auto link training mode OFF */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); - /* disable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); } static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) @@ -1106,6 +1102,13 @@ static void ti_sn_bridge_post_disable(struct drm_bridge *bridge) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); + /* semi auto link training mode OFF */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); + /* Num lanes to 0 as per power sequencing in data sheet */ + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); + /* disable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + if (!pdata->refclk) ti_sn65dsi86_disable_comms(pdata); -- 2.32.0.432.gabb21c7263-goog From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45E74C4320A for ; Wed, 28 Jul 2021 16:46:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18A3760EB9 for ; Wed, 28 Jul 2021 16:46:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 18A3760EB9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DED66E284; Wed, 28 Jul 2021 16:46:30 +0000 (UTC) Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by gabe.freedesktop.org (Postfix) with ESMTPS id D133A6E284 for ; Wed, 28 Jul 2021 16:46:28 +0000 (UTC) Received: by mail-pl1-x62c.google.com with SMTP id z3so2068548plg.8 for ; Wed, 28 Jul 2021 09:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4EzQ3N+ODDdvnvVDTZIarWyD37aI4tmhSikXWpjiVUY=; b=EU3iKiBW+M2JHYQkK//DzPmyuUiY16zfe/dyPa7qUUIzTsMOSUFAQqW+N3JQg9VrZV lxB6ABgl/2kluHAMzNN7nuczUvBQAC8xM0Hlqgvi1CKjFMqyKjVWklc0uTuuRZWZYd7d lBabA3MxS6WKG0Rzb7zJLZ8vf1u1osWdifZ1Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4EzQ3N+ODDdvnvVDTZIarWyD37aI4tmhSikXWpjiVUY=; b=I/KrawCyAkuLgSTrRFg8F0Q1tHjpKdJwp+t8tOO0B1ZV3HjRFyVsmf96GM7GDSbYcl obZiE7t79cFORrnmkGbNtnGKOZ8k8mOwLFiHb2iMcml6NOcwO04Aim5zlbWFtiF87A+U 7sx0WtBbTWmCXYhU2muQh2n7x3BxOrmwGP2zgs8uOGWJcsDWgSeaNli33lzu2k+O+I6O kkKH8opaqHQl/9rVf604WAEL71UoQrCkHsZe/od9dWo/D0lsjjOIkRNHlArcgN1NBIPC r60IAvcHAOdezZ1iKymjJrIyC+ijzcNNkWDssRgifaJmR19ZRJhhuW2+V/K56wPeqdct RHoQ== X-Gm-Message-State: AOAM533BGskt4YG26J0kWzrSvi0yI8VQFM4M+OsTK4IxcUgKy68lAOOX ATRxJolK/UoxOVY2w1gwwaCFSDMU56QKgfPi X-Google-Smtp-Source: ABdhPJwFA6ekQGuPWzWt4zMkZMwPi7juaMmH8xgdIcduykGrCB8inwPTTU0kSK3K8ZC4aCdmzv8rUg== X-Received: by 2002:a17:90b:2286:: with SMTP id kx6mr1613944pjb.11.1627490788164; Wed, 28 Jul 2021 09:46:28 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:9f1e:e713:1a5e:89dc]) by smtp.gmail.com with ESMTPSA id l12sm474075pff.182.2021.07.28.09.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 09:46:27 -0700 (PDT) From: Douglas Anderson To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/6] drm/bridge: ti-sn65dsi86: Fix power off sequence Date: Wed, 28 Jul 2021 09:45:53 -0700 Message-Id: <20210728094511.2.If8a8ec3bf1855cf0dbb62c005a71d6698c99c125@changeid> X-Mailer: git-send-email 2.32.0.432.gabb21c7263-goog In-Reply-To: <20210728164557.1882787-1-dianders@chromium.org> References: <20210728164557.1882787-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: narmstrong@baylibre.com, airlied@linux.ie, Sandeep Panda , steev@kali.org, bjorn.andersson@linaro.org, a.hajda@samsung.com, thierry.reding@gmail.com, Laurent.pinchart@ideasonboard.com, sam@ravnborg.org, jernej.skrabec@gmail.com, devicetree@vger.kernel.org, tzimmermann@suse.de, jonas@kwiboo.se, linux-arm-msm@vger.kernel.org, rodrigo.vivi@intel.com, rajeevny@codeaurora.org, Douglas Anderson , robert.foss@linaro.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When testing with a panel that's apparently a little more persnickety about the correct power sequence (specifically Samsung ATNA33XC20), we found that the ti-sn65dsi86 was doing things just slightly wrong. Looking closely at the ti-sn65dsi86's datasheet, the power off sequence is supposed to be: 1. Clear VSTREAM_ENABLE bit 2. Stop DSI stream from GPU. DSI lanes must be placed in LP11 state. 3. Program the ML_TX_MODE to 0x0 (OFF) 4. Program the DP_NUM_LANES register to 0x0 5. Clear the DP_PLL_EN bit. 6. Deassert the EN pin. 7. Remove power from supply pins Since we were doing the whole sequence in the "disable", I believe that step #2 (stopping the DSI stream from the GPU) wasn't happening. We also weren't setting DP_NUM_LANES to 0. Let's fix this. NOTE: things are a little asymmetric now. For instance, we turn the PLL on in "enable" but now we're not turning it off until "post_disable". It would seem to make sense to move the PLL turning on to "pre_enable" to match. Unfortunately, I don't believe that's allowed. It looks as if (in the non-refclk mode which probably nobody is using) we have to wait until the MIPI clock is there before we can enable the PLL. In any case, the way it is here won't really hurt--it'll just leave the PLL on a little longer. Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver") Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 9bf889302bcc..5e932070a1c3 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -766,10 +766,6 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge) /* disable video stream */ regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); - /* semi auto link training mode OFF */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); - /* disable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); } static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) @@ -1106,6 +1102,13 @@ static void ti_sn_bridge_post_disable(struct drm_bridge *bridge) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); + /* semi auto link training mode OFF */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); + /* Num lanes to 0 as per power sequencing in data sheet */ + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); + /* disable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + if (!pdata->refclk) ti_sn65dsi86_disable_comms(pdata); -- 2.32.0.432.gabb21c7263-goog