All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v2] target/i386: Added V_INTR_PRIO check to virtual interrupts
@ 2021-07-28 10:17 Lara Lazier
  2021-07-29  7:57 ` Paolo Bonzini
  0 siblings, 1 reply; 2+ messages in thread
From: Lara Lazier @ 2021-07-28 10:17 UTC (permalink / raw)
  To: qemu-devel; +Cc: pbonzini, Lara Lazier

v1->v2: Fixed Mask

The APM2 states that The processor takes a virtual INTR interrupt
if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending
whose priority is greater than the value in V_TPR.

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
---
 target/i386/tcg/sysemu/svm_helper.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index 72ea7c9a08..a3138e9f86 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -65,6 +65,16 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
                            sc->base, sc->limit, sc->flags);
 }
 
+static inline bool ctl_has_irq(uint32_t int_ctl)
+{
+    uint32_t int_prio;
+    uint32_t tpr;
+
+    int_prio = (int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
+    tpr = int_ctl & V_TPR_MASK;
+    return (int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
+}
+
 static inline bool is_efer_invalid_state (CPUX86State *env)
 {
     if (!(env->efer & MSR_EFER_SVME)) {
@@ -365,7 +375,6 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
 
     if (ctl_has_irq(int_ctl)) {
         CPUState *cs = env_cpu(env);
-
         cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
     }
 
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH v2] target/i386: Added V_INTR_PRIO check to virtual interrupts
  2021-07-28 10:17 [PATCH v2] target/i386: Added V_INTR_PRIO check to virtual interrupts Lara Lazier
@ 2021-07-29  7:57 ` Paolo Bonzini
  0 siblings, 0 replies; 2+ messages in thread
From: Paolo Bonzini @ 2021-07-29  7:57 UTC (permalink / raw)
  To: Lara Lazier, qemu-devel

On 28/07/21 12:17, Lara Lazier wrote:
> v1->v2: Fixed Mask
> 
> The APM2 states that The processor takes a virtual INTR interrupt
> if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending
> whose priority is greater than the value in V_TPR.
> 
> Signed-off-by: Lara Lazier <laramglazier@gmail.com>
> ---
>   target/i386/tcg/sysemu/svm_helper.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
> index 72ea7c9a08..a3138e9f86 100644
> --- a/target/i386/tcg/sysemu/svm_helper.c
> +++ b/target/i386/tcg/sysemu/svm_helper.c
> @@ -65,6 +65,16 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
>                              sc->base, sc->limit, sc->flags);
>   }
>   
> +static inline bool ctl_has_irq(uint32_t int_ctl)
> +{
> +    uint32_t int_prio;
> +    uint32_t tpr;
> +
> +    int_prio = (int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
> +    tpr = int_ctl & V_TPR_MASK;
> +    return (int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
> +}
> +
>   static inline bool is_efer_invalid_state (CPUX86State *env)
>   {
>       if (!(env->efer & MSR_EFER_SVME)) {
> @@ -365,7 +375,6 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
>   
>       if (ctl_has_irq(int_ctl)) {
>           CPUState *cs = env_cpu(env);
> -
>           cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
>       }
>   
> 

Merged, thanks.

Paolo



^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2021-07-29  7:58 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-28 10:17 [PATCH v2] target/i386: Added V_INTR_PRIO check to virtual interrupts Lara Lazier
2021-07-29  7:57 ` Paolo Bonzini

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.