From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20FDBC432BE for ; Wed, 28 Jul 2021 14:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0976460F9D for ; Wed, 28 Jul 2021 14:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233439AbhG1OBC (ORCPT ); Wed, 28 Jul 2021 10:01:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:35946 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233254AbhG1OBB (ORCPT ); Wed, 28 Jul 2021 10:01:01 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A326E600EF; Wed, 28 Jul 2021 14:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627480860; bh=sNNg1eBjaBERoOL+pNGqJG1GnXOiFtnWCHGA3ZA1guw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uSK3rYX334vCPmIzWf/THTX34yLnn8ni/QBiKG2wSaCIb8flS7V+h/B0eP4sytljM /dQCjspApub1KKi22poI11WUSYyfjIatH2hfq7qGrbqIBlbq4S7vAjAAhS+KS8TxV8 5woiYW5ZUA5Il7RUYHhP1Ry/YyXRyBxz8Ox2BtJMlMkWsKjuc9kKYiDOiacib9sy0i aPfPMZkkYmDggAK37mahkCnICO1fDZeN0JaiIFzgSxGeXShgdXEF1DAYPxU22ln/Di kGzFe7xSqPBokwQ8jjNqfX2hYMIrPy1ah7XaTQx6UwViWPpfyLEfsPSfZ5MEsWr3Ps NAkXFU5X3exlg== Date: Wed, 28 Jul 2021 17:00:53 +0300 From: Georgi Djakov To: Sai Prakash Ranjan Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , isaacm@codeaurora.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno , Kristian H Kristensen , Sean Paul , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Message-ID: <20210728140052.GB22887@mms-0441> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache. Now that system cache support for GPU is added, we will > need to set the right PTE attribute for GPU buffers to be sys cached. > Without this, the system cache lines are not allocated for GPU. > > So the patches in this series introduces a new prot flag IOMMU_LLC, > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > and makes GPU the user of this protection flag. Hi Sai, Thank you for the patchset! Are you planning to refresh it, as it does not apply anymore? Thanks, Georgi > > The series slightly depends on following 2 patches posted earlier and > is based on msm-next branch: > * https://lore.kernel.org/patchwork/patch/1363008/ > * https://lore.kernel.org/patchwork/patch/1363010/ > > Sai Prakash Ranjan (3): > iommu/io-pgtable: Rename last-level cache quirk to > IO_PGTABLE_QUIRK_PTW_LLC > iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag > drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 3 +++ > drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ > drivers/iommu/io-pgtable-arm.c | 9 ++++++--- > include/linux/io-pgtable.h | 6 +++--- > include/linux/iommu.h | 6 ++++++ > 7 files changed, 26 insertions(+), 7 deletions(-) > > > base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FCC0C4338F for ; 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Wed, 28 Jul 2021 14:01:00 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id A326E600EF; Wed, 28 Jul 2021 14:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627480860; bh=sNNg1eBjaBERoOL+pNGqJG1GnXOiFtnWCHGA3ZA1guw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uSK3rYX334vCPmIzWf/THTX34yLnn8ni/QBiKG2wSaCIb8flS7V+h/B0eP4sytljM /dQCjspApub1KKi22poI11WUSYyfjIatH2hfq7qGrbqIBlbq4S7vAjAAhS+KS8TxV8 5woiYW5ZUA5Il7RUYHhP1Ry/YyXRyBxz8Ox2BtJMlMkWsKjuc9kKYiDOiacib9sy0i aPfPMZkkYmDggAK37mahkCnICO1fDZeN0JaiIFzgSxGeXShgdXEF1DAYPxU22ln/Di kGzFe7xSqPBokwQ8jjNqfX2hYMIrPy1ah7XaTQx6UwViWPpfyLEfsPSfZ5MEsWr3Ps NAkXFU5X3exlg== Date: Wed, 28 Jul 2021 17:00:53 +0300 From: Georgi Djakov To: Sai Prakash Ranjan Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Message-ID: <20210728140052.GB22887@mms-0441> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: isaacm@codeaurora.org, David Airlie , Will Deacon , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Sean Paul , Jordan Crouse , Kristian H Kristensen , dri-devel@lists.freedesktop.org, Daniel Vetter , linux-arm-msm@vger.kernel.org, freedreno , Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache. Now that system cache support for GPU is added, we will > need to set the right PTE attribute for GPU buffers to be sys cached. > Without this, the system cache lines are not allocated for GPU. > > So the patches in this series introduces a new prot flag IOMMU_LLC, > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > and makes GPU the user of this protection flag. Hi Sai, Thank you for the patchset! Are you planning to refresh it, as it does not apply anymore? Thanks, Georgi > > The series slightly depends on following 2 patches posted earlier and > is based on msm-next branch: > * https://lore.kernel.org/patchwork/patch/1363008/ > * https://lore.kernel.org/patchwork/patch/1363010/ > > Sai Prakash Ranjan (3): > iommu/io-pgtable: Rename last-level cache quirk to > IO_PGTABLE_QUIRK_PTW_LLC > iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag > drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 3 +++ > drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ > drivers/iommu/io-pgtable-arm.c | 9 ++++++--- > include/linux/io-pgtable.h | 6 +++--- > include/linux/iommu.h | 6 ++++++ > 7 files changed, 26 insertions(+), 7 deletions(-) > > > base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB478C4338F for ; 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b=uSK3rYX334vCPmIzWf/THTX34yLnn8ni/QBiKG2wSaCIb8flS7V+h/B0eP4sytljM /dQCjspApub1KKi22poI11WUSYyfjIatH2hfq7qGrbqIBlbq4S7vAjAAhS+KS8TxV8 5woiYW5ZUA5Il7RUYHhP1Ry/YyXRyBxz8Ox2BtJMlMkWsKjuc9kKYiDOiacib9sy0i aPfPMZkkYmDggAK37mahkCnICO1fDZeN0JaiIFzgSxGeXShgdXEF1DAYPxU22ln/Di kGzFe7xSqPBokwQ8jjNqfX2hYMIrPy1ah7XaTQx6UwViWPpfyLEfsPSfZ5MEsWr3Ps NAkXFU5X3exlg== Date: Wed, 28 Jul 2021 17:00:53 +0300 From: Georgi Djakov To: Sai Prakash Ranjan Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , isaacm@codeaurora.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno , Kristian H Kristensen , Sean Paul , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Message-ID: <20210728140052.GB22887@mms-0441> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210728_070101_113173_344CC971 X-CRM114-Status: GOOD ( 19.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache. Now that system cache support for GPU is added, we will > need to set the right PTE attribute for GPU buffers to be sys cached. > Without this, the system cache lines are not allocated for GPU. > > So the patches in this series introduces a new prot flag IOMMU_LLC, > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > and makes GPU the user of this protection flag. Hi Sai, Thank you for the patchset! Are you planning to refresh it, as it does not apply anymore? Thanks, Georgi > > The series slightly depends on following 2 patches posted earlier and > is based on msm-next branch: > * https://lore.kernel.org/patchwork/patch/1363008/ > * https://lore.kernel.org/patchwork/patch/1363010/ > > Sai Prakash Ranjan (3): > iommu/io-pgtable: Rename last-level cache quirk to > IO_PGTABLE_QUIRK_PTW_LLC > iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag > drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 3 +++ > drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ > drivers/iommu/io-pgtable-arm.c | 9 ++++++--- > include/linux/io-pgtable.h | 6 +++--- > include/linux/iommu.h | 6 ++++++ > 7 files changed, 26 insertions(+), 7 deletions(-) > > > base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93840C4338F for ; Wed, 28 Jul 2021 14:01:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5992A60E9B for ; Wed, 28 Jul 2021 14:01:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5992A60E9B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CCDBA6EAC4; Wed, 28 Jul 2021 14:01:00 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D7406EAC4; Wed, 28 Jul 2021 14:01:00 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id A326E600EF; Wed, 28 Jul 2021 14:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627480860; bh=sNNg1eBjaBERoOL+pNGqJG1GnXOiFtnWCHGA3ZA1guw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uSK3rYX334vCPmIzWf/THTX34yLnn8ni/QBiKG2wSaCIb8flS7V+h/B0eP4sytljM /dQCjspApub1KKi22poI11WUSYyfjIatH2hfq7qGrbqIBlbq4S7vAjAAhS+KS8TxV8 5woiYW5ZUA5Il7RUYHhP1Ry/YyXRyBxz8Ox2BtJMlMkWsKjuc9kKYiDOiacib9sy0i aPfPMZkkYmDggAK37mahkCnICO1fDZeN0JaiIFzgSxGeXShgdXEF1DAYPxU22ln/Di kGzFe7xSqPBokwQ8jjNqfX2hYMIrPy1ah7XaTQx6UwViWPpfyLEfsPSfZ5MEsWr3Ps NAkXFU5X3exlg== Date: Wed, 28 Jul 2021 17:00:53 +0300 From: Georgi Djakov To: Sai Prakash Ranjan Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Message-ID: <20210728140052.GB22887@mms-0441> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaacm@codeaurora.org, David Airlie , Will Deacon , Joerg Roedel , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Sean Paul , Jordan Crouse , Kristian H Kristensen , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno , Robin Murphy , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache. Now that system cache support for GPU is added, we will > need to set the right PTE attribute for GPU buffers to be sys cached. > Without this, the system cache lines are not allocated for GPU. > > So the patches in this series introduces a new prot flag IOMMU_LLC, > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > and makes GPU the user of this protection flag. Hi Sai, Thank you for the patchset! Are you planning to refresh it, as it does not apply anymore? Thanks, Georgi > > The series slightly depends on following 2 patches posted earlier and > is based on msm-next branch: > * https://lore.kernel.org/patchwork/patch/1363008/ > * https://lore.kernel.org/patchwork/patch/1363010/ > > Sai Prakash Ranjan (3): > iommu/io-pgtable: Rename last-level cache quirk to > IO_PGTABLE_QUIRK_PTW_LLC > iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag > drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 3 +++ > drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ > drivers/iommu/io-pgtable-arm.c | 9 ++++++--- > include/linux/io-pgtable.h | 6 +++--- > include/linux/iommu.h | 6 ++++++ > 7 files changed, 26 insertions(+), 7 deletions(-) > > > base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >