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Wed, 28 Jul 2021 17:56:15 +0000 (GMT) Received: from localhost.localdomain (unknown [9.102.1.109]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 3B13652050; Wed, 28 Jul 2021 17:56:11 +0000 (GMT) From: Parth Shah To: linuxppc-dev@lists.ozlabs.org Subject: [PATCHv2 0/3] Subject: [PATCHv2 0/3] Make cache-object aware of L3 siblings by parsing "ibm, thread-groups" property Date: Wed, 28 Jul 2021 23:26:04 +0530 Message-Id: <20210728175607.591679-1-parth@linux.ibm.com> X-Mailer: git-send-email 2.26.3 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FSesK1WUlaNKzZgds2cvNtqBph7JxHbZ X-Proofpoint-ORIG-GUID: QdvteKlnFTtwC56ZP9UyKcFsbktVDUsq Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-28_08:2021-07-27, 2021-07-28 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1011 mlxlogscore=999 mlxscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107280099 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, mikey@neuling.org, srikar@linux.vnet.ibm.com, parths1229@gmail.com, svaidy@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Changes from v1 -> v2: - Based on Gautham's comments, use a separate thread_group_l3_cache_map and modify parsing code to build cache_map for L3. This makes the cache_map building code isolated from the parsing code. v1 can be found at: https://lists.ozlabs.org/pipermail/linuxppc-dev/2021-June/230680.html On POWER10 big-core system, the L3 cache reflected by sysfs contains all the CPUs in the big-core. grep . /sys/devices/system/cpu/cpu0/cache/index*/shared_cpu_list /sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index3/shared_cpu_list:0-7 In the above example, CPU-0 observes CPU 0-7 in L3 (index3) cache, which is not correct as only the CPUs in small core share the L3 cache. The "ibm,thread-groups" contains property "2" to indicate that the CPUs share both the L2 and L3 caches. This patch-set uses this property to reflect correct L3 topology to a cache-object. After applying this patch-set, the topology looks like: $> ppc64_cpu --smt=8 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9,11,13,15 $> ppc64_cpu --smt=4 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9,11 $> ppc64_cpu --smt=2 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9 $> ppc64_cpu --smt=1 grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8 Patches Organization: ===================== This patch-set series is based on top of v5.14-rc2 - Patch 1-2: Add functionality to introduce awareness for "ibm,thread-groups". Original (not merged) posted version can be found at: https://lore.kernel.org/linuxppc-dev/1611041780-8640-1-git-send-email-ego@linux.vnet.ibm.co - Patch 3: Use existing L2 cache_map to detect L3 cache siblings Gautham R. Shenoy (2): powerpc/cacheinfo: Lookup cache by dt node and thread-group id powerpc/cacheinfo: Remove the redundant get_shared_cpu_map() Parth Shah (1): powerpc/smp: Use existing L2 cache_map cpumask to find L3 cache siblings arch/powerpc/include/asm/smp.h | 6 ++ arch/powerpc/kernel/cacheinfo.c | 124 ++++++++++++++++---------------- arch/powerpc/kernel/smp.c | 70 ++++++++++++------ 3 files changed, 115 insertions(+), 85 deletions(-) -- 2.26.3