From: Peter Geis <pgwipeout@gmail.com> To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de> Cc: Peter Geis <pgwipeout@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Date: Wed, 28 Jul 2021 14:00:29 -0400 [thread overview] Message-ID: <20210728180034.717953-4-pgwipeout@gmail.com> (raw) In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f7ecdfd66f86..c2aa7aeec58d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfdd60000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -761,7 +761,7 @@ gpio1: gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe740000 0x0 0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -772,7 +772,7 @@ gpio2: gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe750000 0x0 0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -783,7 +783,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe760000 0x0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -794,7 +794,7 @@ gpio4: gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe770000 0x0 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- 2.25.1
WARNING: multiple messages have this Message-ID
From: Peter Geis <pgwipeout@gmail.com> To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de> Cc: Peter Geis <pgwipeout@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Date: Wed, 28 Jul 2021 14:00:29 -0400 [thread overview] Message-ID: <20210728180034.717953-4-pgwipeout@gmail.com> (raw) In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f7ecdfd66f86..c2aa7aeec58d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfdd60000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -761,7 +761,7 @@ gpio1: gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe740000 0x0 0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -772,7 +772,7 @@ gpio2: gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe750000 0x0 0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -783,7 +783,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe760000 0x0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -794,7 +794,7 @@ gpio4: gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe770000 0x0 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID
From: Peter Geis <pgwipeout@gmail.com> To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de> Cc: Peter Geis <pgwipeout@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Date: Wed, 28 Jul 2021 14:00:29 -0400 [thread overview] Message-ID: <20210728180034.717953-4-pgwipeout@gmail.com> (raw) In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f7ecdfd66f86..c2aa7aeec58d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfdd60000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -761,7 +761,7 @@ gpio1: gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe740000 0x0 0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -772,7 +772,7 @@ gpio2: gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe750000 0x0 0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -783,7 +783,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe760000 0x0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -794,7 +794,7 @@ gpio4: gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe770000 0x0 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-28 18:01 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-28 18:00 [PATCH v2 0/8] fixes and enablement for rk356x Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 1/8] arm64: dts: rockchip: fix rk3568 mbi-alias Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 2/8] clk: rockchip: fix clk-pll rk356x early pll init Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis [this message] 2021-07-28 18:00 ` [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 4/8] arm64: dts: rockchip: add rk356x gmac1 node Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 21:17 ` Heiko Stübner 2021-07-28 21:17 ` Heiko Stübner 2021-07-28 21:17 ` Heiko Stübner 2021-07-28 18:00 ` [PATCH v2 6/8] arm64: dts: rockchip: adjust rk3568 pll clocks Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 7/8] arm64: dts: rockchip: enable gmac node on quartz64-a Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` [PATCH v2 8/8] arm64: dts: rockchip: add thermal support to Quartz64 Model A Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-28 18:00 ` Peter Geis 2021-07-29 13:19 ` (subset) [PATCH v2 0/8] fixes and enablement for rk356x Heiko Stuebner 2021-07-29 13:19 ` Heiko Stuebner 2021-07-29 13:19 ` Heiko Stuebner 2021-08-18 21:25 ` Heiko Stuebner 2021-08-18 21:25 ` Heiko Stuebner 2021-08-18 21:25 ` Heiko Stuebner 2021-08-18 21:42 ` Heiko Stuebner 2021-08-18 21:42 ` Heiko Stuebner 2021-08-18 21:42 ` Heiko Stuebner
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