From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH for-6.2 00/43] Unaligned accesses for user-only
Date: Wed, 28 Jul 2021 14:46:04 -1000 [thread overview]
Message-ID: <20210729004647.282017-1-richard.henderson@linaro.org> (raw)
This began with Peter wanting a cpu_ldst.h interface that can handle
alignment info for Arm M-profile system mode, which will also compile
for user-only without ifdefs. This is patch 32.
Once I had that interface, I thought I might as well enforce the
requested alignment in user-only. There are plenty of cases where
we ought to have been doing that for quite a while. This took rather
more work than I imagined to start.
So far only x86 host has been fully converted to handle unaligned
operations in user-only mode. I'll get to the others later. But
the added testcase is fairly broad, and caught lots of bugs and/or
missing code between target/ and linux-user/.
Notes:
* For target/i386 we have no way to signal SIGBUS from user-only.
In theory we could go through do_unaligned_access in system mode,
via #AC. But we don't even implement that control in tcg, probably
because no one ever sets it. The cmpxchg16b insn requires alignment,
but raises #GP, which maps to SIGSEGV.
* For target/s390x we have no way to signal SIGBUS from user-only.
The atomic operations raise PGM_SPECIFICATION, which the linux
kernel maps to SIGILL.
* I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
In the meantime, all memory accesses are allowed to be unaligned.
r~
Richard Henderson (43):
hw/core: Make do_unaligned_access available to user-only
target/alpha: Implement do_unaligned_access for user-only
target/arm: Implement do_unaligned_access for user-only
target/hppa: Implement do_unaligned_access for user-only
target/microblaze: Implement do_unaligned_access for user-only
target/mips: Implement do_unaligned_access for user-only
target/ppc: Set fault address in ppc_cpu_do_unaligned_access
target/ppc: Implement do_unaligned_access for user-only
target/riscv: Implement do_unaligned_access for user-only
target/s390x: Implement do_unaligned_access for user-only
target/sh4: Set fault address in superh_cpu_do_unaligned_access
target/sh4: Implement do_unaligned_access for user-only
target/sparc: Remove DEBUG_UNALIGNED
target/sparc: Set fault address in sparc_cpu_do_unaligned_access
target/sparc: Implement do_unaligned_access for user-only
target/xtensa: Implement do_unaligned_access for user-only
accel/tcg: Report unaligned atomics for user-only
accel/tcg: Drop signness in tracing in cputlb.c
tcg: Expand MO_SIZE to 3 bits
tcg: Rename TCGMemOpIdx to MemOpIdx
tcg: Split out MemOpIdx to exec/memopidx.h
trace/mem: Pass MemOpIdx to trace_mem_get_info
accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu
accel/tcg: Pass MemOpIdx to atomic_trace_*_post
plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
trace: Split guest_mem_before
target/arm: Use MO_128 for 16 byte atomics
target/i386: Use MO_128 for 16 byte atomics
target/ppc: Use MO_128 for 16 byte atomics
target/s390x: Use MO_128 for 16 byte atomics
target/hexagon: Implement cpu_mmu_index
accel/tcg: Add cpu_{ld,st}*_mmu interfaces
accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h
target/mips: Use cpu_*_data_ra for msa load/store
target/mips: Use 8-byte memory ops for msa load/store
target/s390x: Use cpu_*_mmu instead of helper_*_mmu
target/sparc: Use cpu_*_mmu instead of helper_*_mmu
target/arm: Use cpu_*_mmu instead of helper_*_mmu
tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h
linux-user/alpha: Remove TARGET_ALIGNED_ONLY
tcg: Add helper_unaligned_mmu for user-only sigbus
tcg/i386: Support raising sigbus for user-only
tests/tcg/multiarch: Add sigbus.c
configs/targets/alpha-linux-user.mak | 1 -
accel/tcg/atomic_template.h | 74 ++--
include/exec/cpu_ldst.h | 332 +++++++++---------
include/exec/memop.h | 14 +-
include/exec/memopidx.h | 55 +++
include/hw/core/tcg-cpu-ops.h | 14 +-
include/qemu/plugin.h | 26 +-
include/tcg/tcg-ldst.h | 79 +++++
include/tcg/tcg.h | 197 +----------
target/hexagon/cpu.h | 9 +
tcg/i386/tcg-target.h | 2 -
trace/mem.h | 63 ----
accel/tcg/cputlb.c | 486 +++++++++------------------
accel/tcg/plugin-gen.c | 5 +-
accel/tcg/user-exec.c | 444 ++++++++++--------------
linux-user/aarch64/cpu_loop.c | 4 +
linux-user/arm/cpu_loop.c | 43 ++-
linux-user/hppa/cpu_loop.c | 2 +-
linux-user/mips/cpu_loop.c | 20 +-
linux-user/ppc/cpu_loop.c | 2 +-
linux-user/riscv/cpu_loop.c | 7 +
linux-user/sh4/cpu_loop.c | 8 +
linux-user/sparc/cpu_loop.c | 11 +
plugins/api.c | 19 +-
plugins/core.c | 10 +-
target/alpha/cpu.c | 2 +-
target/alpha/mem_helper.c | 8 +-
target/alpha/translate.c | 8 +-
target/arm/cpu.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
target/arm/helper-a64.c | 77 ++---
target/arm/m_helper.c | 8 +-
target/arm/translate-a64.c | 2 +-
target/hppa/cpu.c | 8 +-
target/i386/tcg/mem_helper.c | 4 +-
target/m68k/op_helper.c | 3 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/mips/tcg/msa_helper.c | 395 +++++-----------------
target/mips/tcg/op_helper.c | 3 +-
target/mips/tcg/user/tlb_helper.c | 23 +-
target/ppc/cpu_init.c | 2 +-
target/ppc/excp_helper.c | 2 +
target/ppc/mem_helper.c | 1 -
target/ppc/translate.c | 12 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 8 +-
target/s390x/cpu.c | 2 +-
target/s390x/tcg/excp_helper.c | 28 +-
target/s390x/tcg/mem_helper.c | 31 +-
target/sh4/cpu.c | 2 +-
target/sh4/op_helper.c | 8 +-
target/sparc/cpu.c | 2 +-
target/sparc/ldst_helper.c | 33 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 30 +-
tcg/optimize.c | 2 +-
tcg/tcg-op.c | 60 ++--
tcg/tcg.c | 3 +-
tcg/tci.c | 15 +-
tests/tcg/multiarch/sigbus.c | 68 ++++
accel/tcg/atomic_common.c.inc | 43 +--
accel/tcg/ldst_common.c.inc | 307 +++++++++++++++++
target/s390x/tcg/translate_vx.c.inc | 2 +-
tcg/aarch64/tcg-target.c.inc | 18 +-
tcg/arm/tcg-target.c.inc | 14 +-
tcg/i386/tcg-target.c.inc | 128 ++++++-
tcg/mips/tcg-target.c.inc | 16 +-
tcg/ppc/tcg-target.c.inc | 18 +-
tcg/riscv/tcg-target.c.inc | 20 +-
tcg/s390/tcg-target.c.inc | 14 +-
tcg/sparc/tcg-target.c.inc | 20 +-
tcg/tcg-ldst.c.inc | 2 +-
trace-events | 18 +-
74 files changed, 1699 insertions(+), 1710 deletions(-)
create mode 100644 include/exec/memopidx.h
create mode 100644 include/tcg/tcg-ldst.h
delete mode 100644 trace/mem.h
create mode 100644 tests/tcg/multiarch/sigbus.c
create mode 100644 accel/tcg/ldst_common.c.inc
--
2.25.1
next reply other threads:[~2021-07-29 0:50 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-29 0:46 Richard Henderson [this message]
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-07-29 6:14 ` Philippe Mathieu-Daudé
2021-07-29 6:19 ` Philippe Mathieu-Daudé
2021-07-29 17:51 ` Richard Henderson
2021-07-29 13:05 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
2021-07-29 13:05 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 03/43] target/arm: " Richard Henderson
2021-07-29 13:14 ` Peter Maydell
2021-07-29 18:51 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 04/43] target/hppa: " Richard Henderson
2021-07-29 13:15 ` Peter Maydell
2021-07-29 17:55 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 05/43] target/microblaze: " Richard Henderson
2021-07-29 8:26 ` Philippe Mathieu-Daudé
2021-07-29 13:26 ` Peter Maydell
2021-07-29 18:00 ` Richard Henderson
2021-07-29 18:44 ` Edgar E. Iglesias
2021-07-29 0:46 ` [PATCH for-6.2 06/43] target/mips: " Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-07-29 13:44 ` Peter Maydell
2021-07-29 18:05 ` Richard Henderson
2021-07-30 17:13 ` Cédric Le Goater
2021-07-30 17:23 ` Cédric Le Goater
2021-07-30 16:58 ` Cédric Le Goater
2021-07-29 0:46 ` [PATCH for-6.2 08/43] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 09/43] target/riscv: " Richard Henderson
2021-07-30 6:13 ` Alistair Francis
2021-07-30 6:13 ` Alistair Francis
2021-07-29 0:46 ` [PATCH for-6.2 10/43] target/s390x: " Richard Henderson
2021-07-29 8:03 ` David Hildenbrand
2021-07-29 0:46 ` [PATCH for-6.2 11/43] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-07-29 6:15 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
2021-07-29 13:52 ` Peter Maydell
2021-07-30 0:01 ` Richard Henderson
2021-07-30 20:54 ` Rob Landley
2021-07-29 0:46 ` [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-07-29 6:16 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-07-29 14:51 ` Peter Maydell
2021-08-01 15:56 ` Mark Cave-Ayland
2021-08-01 15:59 ` Peter Maydell
2021-08-01 16:13 ` Mark Cave-Ayland
2021-07-29 0:46 ` [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
2021-07-29 9:40 ` Philippe Mathieu-Daudé
2021-07-29 18:20 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 16/43] target/xtensa: " Richard Henderson
2021-07-29 8:10 ` Philippe Mathieu-Daudé
2021-07-29 14:55 ` Peter Maydell
2021-07-29 18:22 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics " Richard Henderson
2021-07-29 15:02 ` Peter Maydell
2021-07-29 19:55 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 18/43] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits Richard Henderson
2021-07-29 6:23 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
2021-07-29 6:27 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
2021-07-29 6:27 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 22/43] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu Richard Henderson
2021-07-29 6:29 ` [PATCH for-6.1? " Philippe Mathieu-Daudé
2021-07-29 18:37 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 24/43] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
2021-07-29 6:31 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
2021-08-30 21:26 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 26/43] trace: Split guest_mem_before Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 27/43] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-07-29 6:32 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 28/43] target/i386: " Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 29/43] target/ppc: " Richard Henderson
2021-07-29 6:34 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 30/43] target/s390x: " Richard Henderson
2021-07-29 6:33 ` Philippe Mathieu-Daudé
2021-07-29 8:04 ` David Hildenbrand
2021-07-29 0:46 ` [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-07-29 2:37 ` Taylor Simpson
2021-07-29 6:35 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 32/43] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-07-29 7:36 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-07-29 7:38 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 35/43] target/mips: Use 8-byte memory ops " Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-07-29 7:39 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 37/43] target/sparc: " Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 38/43] target/arm: " Richard Henderson
2021-07-29 7:41 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-07-29 7:42 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 42/43] tcg/i386: Support raising sigbus for user-only Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 43/43] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2021-07-29 6:14 ` [PATCH for-6.2 00/43] Unaligned accesses for user-only Philippe Mathieu-Daudé
2021-07-29 14:01 ` Claudio Fontana
2021-08-02 13:14 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210729004647.282017-1-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.