From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE72EC4338F for ; Thu, 29 Jul 2021 15:42:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B82CD60F01 for ; Thu, 29 Jul 2021 15:42:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B82CD60F01 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=S82ENXPqBhB9+cmGYMHc2HEO0tWMMsMEG+lbh7z6nQs=; b=pa+D0WrmphZ2Mv Mi8RnBrPwEOQnW0UrFYaWe5+3A+bLq7RtTFC5bypv1X3yLxem2hNR7wlm+jc+B7FsTByY2zvvkbyb Upk3ne/dtfBRJzy6tO8LnN+NNzYzUoJ2HC0rykBpiGKhKAiL7MrByJfKDjyBYkAyA8KrgHS6/1TDM YZV8Rd7O2IICC9bBnVVaPH8RyVsHZPPVzNgOQjyy6nqD35AQIvlGPIhO2z2VkiX3mFppiHrq6HVXG 527rf1UoqeINUvm9CL0QaipQc1tjbluKJLBAFiEhr5NpylEUgEjG+M3Wh0cGNR4JTMpbB3eQaAkVL uCSO6gazca3aVQQQtQEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m988Y-004lu5-44; Thu, 29 Jul 2021 15:39:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m984X-004kWN-QN for linux-arm-kernel@lists.infradead.org; Thu, 29 Jul 2021 15:35:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56FA86D; Thu, 29 Jul 2021 08:35:44 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89AE03F73D; Thu, 29 Jul 2021 08:35:43 -0700 (PDT) Date: Thu, 29 Jul 2021 16:34:22 +0100 From: Dave Martin To: Sebastian Andrzej Siewior Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Thomas Gleixner Subject: Re: [PATCH] arm64/sve: Make kernel FPU protection RT friendly Message-ID: <20210729153422.GN1724@arm.com> References: <20210729105215.2222338-1-bigeasy@linutronix.de> <20210729105215.2222338-3-bigeasy@linutronix.de> <20210729135459.GL1724@arm.com> <20210729141748.q66pfjoma2a2qd2k@linutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210729141748.q66pfjoma2a2qd2k@linutronix.de> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_083546_050013_01B7AF3B X-CRM114-Status: GOOD ( 33.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 29, 2021 at 04:17:48PM +0200, Sebastian Andrzej Siewior wrote: > On 2021-07-29 14:54:59 [+0100], Dave Martin wrote: > > > index e098f6c67b1de..a208514bd69a9 100644 > > > --- a/arch/arm64/kernel/fpsimd.c > > > +++ b/arch/arm64/kernel/fpsimd.c > > > @@ -177,10 +177,19 @@ static void __get_cpu_fpsimd_context(void) > > > * > > > * The double-underscore version must only be called if you know the task > > > * can't be preempted. > > > + * > > > + * On RT kernels local_bh_disable() is not sufficient because it only > > > + * serializes soft interrupt related sections via a local lock, but stays > > > + * preemptible. Disabling preemption is the right choice here as bottom > > > + * half processing is always in thread context on RT kernels so it > > > + * implicitly prevents bottom half processing as well. > > > */ > > > static void get_cpu_fpsimd_context(void) > > > { > > > - local_bh_disable(); > > > + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) > > > + local_bh_disable(); > > > + else > > > + preempt_disable(); > > > > Is this wrongly abstracted for RT? > > No, we want to keep BH preemptible. Say your NAPI callback is busy for > the next 200us and your RT task needs the CPU now. > > > The requirement here is that the code should temporarily be > > nonpreemptible by anything except hardirq context. > > That is what I assumed. > > > Having to do this conditional everywhere that is required feels fragile. > > Is a similar thing needed anywhere else? > > pssst. I wisper now so that the other don't hear us. If you look at > arch/x86/include/asm/fpu/api.h and search for fpregs_lock() then you > find the same pattern. Even some of the comments look similar. And > please don't look up the original commit :) > x86 restores the FPU registers on return to userland (not immediately on > context switch) and requires the same kind of synchronisation/ > protection regarding other tasks and crypto in softirq. So it should be > more the same thing that arm64 does here. That rather suggests to me that it is worth factoring this and giving it a name, precisely because irrespectively of CONFIG_PREEMPT_RT, we need to make sure that to task swtich _and_ no bh runs on the same cpu. The problem seems to be that the local_bh_disable() API doesn't express the difference between wanting to prevent local bh processing and wanting to prevent local bh _and_ task switch. So, could this be wrapped up and called something like: preempt_and_local_bh_disable() ... local_bh_and_preempt_enable()? I do wonder whether there are other places making the same assumption about the local_irq > local_bh > preempt hierarchy that have been missed... > > If bh (as a preempting context) doesn't exist on RT, then can't > > local_bh_disable() just suppress all preemption up to but excluding > > hardirq? Would anything break? > > Yes. A lot. Starting with spin_lock_bh() itself because it does: > local_bh_disable(); > spin_lock() > > and with disabled preemption you can't do spin_lock() and you have to > because the owner may be preempted. The next thing is that kmalloc() and > friends won't work in a local_bh_disable() section for the same reason. Couldn't this be solved with a trylock loop that re-enables bh (and preemption) on the sleeping path? But that may still be trying to achieve something that doesn't make sense given the goals of PREEMPT_RT(?) > The list goes on. > > Sebastian Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel