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From: Matthew Brost <matthew.brost@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 0/4] Enable GuC submission by default on DG1
Date: Tue, 3 Aug 2021 17:26:23 +0000	[thread overview]
Message-ID: <20210803172623.GA82856@DUT151-ICLU.fm.intel.com> (raw)
In-Reply-To: <CAKMK7uGOAx7xM=6nDGtLqqW7sf2Rjbj24hAu8U9NK9J2t5+LwQ@mail.gmail.com>

On Tue, Aug 03, 2021 at 02:15:13PM +0200, Daniel Vetter wrote:
> On Tue, Aug 3, 2021 at 6:53 AM Matthew Brost <matthew.brost@intel.com> wrote:
> >
> > Minimum set of patches to enable GuC submission on DG1 and enable it by
> > default.
> >
> > A little difficult to test as IGTs do not work with DG1 due to a bunch
> > of uAPI features being disabled (e.g. relocations, caching memory
> > options, etc...).
> 
> Matt Auld has an igt series which fixes a lot of this stuff, would be
> good to do at least a Test-With run with that.
> 

If I'm understanding his series correct it only fixes the mmap issues
not relocs so I don't think it will help all that much. I probably could
send a trybot series letting relocs work on DG1 + his series and that
might work? I guess I'll find out.

> Also I'm assuming that for ADL-P we'll get this equivalent patch set

GuC submission is enabled by default on ADL-P. We don't have ADL-P in
pre-merge CI currently though :(, just offline runs of about 1800 tests.
Still a awaiting results for that though.

For what it is worth I've run all 1800 locally, via a script, and gotten
solid results back with my IGT updates. There are some failures but I
believe I understand all of them as either test issues or known
differences in behavior between execlists and GuC submission with are
opens (e.g. persistence, semaphores, SUBMIT fence, etc...).

Matt

> soon, and there we should be able to get real results?
> -Daniel
> 
> >
> > Tested with the loading the driver and 'live' selftests. Submissions
> > seem to work.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >
> > Daniele Ceraolo Spurio (1):
> >   drm/i915/guc: put all guc objects in lmem when available
> >
> > Matthew Brost (2):
> >   drm/i915/guc: Add DG1 GuC / HuC firmware defs
> >   drm/i915/guc: Enable GuC submission by default on DG1
> >
> > Venkata Sandeep Dhanalakota (1):
> >   drm/i915: Do not define vma on stack
> >
> >  drivers/gpu/drm/i915/gem/i915_gem_lmem.c  | 26 +++++++
> >  drivers/gpu/drm/i915/gem/i915_gem_lmem.h  |  4 +
> >  drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  9 ++-
> >  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 ++-
> >  drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 14 +++-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc.c     |  2 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 90 ++++++++++++++++++++---
> >  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  2 +
> >  8 files changed, 138 insertions(+), 20 deletions(-)
> >
> > --
> > 2.28.0
> >
> 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 0/4] Enable GuC submission by default on DG1
Date: Tue, 3 Aug 2021 17:26:23 +0000	[thread overview]
Message-ID: <20210803172623.GA82856@DUT151-ICLU.fm.intel.com> (raw)
In-Reply-To: <CAKMK7uGOAx7xM=6nDGtLqqW7sf2Rjbj24hAu8U9NK9J2t5+LwQ@mail.gmail.com>

On Tue, Aug 03, 2021 at 02:15:13PM +0200, Daniel Vetter wrote:
> On Tue, Aug 3, 2021 at 6:53 AM Matthew Brost <matthew.brost@intel.com> wrote:
> >
> > Minimum set of patches to enable GuC submission on DG1 and enable it by
> > default.
> >
> > A little difficult to test as IGTs do not work with DG1 due to a bunch
> > of uAPI features being disabled (e.g. relocations, caching memory
> > options, etc...).
> 
> Matt Auld has an igt series which fixes a lot of this stuff, would be
> good to do at least a Test-With run with that.
> 

If I'm understanding his series correct it only fixes the mmap issues
not relocs so I don't think it will help all that much. I probably could
send a trybot series letting relocs work on DG1 + his series and that
might work? I guess I'll find out.

> Also I'm assuming that for ADL-P we'll get this equivalent patch set

GuC submission is enabled by default on ADL-P. We don't have ADL-P in
pre-merge CI currently though :(, just offline runs of about 1800 tests.
Still a awaiting results for that though.

For what it is worth I've run all 1800 locally, via a script, and gotten
solid results back with my IGT updates. There are some failures but I
believe I understand all of them as either test issues or known
differences in behavior between execlists and GuC submission with are
opens (e.g. persistence, semaphores, SUBMIT fence, etc...).

Matt

> soon, and there we should be able to get real results?
> -Daniel
> 
> >
> > Tested with the loading the driver and 'live' selftests. Submissions
> > seem to work.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >
> > Daniele Ceraolo Spurio (1):
> >   drm/i915/guc: put all guc objects in lmem when available
> >
> > Matthew Brost (2):
> >   drm/i915/guc: Add DG1 GuC / HuC firmware defs
> >   drm/i915/guc: Enable GuC submission by default on DG1
> >
> > Venkata Sandeep Dhanalakota (1):
> >   drm/i915: Do not define vma on stack
> >
> >  drivers/gpu/drm/i915/gem/i915_gem_lmem.c  | 26 +++++++
> >  drivers/gpu/drm/i915/gem/i915_gem_lmem.h  |  4 +
> >  drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  9 ++-
> >  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 ++-
> >  drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 14 +++-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc.c     |  2 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 90 ++++++++++++++++++++---
> >  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  2 +
> >  8 files changed, 138 insertions(+), 20 deletions(-)
> >
> > --
> > 2.28.0
> >
> 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

  reply	other threads:[~2021-08-03 17:26 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-03  5:11 [PATCH 0/4] Enable GuC submission by default on DG1 Matthew Brost
2021-08-03  5:11 ` [Intel-gfx] " Matthew Brost
2021-08-03  5:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-08-03  5:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-03  5:11 ` [PATCH 1/4] drm/i915: Do not define vma on stack Matthew Brost
2021-08-03  5:11   ` [Intel-gfx] " Matthew Brost
2021-08-04 19:37   ` Matthew Brost
2021-08-03  5:11 ` [PATCH 2/4] drm/i915/guc: put all guc objects in lmem when available Matthew Brost
2021-08-03  5:11   ` [Intel-gfx] " Matthew Brost
2021-08-06 18:43   ` John Harrison
2021-08-03  5:11 ` [PATCH 3/4] drm/i915/guc: Add DG1 GuC / HuC firmware defs Matthew Brost
2021-08-03  5:11   ` [Intel-gfx] " Matthew Brost
2021-08-06 18:43   ` John Harrison
2021-08-03  5:11 ` [PATCH 4/4] drm/i915/guc: Enable GuC submission by default on DG1 Matthew Brost
2021-08-03  5:11   ` [Intel-gfx] " Matthew Brost
2021-08-06 18:44   ` John Harrison
2021-08-03  5:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-08-03 12:15 ` [PATCH 0/4] " Daniel Vetter
2021-08-03 12:15   ` [Intel-gfx] " Daniel Vetter
2021-08-03 17:26   ` Matthew Brost [this message]
2021-08-03 17:26     ` Matthew Brost
2021-08-06 11:34     ` Thomas Hellström (Intel)
2021-08-06 12:07       ` Thomas Hellström (Intel)
2021-08-06 16:09       ` Thomas Hellström (Intel)
2021-08-07 17:20       ` Matthew Brost
2021-08-03 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork

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