From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2EFBC4338F for ; Wed, 4 Aug 2021 10:20:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B069561004 for ; Wed, 4 Aug 2021 10:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237107AbhHDKU3 (ORCPT ); Wed, 4 Aug 2021 06:20:29 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:45042 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235522AbhHDKU2 (ORCPT ); Wed, 4 Aug 2021 06:20:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1628072415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=f2E3MlHdXnsphAvhfHhbLwmwP14YJkOfdq2TcSYdMj+pmh5wyPj3MX9QHKRsJCjEiPp7xS Lf/3uos83ONrujd2Fq80liDYZtz2WZiZ7MObEHnMrTBPZLwyliE5pxTZ3ETyfLP6B4AD02 7oC8fJYvGUsjbajuezD63+6kcjaGGyg= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-424-IvRF9RZ5O16_BnfUs_y84g-1; Wed, 04 Aug 2021 06:20:14 -0400 X-MC-Unique: IvRF9RZ5O16_BnfUs_y84g-1 Received: by mail-ed1-f69.google.com with SMTP id v26-20020aa7d9da0000b02903bda706c753so1215620eds.18 for ; Wed, 04 Aug 2021 03:20:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=eFdqUgSmjT3YSHgXoXsiFHq5V9UTP1QFrgG/lAVI6yHElgc3rGSV1sIO264YE9Y09x knDB3VIALK1RhRIBUMISkkPgXGqH2vlKRTKbdeoPJ7lDV1+2zPKP6PcUo9V4CwS75Yro GXujSpXYZSjTmjTIeREzLB1ZYM7cqpcZONeIIHHLwcO5cZ0FCf7B62fonGzPZ/Pd9zKm Uc5EKq2kbgS1KgIGWr+DgnBJ/W52jXzEQUg2Q+WWAoYpbBrB7j/fBTWMZ3sH2eg7VCQV R4zSKVIgSuOb/EVwtD97tmKQviqkC8zaF1rHnG7uAhXQ9iBb1uCeryKtQQdRiIiNH1uz KvaA== X-Gm-Message-State: AOAM533L4MdVu5hothVdwogN/lS4ja9LWYnGzC6HvRChFsldI2431Rx3 aVOrJKb5cFXqJxDLJbeBJjPhmSS/zytFhCQ7eRqvJR594/K2BvHA07wiJby44UzRnBbUMc93o5g 4CmettoZ1ftrK X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671603ejb.223.1628072413564; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybp6Q5XxRbGB4tUMy1zZgwfQUbAhHrD8DGApU6sxGqruuw3bd9FVaZMCtp9rMFmgSs9yfqVg== X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671582ejb.223.1628072413361; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Received: from gator.home (cst2-174-132.cust.vodafone.cz. [31.30.174.132]) by smtp.gmail.com with ESMTPSA id n13sm536160ejk.97.2021.08.04.03.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Date: Wed, 4 Aug 2021 12:20:10 +0200 From: Andrew Jones To: Oliver Upton Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Will Deacon , Catalin Marinas Subject: Re: [PATCH v6 13/21] KVM: arm64: Allow userspace to configure a vCPU's virtual offset Message-ID: <20210804102010.poou6o354rink6e4@gator.home> References: <20210804085819.846610-1-oupton@google.com> <20210804085819.846610-14-oupton@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210804085819.846610-14-oupton@google.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Aug 04, 2021 at 08:58:11AM +0000, Oliver Upton wrote: > Allow userspace to access the guest's virtual counter-timer offset > through the ONE_REG interface. The value read or written is defined to > be an offset from the guest's physical counter-timer. Add some > documentation to clarify how a VMM should use this and the existing > CNTVCT_EL0. > > Signed-off-by: Oliver Upton > --- > Documentation/virt/kvm/api.rst | 10 ++++++++++ > arch/arm64/include/uapi/asm/kvm.h | 1 + > arch/arm64/kvm/arch_timer.c | 11 +++++++++++ > arch/arm64/kvm/guest.c | 6 +++++- > include/kvm/arm_arch_timer.h | 1 + > 5 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index 8d4a3471ad9e..28a65dc89985 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -2487,6 +2487,16 @@ arm64 system registers have the following id bit patterns:: > derived from the register encoding for CNTV_CVAL_EL0. As this is > API, it must remain this way. > > +.. warning:: > + > + The value of KVM_REG_ARM_TIMER_OFFSET is defined as an offset from > + the guest's view of the physical counter-timer. > + > + Userspace should use either KVM_REG_ARM_TIMER_OFFSET or > + KVM_REG_ARM_TIMER_CVAL to pause and resume a guest's virtual > + counter-timer. Mixed use of these registers could result in an > + unpredictable guest counter value. > + > arm64 firmware pseudo-registers have the following bit pattern:: > > 0x6030 0000 0014 > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index b3edde68bc3e..949a31bc10f0 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -255,6 +255,7 @@ struct kvm_arm_copy_mte_tags { > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > +#define KVM_REG_ARM_TIMER_OFFSET ARM64_SYS_REG(3, 4, 14, 0, 3) > > /* KVM-as-firmware specific pseudo-registers */ > #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 4c2b763a8849..a8815b09da3e 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -868,6 +868,10 @@ int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) > timer = vcpu_vtimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CVAL, value); > break; > + case KVM_REG_ARM_TIMER_OFFSET: > + timer = vcpu_vtimer(vcpu); > + update_vtimer_cntvoff(vcpu, value); > + break; > case KVM_REG_ARM_PTIMER_CTL: > timer = vcpu_ptimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CTL, value); > @@ -912,6 +916,9 @@ u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) > case KVM_REG_ARM_TIMER_CVAL: > return kvm_arm_timer_read(vcpu, > vcpu_vtimer(vcpu), TIMER_REG_CVAL); > + case KVM_REG_ARM_TIMER_OFFSET: > + return kvm_arm_timer_read(vcpu, > + vcpu_vtimer(vcpu), TIMER_REG_OFFSET); > case KVM_REG_ARM_PTIMER_CTL: > return kvm_arm_timer_read(vcpu, > vcpu_ptimer(vcpu), TIMER_REG_CTL); > @@ -949,6 +956,10 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > val = kvm_phys_timer_read() - timer_get_offset(timer); > break; > > + case TIMER_REG_OFFSET: > + val = timer_get_offset(timer); > + break; > + > default: > BUG(); > } > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 1dfb83578277..17fc06e2b422 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -591,7 +591,7 @@ static unsigned long num_core_regs(const struct kvm_vcpu *vcpu) > * ARM64 versions of the TIMER registers, always available on arm64 > */ > > -#define NUM_TIMER_REGS 3 > +#define NUM_TIMER_REGS 4 > > static bool is_timer_reg(u64 index) > { > @@ -599,6 +599,7 @@ static bool is_timer_reg(u64 index) > case KVM_REG_ARM_TIMER_CTL: > case KVM_REG_ARM_TIMER_CNT: > case KVM_REG_ARM_TIMER_CVAL: > + case KVM_REG_ARM_TIMER_OFFSET: > return true; > } > return false; > @@ -614,6 +615,9 @@ static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) > uindices++; > if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices)) > return -EFAULT; > + uindices++; > + if (put_user(KVM_REG_ARM_TIMER_OFFSET, uindices)) > + return -EFAULT; > > return 0; > } > diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h > index 9d65d4a29f81..615f9314f6a5 100644 > --- a/include/kvm/arm_arch_timer.h > +++ b/include/kvm/arm_arch_timer.h > @@ -21,6 +21,7 @@ enum kvm_arch_timer_regs { > TIMER_REG_CVAL, > TIMER_REG_TVAL, > TIMER_REG_CTL, > + TIMER_REG_OFFSET, > }; > > struct arch_timer_context { > -- > 2.32.0.605.g8dce9f2422-goog > Reviewed-by: Andrew Jones From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0554DC4338F for ; Wed, 4 Aug 2021 10:20:21 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 56E9060FC3 for ; Wed, 4 Aug 2021 10:20:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 56E9060FC3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D258D4A003; Wed, 4 Aug 2021 06:20:19 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@redhat.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dNGLHqQTOLza; Wed, 4 Aug 2021 06:20:18 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 62F3F4A195; Wed, 4 Aug 2021 06:20:18 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 635CA49FA6 for ; Wed, 4 Aug 2021 06:20:17 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NYvLX2qOWuOG for ; Wed, 4 Aug 2021 06:20:16 -0400 (EDT) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2A03240FC7 for ; Wed, 4 Aug 2021 06:20:16 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1628072415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=f2E3MlHdXnsphAvhfHhbLwmwP14YJkOfdq2TcSYdMj+pmh5wyPj3MX9QHKRsJCjEiPp7xS Lf/3uos83ONrujd2Fq80liDYZtz2WZiZ7MObEHnMrTBPZLwyliE5pxTZ3ETyfLP6B4AD02 7oC8fJYvGUsjbajuezD63+6kcjaGGyg= Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-440-6OxH6AQRPkqWnBeJit5Hxg-1; Wed, 04 Aug 2021 06:20:14 -0400 X-MC-Unique: 6OxH6AQRPkqWnBeJit5Hxg-1 Received: by mail-ed1-f71.google.com with SMTP id n24-20020aa7c7980000b02903bb4e1d45aaso1204457eds.15 for ; Wed, 04 Aug 2021 03:20:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=NwVRdFzCBnNcxvwqswNSPE2C/+ibjrzqaC9qPsY4EtjfEh84XkubAmOMEZqefFw4D6 xAjjwgdCqkkrBzNX9t326/pu0fENe1cZSr1x0Sd6LiRPzsrjGhtVniqjMR+sSFm+fuws NUmi9sRTBQSIh2VIIt6k0YKX7VYImDH47nofwn/p5hqiXnUot4cBssdafeEcVyYbpIoi yogBVpA4Mk5Fusi2gUmz0NlsMKsbyRBfIxyoNGLINTqYN5AOSiwe4acRODrU2ELVxbgg Oeq60EO7/s+4wYkwoN8+kp+N7iBFxR3IlmPqwMWG321pA2CCc66A+eQP7uYHxGToZZvi KY+w== X-Gm-Message-State: AOAM531IZM9clKQ3eRZyI+0kFFEf69QRN2t4/KyDbbV8gfix04bysQWu 0MO0Tc4BD7gpja2HmvESW02/CVaL7KX/ONbe02gwogBr+6nAM5SM7g7TI3MN5wWTNeFIJn+C6z3 nzJ7FlAdQS0mLOKFT40KTyKGe X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671617ejb.223.1628072413657; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybp6Q5XxRbGB4tUMy1zZgwfQUbAhHrD8DGApU6sxGqruuw3bd9FVaZMCtp9rMFmgSs9yfqVg== X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671582ejb.223.1628072413361; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Received: from gator.home (cst2-174-132.cust.vodafone.cz. [31.30.174.132]) by smtp.gmail.com with ESMTPSA id n13sm536160ejk.97.2021.08.04.03.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Date: Wed, 4 Aug 2021 12:20:10 +0200 From: Andrew Jones To: Oliver Upton Subject: Re: [PATCH v6 13/21] KVM: arm64: Allow userspace to configure a vCPU's virtual offset Message-ID: <20210804102010.poou6o354rink6e4@gator.home> References: <20210804085819.846610-1-oupton@google.com> <20210804085819.846610-14-oupton@google.com> MIME-Version: 1.0 In-Reply-To: <20210804085819.846610-14-oupton@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline Cc: Catalin Marinas , kvm@vger.kernel.org, Will Deacon , Marc Zyngier , Raghavendra Rao Anata , Peter Shier , Sean Christopherson , David Matlack , Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Jim Mattson X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Aug 04, 2021 at 08:58:11AM +0000, Oliver Upton wrote: > Allow userspace to access the guest's virtual counter-timer offset > through the ONE_REG interface. The value read or written is defined to > be an offset from the guest's physical counter-timer. Add some > documentation to clarify how a VMM should use this and the existing > CNTVCT_EL0. > > Signed-off-by: Oliver Upton > --- > Documentation/virt/kvm/api.rst | 10 ++++++++++ > arch/arm64/include/uapi/asm/kvm.h | 1 + > arch/arm64/kvm/arch_timer.c | 11 +++++++++++ > arch/arm64/kvm/guest.c | 6 +++++- > include/kvm/arm_arch_timer.h | 1 + > 5 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index 8d4a3471ad9e..28a65dc89985 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -2487,6 +2487,16 @@ arm64 system registers have the following id bit patterns:: > derived from the register encoding for CNTV_CVAL_EL0. As this is > API, it must remain this way. > > +.. warning:: > + > + The value of KVM_REG_ARM_TIMER_OFFSET is defined as an offset from > + the guest's view of the physical counter-timer. > + > + Userspace should use either KVM_REG_ARM_TIMER_OFFSET or > + KVM_REG_ARM_TIMER_CVAL to pause and resume a guest's virtual > + counter-timer. Mixed use of these registers could result in an > + unpredictable guest counter value. > + > arm64 firmware pseudo-registers have the following bit pattern:: > > 0x6030 0000 0014 > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index b3edde68bc3e..949a31bc10f0 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -255,6 +255,7 @@ struct kvm_arm_copy_mte_tags { > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > +#define KVM_REG_ARM_TIMER_OFFSET ARM64_SYS_REG(3, 4, 14, 0, 3) > > /* KVM-as-firmware specific pseudo-registers */ > #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 4c2b763a8849..a8815b09da3e 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -868,6 +868,10 @@ int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) > timer = vcpu_vtimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CVAL, value); > break; > + case KVM_REG_ARM_TIMER_OFFSET: > + timer = vcpu_vtimer(vcpu); > + update_vtimer_cntvoff(vcpu, value); > + break; > case KVM_REG_ARM_PTIMER_CTL: > timer = vcpu_ptimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CTL, value); > @@ -912,6 +916,9 @@ u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) > case KVM_REG_ARM_TIMER_CVAL: > return kvm_arm_timer_read(vcpu, > vcpu_vtimer(vcpu), TIMER_REG_CVAL); > + case KVM_REG_ARM_TIMER_OFFSET: > + return kvm_arm_timer_read(vcpu, > + vcpu_vtimer(vcpu), TIMER_REG_OFFSET); > case KVM_REG_ARM_PTIMER_CTL: > return kvm_arm_timer_read(vcpu, > vcpu_ptimer(vcpu), TIMER_REG_CTL); > @@ -949,6 +956,10 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > val = kvm_phys_timer_read() - timer_get_offset(timer); > break; > > + case TIMER_REG_OFFSET: > + val = timer_get_offset(timer); > + break; > + > default: > BUG(); > } > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 1dfb83578277..17fc06e2b422 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -591,7 +591,7 @@ static unsigned long num_core_regs(const struct kvm_vcpu *vcpu) > * ARM64 versions of the TIMER registers, always available on arm64 > */ > > -#define NUM_TIMER_REGS 3 > +#define NUM_TIMER_REGS 4 > > static bool is_timer_reg(u64 index) > { > @@ -599,6 +599,7 @@ static bool is_timer_reg(u64 index) > case KVM_REG_ARM_TIMER_CTL: > case KVM_REG_ARM_TIMER_CNT: > case KVM_REG_ARM_TIMER_CVAL: > + case KVM_REG_ARM_TIMER_OFFSET: > return true; > } > return false; > @@ -614,6 +615,9 @@ static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) > uindices++; > if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices)) > return -EFAULT; > + uindices++; > + if (put_user(KVM_REG_ARM_TIMER_OFFSET, uindices)) > + return -EFAULT; > > return 0; > } > diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h > index 9d65d4a29f81..615f9314f6a5 100644 > --- a/include/kvm/arm_arch_timer.h > +++ b/include/kvm/arm_arch_timer.h > @@ -21,6 +21,7 @@ enum kvm_arch_timer_regs { > TIMER_REG_CVAL, > TIMER_REG_TVAL, > TIMER_REG_CTL, > + TIMER_REG_OFFSET, > }; > > struct arch_timer_context { > -- > 2.32.0.605.g8dce9f2422-goog > Reviewed-by: Andrew Jones _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08D58C4320A for ; Wed, 4 Aug 2021 10:22:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C546561004 for ; Wed, 4 Aug 2021 10:22:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C546561004 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g4tHNOQYQMBj5zw8f/QnSQ7SxhcAngxSUSR1d60ySIY=; b=Ltk3KjkVDpdB2t NjkGVPQee9YYVkp8zR055alO5MmlNnP8w/SFw8lxuh9YG8Vw4d9OAkYfViaMt/X5Wl2SURIJPLtUZ qQ5V+X1DMIjsNEGabMC0KMG7eEyRRKdwOO3/Vbiae5uGUH8JaMxxB9928/GDugB3SqxzxS+OO/pe6 LzgqrfhReCywtCa9gR4UYKtfvTiuljqTGWFL2Zk9fJrZNtGgVTXqcNQly6WhB1Hr8ovqon1HNeCmI xEjl1InSunDCAGV9OmcAhgV/SHjj5izgX9wCCcrIVmp8NbRwuBa8gI08foUmMRPO36QvySzJbjN3q XAB1PhlZcuFQAJGxbdwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mBE0j-005hN8-2L; Wed, 04 Aug 2021 10:20:30 +0000 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mBE0X-005hJy-0h for linux-arm-kernel@lists.infradead.org; Wed, 04 Aug 2021 10:20:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1628072415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=f2E3MlHdXnsphAvhfHhbLwmwP14YJkOfdq2TcSYdMj+pmh5wyPj3MX9QHKRsJCjEiPp7xS Lf/3uos83ONrujd2Fq80liDYZtz2WZiZ7MObEHnMrTBPZLwyliE5pxTZ3ETyfLP6B4AD02 7oC8fJYvGUsjbajuezD63+6kcjaGGyg= Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-541-EDUpJd0jPAG0fF8bqrYe_g-1; Wed, 04 Aug 2021 06:20:14 -0400 X-MC-Unique: EDUpJd0jPAG0fF8bqrYe_g-1 Received: by mail-ej1-f71.google.com with SMTP id qf6-20020a1709077f06b029057e66b6665aso660619ejc.18 for ; Wed, 04 Aug 2021 03:20:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TzuddHkqTHaeNbxF+wgJby3k6T0ZjRGzb/st0YjSDro=; b=n4WRgO2ii7FLWUvRd0bspZ80n8S3x322kiJbaN2KAjTHlYxNsdm3m1jXC1JDArq2Sj NbSstT/OqVzGRI5JcexFf669ZdAlag5LmSdFaAvsTpmLpsX8uIFCaIFBi79nPiawnm2A p6Y9PqtwzkrjLJ+5vTgJe3Z1yomRFbJzjEXvTYkDnqidWjlMFf/U4zjVkzuqSI9JZkMo VSAKqfVWVGTVFwHGYsYxb6I7S6pjXrTnSF/a8Eit3nmqU64Fr6jeSzoL5V3lzgziqNwa URTiGMfs9+hUrFpW7o+AjJU3UDygFWR7VcaA/Mu2ordxAsDtQdFuI8eJWAKZMCu/TKaT dteg== X-Gm-Message-State: AOAM532CpWckSNZkddwgKHgNJ08kfUasXiDOk/yujB4hD4QUs8O2J8Gz DvMUcl4n1pNDEDONROAps1jzf12EXc1c7SxkB23nzFi5f3cWUNdQZwy3A5XQYVnUueJz6/IEPoh 0VwmXmJXzOJLpRFE90ME+Ro63zwE4Em3C+h4= X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671612ejb.223.1628072413580; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybp6Q5XxRbGB4tUMy1zZgwfQUbAhHrD8DGApU6sxGqruuw3bd9FVaZMCtp9rMFmgSs9yfqVg== X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr25671582ejb.223.1628072413361; Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Received: from gator.home (cst2-174-132.cust.vodafone.cz. [31.30.174.132]) by smtp.gmail.com with ESMTPSA id n13sm536160ejk.97.2021.08.04.03.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 03:20:13 -0700 (PDT) Date: Wed, 4 Aug 2021 12:20:10 +0200 From: Andrew Jones To: Oliver Upton Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Will Deacon , Catalin Marinas Subject: Re: [PATCH v6 13/21] KVM: arm64: Allow userspace to configure a vCPU's virtual offset Message-ID: <20210804102010.poou6o354rink6e4@gator.home> References: <20210804085819.846610-1-oupton@google.com> <20210804085819.846610-14-oupton@google.com> MIME-Version: 1.0 In-Reply-To: <20210804085819.846610-14-oupton@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210804_032017_206286_8D9F7B58 X-CRM114-Status: GOOD ( 26.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 04, 2021 at 08:58:11AM +0000, Oliver Upton wrote: > Allow userspace to access the guest's virtual counter-timer offset > through the ONE_REG interface. The value read or written is defined to > be an offset from the guest's physical counter-timer. Add some > documentation to clarify how a VMM should use this and the existing > CNTVCT_EL0. > > Signed-off-by: Oliver Upton > --- > Documentation/virt/kvm/api.rst | 10 ++++++++++ > arch/arm64/include/uapi/asm/kvm.h | 1 + > arch/arm64/kvm/arch_timer.c | 11 +++++++++++ > arch/arm64/kvm/guest.c | 6 +++++- > include/kvm/arm_arch_timer.h | 1 + > 5 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index 8d4a3471ad9e..28a65dc89985 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -2487,6 +2487,16 @@ arm64 system registers have the following id bit patterns:: > derived from the register encoding for CNTV_CVAL_EL0. As this is > API, it must remain this way. > > +.. warning:: > + > + The value of KVM_REG_ARM_TIMER_OFFSET is defined as an offset from > + the guest's view of the physical counter-timer. > + > + Userspace should use either KVM_REG_ARM_TIMER_OFFSET or > + KVM_REG_ARM_TIMER_CVAL to pause and resume a guest's virtual > + counter-timer. Mixed use of these registers could result in an > + unpredictable guest counter value. > + > arm64 firmware pseudo-registers have the following bit pattern:: > > 0x6030 0000 0014 > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index b3edde68bc3e..949a31bc10f0 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -255,6 +255,7 @@ struct kvm_arm_copy_mte_tags { > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) > +#define KVM_REG_ARM_TIMER_OFFSET ARM64_SYS_REG(3, 4, 14, 0, 3) > > /* KVM-as-firmware specific pseudo-registers */ > #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 4c2b763a8849..a8815b09da3e 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -868,6 +868,10 @@ int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) > timer = vcpu_vtimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CVAL, value); > break; > + case KVM_REG_ARM_TIMER_OFFSET: > + timer = vcpu_vtimer(vcpu); > + update_vtimer_cntvoff(vcpu, value); > + break; > case KVM_REG_ARM_PTIMER_CTL: > timer = vcpu_ptimer(vcpu); > kvm_arm_timer_write(vcpu, timer, TIMER_REG_CTL, value); > @@ -912,6 +916,9 @@ u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) > case KVM_REG_ARM_TIMER_CVAL: > return kvm_arm_timer_read(vcpu, > vcpu_vtimer(vcpu), TIMER_REG_CVAL); > + case KVM_REG_ARM_TIMER_OFFSET: > + return kvm_arm_timer_read(vcpu, > + vcpu_vtimer(vcpu), TIMER_REG_OFFSET); > case KVM_REG_ARM_PTIMER_CTL: > return kvm_arm_timer_read(vcpu, > vcpu_ptimer(vcpu), TIMER_REG_CTL); > @@ -949,6 +956,10 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > val = kvm_phys_timer_read() - timer_get_offset(timer); > break; > > + case TIMER_REG_OFFSET: > + val = timer_get_offset(timer); > + break; > + > default: > BUG(); > } > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 1dfb83578277..17fc06e2b422 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -591,7 +591,7 @@ static unsigned long num_core_regs(const struct kvm_vcpu *vcpu) > * ARM64 versions of the TIMER registers, always available on arm64 > */ > > -#define NUM_TIMER_REGS 3 > +#define NUM_TIMER_REGS 4 > > static bool is_timer_reg(u64 index) > { > @@ -599,6 +599,7 @@ static bool is_timer_reg(u64 index) > case KVM_REG_ARM_TIMER_CTL: > case KVM_REG_ARM_TIMER_CNT: > case KVM_REG_ARM_TIMER_CVAL: > + case KVM_REG_ARM_TIMER_OFFSET: > return true; > } > return false; > @@ -614,6 +615,9 @@ static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) > uindices++; > if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices)) > return -EFAULT; > + uindices++; > + if (put_user(KVM_REG_ARM_TIMER_OFFSET, uindices)) > + return -EFAULT; > > return 0; > } > diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h > index 9d65d4a29f81..615f9314f6a5 100644 > --- a/include/kvm/arm_arch_timer.h > +++ b/include/kvm/arm_arch_timer.h > @@ -21,6 +21,7 @@ enum kvm_arch_timer_regs { > TIMER_REG_CVAL, > TIMER_REG_TVAL, > TIMER_REG_CTL, > + TIMER_REG_OFFSET, > }; > > struct arch_timer_context { > -- > 2.32.0.605.g8dce9f2422-goog > Reviewed-by: Andrew Jones _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel