From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v5 1/9] drm/i915/dg2: Add support for new DG2-G11 revid 0x5
Date: Thu, 5 Aug 2021 09:48:36 -0700 [thread overview]
Message-ID: <20210805164836.eruf27ryzmont2zf@ldmartin-desk2> (raw)
In-Reply-To: <20210805163647.801064-2-matthew.d.roper@intel.com>
On Thu, Aug 05, 2021 at 09:36:39AM -0700, Matt Roper wrote:
>The bspec has been updated with a new revision 0x5 that translates to B1
>GT stepping and C0 display stepping.
>
>Bspec: 44477
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_step.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
>index b5fb961e1b62..6cf967631395 100644
>--- a/drivers/gpu/drm/i915/intel_step.c
>+++ b/drivers/gpu/drm/i915/intel_step.c
>@@ -118,6 +118,7 @@ static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
> static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
> [0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
> [0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
>+ [0x5] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
> };
>
> void intel_step_init(struct drm_i915_private *i915)
>--
>2.25.4
>
next prev parent reply other threads:[~2021-08-05 16:48 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 16:36 [Intel-gfx] [PATCH v5 0/9] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 1/9] drm/i915/dg2: Add support for new DG2-G11 revid 0x5 Matt Roper
2021-08-05 16:48 ` Lucas De Marchi [this message]
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 2/9] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-08-11 0:18 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 3/9] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 4/9] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-08-05 17:26 ` Lucas De Marchi
2021-08-06 17:29 ` [Intel-gfx] [PATCH v5.1 " Matt Roper
2021-08-11 0:17 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 5/9] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-08-12 22:49 ` Souza, Jose
2021-08-12 23:14 ` Lucas De Marchi
2021-08-12 23:18 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 6/9] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-08-25 0:03 ` Yokoyama, Caz
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 8/9] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-08-18 21:56 ` Srivatsa, Anusha
2021-08-23 9:26 ` Tvrtko Ursulin
2021-08-24 4:06 ` Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 9/9] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-08-10 21:51 ` Souza, Jose
2021-08-05 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev9) Patchwork
2021-08-05 17:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-05 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 7:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-06 18:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev10) Patchwork
2021-08-06 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-06 18:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 23:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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