From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38590C4338F for ; Thu, 5 Aug 2021 17:59:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F1DAE61078 for ; Thu, 5 Aug 2021 17:59:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F1DAE61078 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:44030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBhed-000541-3J for qemu-devel@archiver.kernel.org; Thu, 05 Aug 2021 13:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc4-0007e9-4i; Thu, 05 Aug 2021 13:57:00 -0400 Received: from exmail.andestech.com ([60.248.187.195]:13049 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhbz-0007p6-VK; Thu, 05 Aug 2021 13:56:59 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 175HuPF5055921; Fri, 6 Aug 2021 01:56:25 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 6 Aug 2021 01:56:26 +0800 From: Ruinland Chuan-Tzu Tsai To: , Subject: [RFC PATCH v4 0/4] Add basic support for custom CSR Date: Fri, 6 Aug 2021 01:56:22 +0800 Message-ID: <20210805175626.11573-1-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HuPF5055921 Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, wangjunqiang@iscas.ac.cn, bin.meng@windriver.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Ruinland ChuanTzu Tsai Dear all, In this patch, the implementation of custom CSR handling logic is introduced. If --enable-riscv-custom is set during configuration, custom CSR logic will be turned on. During CPU model initialization, setup_custom_csr() is invoked to register vendor-provided custom CSR opsets into a hash table. When accessing a CSR, in riscv_csrrw(), is_custom_csr() will be called to check whether the encountering csrno is a custom CSR. If that's a custom one, a struct riscv_csr_operations will be returned and such CSR will be served accordingly. The performance slowdown could be easily tested with a simple program running on linux-user mode. /* test_csr.c */ #include #include #include int main (int ac, char *av[]) { struct timeval start; struct timeval end; gettimeofday(&start,NULL); unsigned int loop_n = 999999 ; unsigned char i; unsigned char o; do { for(i=0; i<32; i++) { #if defined(FCSR) __asm__("csrw fcsr, %0;"::"r"(i)); __asm__("csrr %0, fcsr;":"=r"(o)); #elif defined(UITB) __asm__("csrw 0x800, %0;"::"r"(i)); __asm__("csrr %0, 0x800;":"=r"(o)); #endif } --loop_n; } while (loop_n > 0); gettimeofday(&end,NULL); unsigned long diff = 1000000 * (end.tv_sec-start.tv_sec)+end.tv_usec-start.tv_usec; printf("%f\n", (double)(diff)/1000000); return 0; } $ riscv64-linux-gnu-gcc -static -DUITB ./test_csr.c -o ./u $ riscv64-linux-gnu-gcc -static -DFCSR ./test_csr.c -o ./f For a custom CSR, uitb, being accessed on andes-ax25 : $ ./build/qemu-riscv64 -cpu andes-ax25 ./u 4.283091 For a stock CSR, fcsr, being accessed on andes-ax25: $ ./build/qemu-riscv64 ./f 3.875519 For a custom CSR being accessed on stock rv64: $ ./build/qemu-riscv64 -cpu rv64 ./u Illegal instruction (core dumped) # This is expected to fail. Currently, the statics on my hands shows that : When the custom CSR handling mechanism is activated, we will suffer a 17% slow- down on stock CSRs and the penalty of accessing to a custom CSR will be another 7% more. Cordially yours, Ruinland ChuanTzu Tsai Changes from v3 : * Adding options in configure and meson files to turn on/off custom CSR logic. * Adding unlikely() to check if custom_csr_map is set. * Moving any32 and any out of !(CONFIG_USER_ONLY) for enabling linux-user mode. * Fix comment style, add missing license boilerplate. Ruinalnd ChuanTzu Tsai (4): Adding basic custom/vendor CSR handling mechanism Adding Andes AX25 and A25 CPU model Enable custom CSR logic for Andes AX25 and A25 Add options to config/meson files for custom CSR configure | 6 ++ meson.build | 2 + meson_options.txt | 2 + target/riscv/andes_cpu_bits.h | 124 +++++++++++++++++++++++++ target/riscv/cpu.c | 51 +++++++++++ target/riscv/cpu.h | 33 ++++++- target/riscv/cpu_bits.h | 4 + target/riscv/csr.c | 83 ++++++++++++++--- target/riscv/csr_andes.inc.c | 160 +++++++++++++++++++++++++++++++++ target/riscv/custom_cpu_bits.h | 12 +++ 10 files changed, 462 insertions(+), 15 deletions(-) create mode 100644 target/riscv/andes_cpu_bits.h create mode 100644 target/riscv/csr_andes.inc.c create mode 100644 target/riscv/custom_cpu_bits.h -- 2.32.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mBhc5-0007gP-IH for mharc-qemu-riscv@gnu.org; Thu, 05 Aug 2021 13:57:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc4-0007e9-4i; Thu, 05 Aug 2021 13:57:00 -0400 Received: from exmail.andestech.com ([60.248.187.195]:13049 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhbz-0007p6-VK; Thu, 05 Aug 2021 13:56:59 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 175HuPF5055921; Fri, 6 Aug 2021 01:56:25 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 6 Aug 2021 01:56:26 +0800 From: Ruinland Chuan-Tzu Tsai To: , CC: , , Subject: [RFC PATCH v4 0/4] Add basic support for custom CSR Date: Fri, 6 Aug 2021 01:56:22 +0800 Message-ID: <20210805175626.11573-1-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HuPF5055921 Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Aug 2021 17:57:00 -0000 From: Ruinland ChuanTzu Tsai Dear all, In this patch, the implementation of custom CSR handling logic is introduced. If --enable-riscv-custom is set during configuration, custom CSR logic will be turned on. During CPU model initialization, setup_custom_csr() is invoked to register vendor-provided custom CSR opsets into a hash table. When accessing a CSR, in riscv_csrrw(), is_custom_csr() will be called to check whether the encountering csrno is a custom CSR. If that's a custom one, a struct riscv_csr_operations will be returned and such CSR will be served accordingly. The performance slowdown could be easily tested with a simple program running on linux-user mode. /* test_csr.c */ #include #include #include int main (int ac, char *av[]) { struct timeval start; struct timeval end; gettimeofday(&start,NULL); unsigned int loop_n = 999999 ; unsigned char i; unsigned char o; do { for(i=0; i<32; i++) { #if defined(FCSR) __asm__("csrw fcsr, %0;"::"r"(i)); __asm__("csrr %0, fcsr;":"=r"(o)); #elif defined(UITB) __asm__("csrw 0x800, %0;"::"r"(i)); __asm__("csrr %0, 0x800;":"=r"(o)); #endif } --loop_n; } while (loop_n > 0); gettimeofday(&end,NULL); unsigned long diff = 1000000 * (end.tv_sec-start.tv_sec)+end.tv_usec-start.tv_usec; printf("%f\n", (double)(diff)/1000000); return 0; } $ riscv64-linux-gnu-gcc -static -DUITB ./test_csr.c -o ./u $ riscv64-linux-gnu-gcc -static -DFCSR ./test_csr.c -o ./f For a custom CSR, uitb, being accessed on andes-ax25 : $ ./build/qemu-riscv64 -cpu andes-ax25 ./u 4.283091 For a stock CSR, fcsr, being accessed on andes-ax25: $ ./build/qemu-riscv64 ./f 3.875519 For a custom CSR being accessed on stock rv64: $ ./build/qemu-riscv64 -cpu rv64 ./u Illegal instruction (core dumped) # This is expected to fail. Currently, the statics on my hands shows that : When the custom CSR handling mechanism is activated, we will suffer a 17% slow- down on stock CSRs and the penalty of accessing to a custom CSR will be another 7% more. Cordially yours, Ruinland ChuanTzu Tsai Changes from v3 : * Adding options in configure and meson files to turn on/off custom CSR logic. * Adding unlikely() to check if custom_csr_map is set. * Moving any32 and any out of !(CONFIG_USER_ONLY) for enabling linux-user mode. * Fix comment style, add missing license boilerplate. Ruinalnd ChuanTzu Tsai (4): Adding basic custom/vendor CSR handling mechanism Adding Andes AX25 and A25 CPU model Enable custom CSR logic for Andes AX25 and A25 Add options to config/meson files for custom CSR configure | 6 ++ meson.build | 2 + meson_options.txt | 2 + target/riscv/andes_cpu_bits.h | 124 +++++++++++++++++++++++++ target/riscv/cpu.c | 51 +++++++++++ target/riscv/cpu.h | 33 ++++++- target/riscv/cpu_bits.h | 4 + target/riscv/csr.c | 83 ++++++++++++++--- target/riscv/csr_andes.inc.c | 160 +++++++++++++++++++++++++++++++++ target/riscv/custom_cpu_bits.h | 12 +++ 10 files changed, 462 insertions(+), 15 deletions(-) create mode 100644 target/riscv/andes_cpu_bits.h create mode 100644 target/riscv/csr_andes.inc.c create mode 100644 target/riscv/custom_cpu_bits.h -- 2.32.0