All of lore.kernel.org
 help / color / mirror / Atom feed
From: Will Deacon <will@kernel.org>
To: Frank Li <frank.li@nxp.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Zhi Li <lznuaa@gmail.com>, Shenwei Wang <shenwei.wang@nxp.com>,
	Han Xu <han.xu@nxp.com>, Nitin Garg <nitin.garg@nxp.com>,
	Jason Liu <jason.hui.liu@nxp.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers in default I/O accessors
Date: Mon, 9 Aug 2021 16:26:34 +0100	[thread overview]
Message-ID: <20210809152634.GA1589@willie-the-truck> (raw)
In-Reply-To: <AS8PR04MB85001637B4DAE19BB51FA54588F69@AS8PR04MB8500.eurprd04.prod.outlook.com>

On Mon, Aug 09, 2021 at 02:46:55PM +0000, Frank Li wrote:
> 
> 
> > -----Original Message-----
> > From: Will Deacon <will@kernel.org>
> > Sent: Monday, August 9, 2021 8:51 AM
> > To: Frank Li <frank.li@nxp.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>; Zhi Li <lznuaa@gmail.com>;
> > Shenwei Wang <shenwei.wang@nxp.com>; Han Xu <han.xu@nxp.com>; Nitin Garg
> > <nitin.garg@nxp.com>; Jason Liu <jason.hui.liu@nxp.com>; linux-arm-
> > kernel@lists.infradead.org
> > Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers
> > in default I/O accessors
> > 
> > Caution: EXT Email
> > 
> > On Thu, Jul 22, 2021 at 07:14:19PM +0000, Frank Li wrote:
> > > > > On Wed, Jun 23, 2021 at 03:48:10PM +0000, Frank Li wrote:
> > > > > > > I think you had a support case open with Arm [1] which I'm not
> > able
> > > > to
> > > > > > > access -- please can you ask them about the two examples above?
> > > > > >
> > > > > > Still not get feedback from ARM.
> > > > >
> > > > > Just wondering if you were able to solve this without the need to
> > change
> > > > > Linux?
> > > >
> > > > Sorry for late reply
> > > >
> > > > For CCI-500 and 550, ARM removed support for barrier transactions but
> > CCI-
> > > > 400 supports barrier transactions. With CCI-400 it is a valid
> > configuration
> > > > to have SYSBARDISABLE LOW in Cortex-A processors. This change in Linux
> > > > kernel is assuming that the SYSBARDISABLE is set to HIGH hence its not
> > > > correct change for all products having various versions of ARM CCI IP.
> > > >
> > > > Frank Li
> > >
> > > Deacon:
> > >
> > >       Did you plan fix this problem by changing dma_wmb()?
> > 
> > No. As far as I understand this problem, you're driving SYSBARDISABLE
> > 'low' yet you have your own bus fabric downstream of the CCI which doesn't
> > respect barrier transactions. Even if we bodge dma_wmb(), store-release to
> > non-cacheable memory cannot be made to work on your system as you're
> > effectively putting some of your non-coherent DMA devices into a separate
> > outer-shareable domain from the CPUs.
> 
> Does it means the Linux expect all DMA devices in outer-shareable domain instead
> of system shared domain?  

I don't think we've ever documented that and, to be honest, the
outer-shareable domain stuff in the architecture is pretty academic.

However, I think it's fair to say that we do want the acquire/release
instructions to work for non-cacheable buffers when communicating with
non-coherent devices. I _think_ that implies that such devices need to
be in the same outer-shareable domain as the CPUs, although the
architecture isn't really clear here. I can try to find out.

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-08-09 15:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <AS8PR04MB850004639EE6CE9432BBF13E880F9@AS8PR04MB8500.eurprd04.prod.outlook.com>
     [not found] ` <CAHrpEqRsp2_bt=p5JgS5F-2F_LCwgT+VX7mSENzpEYTQiW1tjg@mail.gmail.com>
2021-06-17  9:27   ` Catalin Marinas
2021-06-17 17:25     ` Will Deacon
2021-06-17 17:41       ` Will Deacon
2021-06-17 20:11         ` [EXT] " Frank Li
2021-06-17 21:40           ` Will Deacon
2021-06-17 22:13             ` Frank Li
2021-06-18 14:56             ` Nitin Garg
2021-06-21 16:11             ` Frank Li
2021-06-21 16:26               ` Will Deacon
2021-06-21 16:59                 ` Will Deacon
2021-06-21 17:56                   ` Frank Li
2021-06-21 18:13                     ` Will Deacon
2021-06-21 21:32                       ` Frank Li
2021-06-22  9:11                         ` Will Deacon
2021-06-23 15:48                           ` Frank Li
2021-07-06 17:11                             ` Will Deacon
2021-07-15 15:53                               ` Frank Li
2021-07-22 19:14                                 ` Frank Li
2021-08-09 13:50                                   ` Will Deacon
2021-08-09 14:46                                     ` Frank Li
2021-08-09 15:26                                       ` Will Deacon [this message]
2021-08-10 18:50                                         ` Frank Li

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210809152634.GA1589@willie-the-truck \
    --to=will@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=frank.li@nxp.com \
    --cc=han.xu@nxp.com \
    --cc=jason.hui.liu@nxp.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=lznuaa@gmail.com \
    --cc=nitin.garg@nxp.com \
    --cc=shenwei.wang@nxp.com \
    --subject='Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers in default I/O accessors' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.