From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5336BC4338F for ; Mon, 9 Aug 2021 15:46:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D87F6023B for ; Mon, 9 Aug 2021 15:46:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0D87F6023B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=F254QTrwqZP25yYDkM1AFk27tsarzSLgKJLZhkANdL4=; b=iGhaa/jkaWw38y BYMIw+05R7wO/EKG19PzVCr+8Ku4xF6qgh/8uRJ8U7PZU6iCa657U9K0DHau6k1GaLiDr2siskB61 6vcNr75pQ5gtkxXnHabzAtoGMHNQW0SrOMXFTNAra0BWSmK7MSP9Q7RQlWZ7oxSX5joeDPw2dirrt n5K5FhouPFwfPmxc+AtotILFZCzYFJGW+grWS4YfrDbYnhEzQytadsXhCi3KyQVqUlA/9IKJrYg44 FnX4ijZ5kXCJ4H3TJx7OdCwFFcjyFrqEVtsSxUEVK4RuVYnIMAjtgsic9vxVhBI+BEiNKZP0Lx9CF 2HWvqudZyalxElxEq3AQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD7RL-001FBl-8w; Mon, 09 Aug 2021 15:43:48 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD7Al-0018XN-Qg for linux-arm-kernel@lists.infradead.org; Mon, 09 Aug 2021 15:26:41 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id F3B3A60F8F; Mon, 9 Aug 2021 15:26:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1628522799; bh=Q5+Bmh4KqnnRkhGzDue1/gNrvSiJt7SxDmz0Q/r78FQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=eyqGk660RxBbtmMQzUzSd4eVsDxo5LVZwTZBO96B7Mx5ajB2wDJv3nPYLUa4Xg4YE 0TL1qTDXJE41w7VeGOC3m45V9riOxewhli6S5F7PY0wQAbpgc6/S/E+4+6mrLC+UmB aVhGDA+vCuN1UXE2Fo2rMROLwhW+pAJYODC8Emz4cmBfXNuMYH9IZi0Rz3mDJAeZ8/ wKRX+ZCZTbzFi4PQhB0AizQP0958GmjXK/e25y1+Bj52zJjE00wrW7qMwqfN2zOzkz rMWwI49zBWrMspCacFmLlV4U2ViDgCBU0vhKxB2a1a0CuZ3GuNfXv+fQ8Mq2rGIbcu GiLqMZWaPwrnA== Date: Mon, 9 Aug 2021 16:26:34 +0100 From: Will Deacon To: Frank Li Cc: Catalin Marinas , Zhi Li , Shenwei Wang , Han Xu , Nitin Garg , Jason Liu , "linux-arm-kernel@lists.infradead.org" Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers in default I/O accessors Message-ID: <20210809152634.GA1589@willie-the-truck> References: <20210621181326.GD29713@willie-the-truck> <20210622091140.GA30677@willie-the-truck> <20210706171106.GE20750@willie-the-truck> <20210809135041.GC1207@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210809_082639_944541_6278EE91 X-CRM114-Status: GOOD ( 30.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 09, 2021 at 02:46:55PM +0000, Frank Li wrote: > > > > -----Original Message----- > > From: Will Deacon > > Sent: Monday, August 9, 2021 8:51 AM > > To: Frank Li > > Cc: Catalin Marinas ; Zhi Li ; > > Shenwei Wang ; Han Xu ; Nitin Garg > > ; Jason Liu ; linux-arm- > > kernel@lists.infradead.org > > Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers > > in default I/O accessors > > > > Caution: EXT Email > > > > On Thu, Jul 22, 2021 at 07:14:19PM +0000, Frank Li wrote: > > > > > On Wed, Jun 23, 2021 at 03:48:10PM +0000, Frank Li wrote: > > > > > > > I think you had a support case open with Arm [1] which I'm not > > able > > > > to > > > > > > > access -- please can you ask them about the two examples above? > > > > > > > > > > > > Still not get feedback from ARM. > > > > > > > > > > Just wondering if you were able to solve this without the need to > > change > > > > > Linux? > > > > > > > > Sorry for late reply > > > > > > > > For CCI-500 and 550, ARM removed support for barrier transactions but > > CCI- > > > > 400 supports barrier transactions. With CCI-400 it is a valid > > configuration > > > > to have SYSBARDISABLE LOW in Cortex-A processors. This change in Linux > > > > kernel is assuming that the SYSBARDISABLE is set to HIGH hence its not > > > > correct change for all products having various versions of ARM CCI IP. > > > > > > > > Frank Li > > > > > > Deacon: > > > > > > Did you plan fix this problem by changing dma_wmb()? > > > > No. As far as I understand this problem, you're driving SYSBARDISABLE > > 'low' yet you have your own bus fabric downstream of the CCI which doesn't > > respect barrier transactions. Even if we bodge dma_wmb(), store-release to > > non-cacheable memory cannot be made to work on your system as you're > > effectively putting some of your non-coherent DMA devices into a separate > > outer-shareable domain from the CPUs. > > Does it means the Linux expect all DMA devices in outer-shareable domain instead > of system shared domain? I don't think we've ever documented that and, to be honest, the outer-shareable domain stuff in the architecture is pretty academic. However, I think it's fair to say that we do want the acquire/release instructions to work for non-cacheable buffers when communicating with non-coherent devices. I _think_ that implies that such devices need to be in the same outer-shareable domain as the CPUs, although the architecture isn't really clear here. I can try to find out. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel