From: Dan Carpenter <dan.carpenter@oracle.com>
To: p.pisati@gmail.com
Cc: linux-fpga@vger.kernel.org
Subject: [bug report] fpga: lattice machxo2: Add Lattice MachXO2 support
Date: Tue, 10 Aug 2021 11:52:19 +0300 [thread overview]
Message-ID: <20210810085219.GB23998@kili> (raw)
Hello Paolo Pisati,
The patch 88fb3a002330: "fpga: lattice machxo2: Add Lattice MachXO2
support" from Apr 16, 2018, leads to the following static checker
warning:
drivers/fpga/machxo2-spi.c:229 machxo2_write_init()
warn: missing error code 'ret'
drivers/fpga/machxo2-spi.c:316 machxo2_write_complete()
warn: missing error code 'ret'
drivers/fpga/machxo2-spi.c
187 static int machxo2_write_init(struct fpga_manager *mgr,
188 struct fpga_image_info *info,
189 const char *buf, size_t count)
190 {
191 struct spi_device *spi = mgr->priv;
192 struct spi_message msg;
193 struct spi_transfer tx[3];
194 static const u8 enable[] = ISC_ENABLE;
195 static const u8 erase[] = ISC_ERASE;
196 static const u8 initaddr[] = LSC_INITADDRESS;
197 unsigned long status;
198 int ret;
199
200 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
201 dev_err(&mgr->dev,
202 "Partial reconfiguration is not supported\n");
203 return -ENOTSUPP;
204 }
205
206 get_status(spi, &status);
207 dump_status_reg(&status);
208 memset(tx, 0, sizeof(tx));
209 spi_message_init(&msg);
210 tx[0].tx_buf = &enable;
211 tx[0].len = sizeof(enable);
212 tx[0].delay.value = MACHXO2_LOW_DELAY_USEC;
213 tx[0].delay.unit = SPI_DELAY_UNIT_USECS;
214 spi_message_add_tail(&tx[0], &msg);
215
216 tx[1].tx_buf = &erase;
217 tx[1].len = sizeof(erase);
218 spi_message_add_tail(&tx[1], &msg);
219 ret = spi_sync(spi, &msg);
220 if (ret)
221 goto fail;
222
223 ret = wait_until_not_busy(spi);
224 if (ret)
225 goto fail;
226
227 get_status(spi, &status);
228 if (test_bit(FAIL, &status))
--> 229 goto fail;
Set an error code here? The other warning is similar.
230 dump_status_reg(&status);
231
232 spi_message_init(&msg);
233 tx[2].tx_buf = &initaddr;
234 tx[2].len = sizeof(initaddr);
235 spi_message_add_tail(&tx[2], &msg);
236 ret = spi_sync(spi, &msg);
237 if (ret)
238 goto fail;
239
240 get_status(spi, &status);
241 dump_status_reg(&status);
242
243 return 0;
244 fail:
245 dev_err(&mgr->dev, "Error during FPGA init.\n");
246
247 return ret;
248 }
regards,
dan carpenter
reply other threads:[~2021-08-10 8:52 UTC|newest]
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