From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6904EC4338F for ; Fri, 13 Aug 2021 18:06:47 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DC44610CC for ; Fri, 13 Aug 2021 18:06:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6DC44610CC Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CD8E28201E; Fri, 13 Aug 2021 20:06:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="rvAjp882"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5B385829C6; Fri, 13 Aug 2021 20:06:41 +0200 (CEST) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5E4CF80EEA for ; Fri, 13 Aug 2021 20:06:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 17DI6W7b114112; Fri, 13 Aug 2021 13:06:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1628877992; bh=UgK+V57ECr6LjVbnGRJ/TcjS2KtJBmbthinvQGTmVVM=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=rvAjp882YrdPSoLEi6lkGhANjWgDC/G3RlSALcqnXHbeOGfcJugRRi7Db4C6asz/9 M/THGRkbcDz8+NLuHpEsy/e5zhOS3bFE9BlAG1ncTTHlPnmPoDJowgDoXR4k1Fsn7X kWPH3+w5DeWgg7fMVxWM9NwD3KQp4vij5SRSHE4Q= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 17DI6W0U047572 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 13 Aug 2021 13:06:32 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 13 Aug 2021 13:06:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 13 Aug 2021 13:06:31 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 17DI6V9R074811; Fri, 13 Aug 2021 13:06:31 -0500 Date: Fri, 13 Aug 2021 23:36:30 +0530 From: Pratyush Yadav To: JaimeLiao CC: , , , , , Subject: Re: [PATCH 1/4] mtd: spi-nor: macronix: add support for Macronix octaflash Message-ID: <20210813180628.muz3o7y3q635lftx@ti.com> References: <20210813072552.21772-1-jaimeliao.tw@gmail.com> <20210813072552.21772-2-jaimeliao.tw@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20210813072552.21772-2-jaimeliao.tw@gmail.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 13/08/21 03:25PM, JaimeLiao wrote: > Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding > Macronix flash in Octal DTR mode. > Enable Octal DTR mode with 20 dummy cycles to allow running at the > maximum supported frequency. Please include a link to the flash datasheet so the reviewers can properly review your patch. > > Signed-off-by: JaimeLiao > --- > drivers/mtd/spi/spi-nor-core.c | 75 ++++++++++++++++++++++++++++++++++ > include/linux/mtd/spi-nor.h | 13 +++++- > 2 files changed, 86 insertions(+), 2 deletions(-) > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index d5d905fa5a..6b195b1fd3 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c > @@ -3489,6 +3489,77 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { > }; > #endif /* CONFIG_SPI_FLASH_MT35XU */ > > +#ifdef CONFIG_SPI_FLASH_MACRONIX > +/** > + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2. > + * @nor: pointer to a 'struct spi_nor' > + * > + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2. Nitpick: Why the blank line here? > + * > + * bit 2 of Configuration Register 2 is the DOPI bit for Macronix like OPI memories. Nitpick: Capitalize the 'b'. > + * > + * Return: 0 on success, -errno otherwise. > + */ > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) > +{ > + struct spi_mem_op op; > + int ret; > + u8 buf; > + > + write_enable(nor); Need to check the return code here. > + > + buf = SPINOR_REG_MXIC_DC_20; > + op = (struct spi_mem_op) > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), > + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), > + SPI_MEM_OP_NO_DUMMY, > + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); > + > + ret = spi_mem_exec_op(nor->spi, &op); > + if (ret) > + return ret; > + > + ret = spi_nor_wait_till_ready(nor); > + if (ret) > + return ret; > + > + nor->read_dummy = MXIC_MAX_DC; > + write_enable(nor); > + > + buf = SPINOR_REG_MXIC_OPI_DTR_EN; > + op = (struct spi_mem_op) > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), > + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1), > + SPI_MEM_OP_NO_DUMMY, > + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); > + > + ret = spi_mem_exec_op(nor->spi, &op); > + if (ret) { > + dev_err(nor->dev, "Failed to enable octal DTR mode\n"); > + return ret; > + } > + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; > + > + return 0; > +} > + > +static void macronix_default_init(struct spi_nor *nor) > +{ > + nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; > +} > + > +static void macronix_post_sfdp_fixup(struct spi_nor *nor, > + struct spi_nor_flash_parameter *params) > +{ > + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; This does not seem right. You would mark every Macronix flash Octal DTR capable which is clearly not true. > +} > + > +static struct spi_nor_fixups macronix_fixups = { > + .default_init = macronix_default_init, > + .post_sfdp = macronix_post_sfdp_fixup, > +}; > +#endif /* CONFIG_SPI_FLASH_MACRONIX */ > + > /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed > * @nor: pointer to a 'struct spi_nor' > * > @@ -3655,6 +3726,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) > if (!strcmp(nor->info->name, "mt35xu512aba")) > nor->fixups = &mt35xu512aba_fixups; > #endif > + > +#ifdef CONFIG_SPI_FLASH_MACRONIX > + nor->fixups = ¯onix_fixups; > +#endif > } > > int spi_nor_scan(struct spi_nor *nor) > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 7ddc4ba2bf..2ad579f66d 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -116,8 +116,17 @@ > #define XSR_RDY BIT(7) /* Ready */ > > /* Used for Macronix and Winbond flashes. */ > -#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ > -#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ > +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ > +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ > +#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ > +#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ > +#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ > +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ > +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ > +#define SPINOR_REG_MXIC_OPI_DTR_DIS 0x1 /* Disable Octal DTR */ > +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ > +#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ > +#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */ > > /* Used for Spansion flashes only. */ > #define SPINOR_OP_BRWR 0x17 /* Bank register write */ > -- > 2.17.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.