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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, drmdevel@freedesktop.org
Cc: <daniel.vetter@ffwll.ch>
Subject: [Intel-gfx] [PATCH 15/21] drm/i915/guc: Release submit fence from an IRQ
Date: Sun, 15 Aug 2021 13:15:53 -0700	[thread overview]
Message-ID: <20210815201559.1150-16-matthew.brost@intel.com> (raw)
In-Reply-To: <20210815201559.1150-1-matthew.brost@intel.com>

A subsequent patch will flip the locking hierarchy from
ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
ce->guc_state.lock. As such we need to release the submit fence for a
request from an IRQ to break a lock inversion - i.e. the fence must be
release went holding ce->guc_state.lock and the releasing of the can
acquire sched_engine->lock.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++++++++++++++-
 drivers/gpu/drm/i915/i915_request.h               |  5 +++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 54c0914b21f3..b09be9b88cb3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2016,6 +2016,14 @@ static const struct intel_context_ops guc_context_ops = {
 	.create_virtual = guc_create_virtual,
 };
 
+static void submit_work_cb(struct irq_work *wrk)
+{
+	struct i915_request *rq = container_of(wrk, typeof(*rq), submit_work);
+
+	might_lock(&rq->engine->sched_engine->lock);
+	i915_sw_fence_complete(&rq->submit);
+}
+
 static void __guc_signal_context_fence(struct intel_context *ce)
 {
 	struct i915_request *rq;
@@ -2025,8 +2033,12 @@ static void __guc_signal_context_fence(struct intel_context *ce)
 	if (!list_empty(&ce->guc_state.fences))
 		trace_intel_context_fence_release(ce);
 
+	/*
+	 * Use an IRQ to ensure locking order of sched_engine->lock ->
+	 * ce->guc_state.lock is preserved.
+	 */
 	list_for_each_entry(rq, &ce->guc_state.fences, guc_fence_link)
-		i915_sw_fence_complete(&rq->submit);
+		irq_work_queue(&rq->submit_work);
 
 	INIT_LIST_HEAD(&ce->guc_state.fences);
 }
@@ -2136,6 +2148,7 @@ static int guc_request_alloc(struct i915_request *rq)
 	spin_lock_irqsave(&ce->guc_state.lock, flags);
 	if (context_wait_for_deregister_to_register(ce) ||
 	    context_pending_disable(ce)) {
+		init_irq_work(&rq->submit_work, submit_work_cb);
 		i915_sw_fence_await(&rq->submit);
 
 		list_add_tail(&rq->guc_fence_link, &ce->guc_state.fences);
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 1bc1349ba3c2..d818cfbfc41d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -218,6 +218,11 @@ struct i915_request {
 	};
 	struct llist_head execute_cb;
 	struct i915_sw_fence semaphore;
+	/**
+	 * @submit_work: complete submit fence from an IRQ if needed for
+	 * locking hierarchy reasons.
+	 */
+	struct irq_work submit_work;
 
 	/*
 	 * A list of everyone we wait upon, and everyone who waits upon us.
-- 
2.32.0


  parent reply	other threads:[~2021-08-15 20:21 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-15 20:15 [Intel-gfx] [PATCH 00/21] Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 01/21] drm/i915/guc: Fix blocked context accounting Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 02/21] drm/i915/guc: outstanding G2H accounting Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 03/21] drm/i915/guc: Unwind context requests in reverse order Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 04/21] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 05/21] drm/i915/guc: Workaround reset G2H is received after schedule done G2H Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 06/21] drm/i915/selftests: Add a cancel request selftest that triggers a reset Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 07/21] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 08/21] drm/i915/selftests: Fix memory corruption in live_lrc_isolation Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 09/21] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 10/21] drm/i915/guc: Take context ref when cancelling request Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 11/21] drm/i915/guc: Don't touch guc_state.sched_state without a lock Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 12/21] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 13/21] drm/i915: Allocate error capture in atomic context Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 14/21] drm/i915/guc: Flush G2H work queue during reset Matthew Brost
2021-08-15 20:15 ` Matthew Brost [this message]
2021-08-15 20:15 ` [Intel-gfx] [PATCH 16/21] drm/i915/guc: Move guc_blocked fence to struct guc_state Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 17/21] drm/i915/guc: Rework and simplify locking Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 18/21] drm/i915/guc: Proper xarray usage for contexts_lookup Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 19/21] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 20/21] drm/i915/guc: Move GuC priority fields in context under guc_active Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 21/21] drm/i915/guc: Add GuC kernel doc Matthew Brost
2021-08-15 20:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC Patchwork
2021-08-15 20:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-15 21:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-08-15 21:54   ` Matthew Brost

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