From: Dmitry Osipenko <digetx@gmail.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Jonathan Hunter" <jonathanh@nvidia.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Viresh Kumar" <vireshk@kernel.org>, "Stephen Boyd" <sboyd@kernel.org>, "Peter De Schrijver" <pdeschrijver@nvidia.com>, "Mikko Perttunen" <mperttunen@nvidia.com>, "Peter Chen" <peter.chen@kernel.org>, "Mark Brown" <broonie@kernel.org>, "Lee Jones" <lee.jones@linaro.org>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Nishanth Menon" <nm@ti.com>, "Vignesh Raghavendra" <vigneshr@ti.com>, "Richard Weinberger" <richard@nod.at>, "Miquel Raynal" <miquel.raynal@bootlin.com>, "Lucas Stach" <dev@lynxeye.de>, "Stefan Agner" <stefan@agner.ch>, "Adrian Hunter" <adrian.hunter@intel.com>, "Mauro Carvalho Chehab" <mchehab@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Michael Turquette" <mturquette@baylibre.com> Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 12/34] drm/tegra: dc: Support OPP and SoC core voltage scaling Date: Tue, 17 Aug 2021 04:27:32 +0300 [thread overview] Message-ID: <20210817012754.8710-13-digetx@gmail.com> (raw) In-Reply-To: <20210817012754.8710-1-digetx@gmail.com> Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 74 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dc.h | 2 ++ 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 16c7aabb94d3..435dd8139c6e 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -11,9 +11,12 @@ #include <linux/interconnect.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h> +#include <soc/tegra/common.h> #include <soc/tegra/pmc.h> #include <drm/drm_atomic.h> @@ -1762,6 +1765,47 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, return 0; } +static void tegra_dc_update_voltage_state(struct tegra_dc *dc, + struct tegra_dc_state *state) +{ + unsigned long rate, pstate; + struct dev_pm_opp *opp; + int err; + + if (!dc->has_opp_table) + return; + + /* calculate actual pixel clock rate which depends on internal divider */ + rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); + + /* find suitable OPP for the rate */ + opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); + + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); + + if (IS_ERR(opp)) { + dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", + rate, opp); + return; + } + + pstate = dev_pm_opp_get_required_pstate(opp, 0); + dev_pm_opp_put(opp); + + /* + * The minimum core voltage depends on the pixel clock rate (which + * depends on internal clock divider of the CRTC) and not on the + * rate of the display controller clock. This is why we're not using + * dev_pm_opp_set_rate() API and instead controlling the power domain + * directly. + */ + err = dev_pm_genpd_set_performance_state(dc->dev, pstate); + if (err) + dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", + pstate, err); +} + static void tegra_dc_commit_state(struct tegra_dc *dc, struct tegra_dc_state *state) { @@ -1801,6 +1845,8 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); } + + tegra_dc_update_voltage_state(dc, state); } static void tegra_dc_stop(struct tegra_dc *dc) @@ -1994,6 +2040,13 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, err = host1x_client_suspend(&dc->client); if (err < 0) dev_err(dc->dev, "failed to suspend: %d\n", err); + + if (dc->has_opp_table) { + err = dev_pm_genpd_set_performance_state(dc->dev, 0); + if (err) + dev_err(dc->dev, + "failed to clear power domain state: %d\n", err); + } } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, @@ -2976,6 +3029,23 @@ static int tegra_dc_couple(struct tegra_dc *dc) return 0; } +static int tegra_dc_init_opp_table(struct tegra_dc *dc) +{ + struct tegra_core_opp_params opp_params = {}; + int err; + + err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); + if (err && err != -ENODEV) + return err; + + if (err) + dc->has_opp_table = false; + else + dc->has_opp_table = true; + + return 0; +} + static int tegra_dc_probe(struct platform_device *pdev) { u64 dma_mask = dma_get_mask(pdev->dev.parent); @@ -3041,6 +3111,10 @@ static int tegra_dc_probe(struct platform_device *pdev) tegra_powergate_power_off(dc->powergate); } + err = tegra_dc_init_opp_table(dc); + if (err < 0) + return err; + dc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dc->regs)) return PTR_ERR(dc->regs); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index f0cb691852a1..26ad1e448c44 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -106,6 +106,8 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + bool has_opp_table; }; static inline struct tegra_dc * -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Jonathan Hunter" <jonathanh@nvidia.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Viresh Kumar" <vireshk@kernel.org>, "Stephen Boyd" <sboyd@kernel.org>, "Peter De Schrijver" <pdeschrijver@nvidia.com>, "Mikko Perttunen" <mperttunen@nvidia.com>, "Peter Chen" <peter.chen@kernel.org>, "Mark Brown" <broonie@kernel.org>, "Lee Jones" <lee.jones@linaro.org>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Nishanth Menon" <nm@ti.com>, "Vignesh Raghavendra" <vigneshr@ti.com>, "Richard Weinberger" <richard@nod.at>, "Miquel Raynal" <miquel.raynal@bootlin.com>, "Lucas Stach" <dev@lynxeye.de>, "Stefan Agner" <stefan@agner.ch>, "Adrian Hunter" <adrian.hunter@intel.com>, "Mauro Carvalho Chehab" <mchehab@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Michael Turquette" <mturquette@baylibre.com> Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 12/34] drm/tegra: dc: Support OPP and SoC core voltage scaling Date: Tue, 17 Aug 2021 04:27:32 +0300 [thread overview] Message-ID: <20210817012754.8710-13-digetx@gmail.com> (raw) In-Reply-To: <20210817012754.8710-1-digetx@gmail.com> Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 74 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dc.h | 2 ++ 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 16c7aabb94d3..435dd8139c6e 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -11,9 +11,12 @@ #include <linux/interconnect.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h> +#include <soc/tegra/common.h> #include <soc/tegra/pmc.h> #include <drm/drm_atomic.h> @@ -1762,6 +1765,47 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, return 0; } +static void tegra_dc_update_voltage_state(struct tegra_dc *dc, + struct tegra_dc_state *state) +{ + unsigned long rate, pstate; + struct dev_pm_opp *opp; + int err; + + if (!dc->has_opp_table) + return; + + /* calculate actual pixel clock rate which depends on internal divider */ + rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); + + /* find suitable OPP for the rate */ + opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); + + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); + + if (IS_ERR(opp)) { + dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", + rate, opp); + return; + } + + pstate = dev_pm_opp_get_required_pstate(opp, 0); + dev_pm_opp_put(opp); + + /* + * The minimum core voltage depends on the pixel clock rate (which + * depends on internal clock divider of the CRTC) and not on the + * rate of the display controller clock. This is why we're not using + * dev_pm_opp_set_rate() API and instead controlling the power domain + * directly. + */ + err = dev_pm_genpd_set_performance_state(dc->dev, pstate); + if (err) + dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", + pstate, err); +} + static void tegra_dc_commit_state(struct tegra_dc *dc, struct tegra_dc_state *state) { @@ -1801,6 +1845,8 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); } + + tegra_dc_update_voltage_state(dc, state); } static void tegra_dc_stop(struct tegra_dc *dc) @@ -1994,6 +2040,13 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, err = host1x_client_suspend(&dc->client); if (err < 0) dev_err(dc->dev, "failed to suspend: %d\n", err); + + if (dc->has_opp_table) { + err = dev_pm_genpd_set_performance_state(dc->dev, 0); + if (err) + dev_err(dc->dev, + "failed to clear power domain state: %d\n", err); + } } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, @@ -2976,6 +3029,23 @@ static int tegra_dc_couple(struct tegra_dc *dc) return 0; } +static int tegra_dc_init_opp_table(struct tegra_dc *dc) +{ + struct tegra_core_opp_params opp_params = {}; + int err; + + err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); + if (err && err != -ENODEV) + return err; + + if (err) + dc->has_opp_table = false; + else + dc->has_opp_table = true; + + return 0; +} + static int tegra_dc_probe(struct platform_device *pdev) { u64 dma_mask = dma_get_mask(pdev->dev.parent); @@ -3041,6 +3111,10 @@ static int tegra_dc_probe(struct platform_device *pdev) tegra_powergate_power_off(dc->powergate); } + err = tegra_dc_init_opp_table(dc); + if (err < 0) + return err; + dc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dc->regs)) return PTR_ERR(dc->regs); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index f0cb691852a1..26ad1e448c44 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -106,6 +106,8 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + bool has_opp_table; }; static inline struct tegra_dc * -- 2.32.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-08-17 1:30 UTC|newest] Thread overview: 238+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-17 1:27 [PATCH v8 00/34] NVIDIA Tegra power management patches for 5.16 Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 01/34] opp: Add dev_pm_opp_sync() helper Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 7:55 ` Viresh Kumar 2021-08-17 7:55 ` Viresh Kumar 2021-08-17 15:49 ` Dmitry Osipenko 2021-08-17 15:49 ` Dmitry Osipenko 2021-08-18 3:55 ` Viresh Kumar 2021-08-18 3:55 ` Viresh Kumar 2021-08-18 4:12 ` Dmitry Osipenko 2021-08-18 4:12 ` Dmitry Osipenko 2021-08-18 4:29 ` Dmitry Osipenko 2021-08-18 4:29 ` Dmitry Osipenko 2021-08-18 4:30 ` Dmitry Osipenko 2021-08-18 4:30 ` Dmitry Osipenko 2021-08-18 4:34 ` Viresh Kumar 2021-08-18 4:34 ` Viresh Kumar 2021-08-18 4:31 ` Viresh Kumar 2021-08-18 4:31 ` Viresh Kumar 2021-08-18 4:37 ` Dmitry Osipenko 2021-08-18 4:37 ` Dmitry Osipenko 2021-08-18 4:53 ` Viresh Kumar 2021-08-18 4:53 ` Viresh Kumar 2021-08-18 5:21 ` Dmitry Osipenko 2021-08-18 5:21 ` Dmitry Osipenko 2021-08-18 5:58 ` Viresh Kumar 2021-08-18 5:58 ` Viresh Kumar 2021-08-18 6:00 ` Viresh Kumar 2021-08-18 6:00 ` Viresh Kumar 2021-08-18 6:22 ` Dmitry Osipenko 2021-08-18 6:22 ` Dmitry Osipenko 2021-08-18 6:27 ` Viresh Kumar 2021-08-18 6:27 ` Viresh Kumar 2021-08-18 8:29 ` Ulf Hansson 2021-08-18 8:29 ` Ulf Hansson 2021-08-18 9:14 ` Viresh Kumar 2021-08-18 9:14 ` Viresh Kumar 2021-08-18 9:41 ` Ulf Hansson 2021-08-18 9:41 ` Ulf Hansson 2021-08-18 9:42 ` Ulf Hansson 2021-08-18 9:42 ` Ulf Hansson 2021-08-18 9:50 ` Viresh Kumar 2021-08-18 9:50 ` Viresh Kumar 2021-08-18 10:08 ` Ulf Hansson 2021-08-18 10:08 ` Ulf Hansson 2021-08-18 15:43 ` Dmitry Osipenko 2021-08-18 15:43 ` Dmitry Osipenko 2021-08-18 15:46 ` Dmitry Osipenko 2021-08-18 15:46 ` Dmitry Osipenko 2021-08-19 13:07 ` Ulf Hansson 2021-08-19 13:07 ` Ulf Hansson 2021-08-19 19:35 ` Dmitry Osipenko 2021-08-19 19:35 ` Dmitry Osipenko 2021-08-20 5:07 ` Viresh Kumar 2021-08-20 5:07 ` Viresh Kumar 2021-08-20 12:42 ` Ulf Hansson 2021-08-20 12:42 ` Ulf Hansson 2021-08-21 17:34 ` Dmitry Osipenko 2021-08-21 17:34 ` Dmitry Osipenko 2021-08-23 10:46 ` Ulf Hansson 2021-08-23 10:46 ` Ulf Hansson 2021-08-23 15:54 ` Dmitry Osipenko 2021-08-23 15:54 ` Dmitry Osipenko 2021-08-18 15:55 ` Dmitry Osipenko 2021-08-18 15:55 ` Dmitry Osipenko 2021-08-19 6:16 ` Viresh Kumar 2021-08-19 6:16 ` Viresh Kumar 2021-08-19 14:55 ` Ulf Hansson 2021-08-19 14:55 ` Ulf Hansson 2021-08-20 5:18 ` Viresh Kumar 2021-08-20 5:18 ` Viresh Kumar 2021-08-20 12:57 ` Ulf Hansson 2021-08-20 12:57 ` Ulf Hansson 2021-08-23 20:24 ` Dmitry Osipenko 2021-08-23 20:24 ` Dmitry Osipenko 2021-08-24 3:04 ` Viresh Kumar 2021-08-24 3:04 ` Viresh Kumar 2021-08-22 18:35 ` Dmitry Osipenko 2021-08-22 18:35 ` Dmitry Osipenko 2021-08-25 15:41 ` Dmitry Osipenko 2021-08-25 15:41 ` Dmitry Osipenko 2021-08-26 2:54 ` Viresh Kumar 2021-08-26 2:54 ` Viresh Kumar 2021-08-26 2:55 ` Viresh Kumar 2021-08-26 2:55 ` Viresh Kumar 2021-08-17 1:27 ` [PATCH v8 02/34] soc/tegra: pmc: Disable PMC state syncing Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 03/34] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 04/34] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 05/34] soc/tegra: Use dev_pm_opp_sync() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 06/34] dt-bindings: clock: tegra-car: Document new tegra-clocks sub-node Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:15 ` Rob Herring 2021-08-18 1:15 ` Rob Herring 2021-08-18 1:44 ` Dmitry Osipenko 2021-08-18 1:44 ` Dmitry Osipenko 2021-08-18 13:52 ` Thierry Reding 2021-08-18 13:52 ` Thierry Reding 2021-08-18 15:04 ` Dmitry Osipenko 2021-08-18 15:04 ` Dmitry Osipenko 2021-08-18 13:59 ` Thierry Reding 2021-08-18 13:59 ` Thierry Reding 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 16:39 ` Thierry Reding 2021-08-18 16:39 ` Thierry Reding 2021-08-18 16:57 ` Dmitry Osipenko 2021-08-18 16:57 ` Dmitry Osipenko 2021-08-18 17:16 ` Dmitry Osipenko 2021-08-18 17:16 ` Dmitry Osipenko 2021-08-19 16:31 ` Thierry Reding 2021-08-19 16:31 ` Thierry Reding 2021-08-19 22:20 ` Dmitry Osipenko 2021-08-19 22:20 ` Dmitry Osipenko 2021-08-20 2:51 ` Dmitry Osipenko 2021-08-20 2:51 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 07/34] clk: tegra: Support runtime PM and power domain Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 14:07 ` Thierry Reding 2021-08-18 14:07 ` Thierry Reding 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 16:42 ` Thierry Reding 2021-08-18 16:42 ` Thierry Reding 2021-08-18 17:11 ` Dmitry Osipenko 2021-08-18 17:11 ` Dmitry Osipenko 2021-08-19 16:54 ` Thierry Reding 2021-08-19 16:54 ` Thierry Reding 2021-08-19 22:09 ` Dmitry Osipenko 2021-08-19 22:09 ` Dmitry Osipenko 2021-08-20 11:42 ` Thierry Reding 2021-08-20 11:42 ` Thierry Reding 2021-08-20 13:08 ` Ulf Hansson 2021-08-20 13:08 ` Ulf Hansson 2021-08-21 17:45 ` Dmitry Osipenko 2021-08-21 17:45 ` Dmitry Osipenko 2021-08-23 14:33 ` Thierry Reding 2021-08-23 14:33 ` Thierry Reding 2021-08-23 18:54 ` Dmitry Osipenko 2021-08-23 18:54 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 08/34] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 09/34] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:16 ` Rob Herring 2021-08-18 1:16 ` Rob Herring 2021-08-18 1:37 ` Dmitry Osipenko 2021-08-18 1:37 ` Dmitry Osipenko 2021-08-18 2:04 ` Dmitry Osipenko 2021-08-18 2:04 ` Dmitry Osipenko 2021-08-18 2:07 ` Dmitry Osipenko 2021-08-18 2:07 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 10/34] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 11/34] gpu: host1x: Add runtime PM and OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 12:04 ` Ulf Hansson 2021-08-17 12:04 ` Ulf Hansson 2021-08-17 14:02 ` Thierry Reding 2021-08-17 14:02 ` Thierry Reding 2021-08-18 8:35 ` Ulf Hansson 2021-08-18 8:35 ` Ulf Hansson 2021-08-18 17:24 ` Dmitry Osipenko 2021-08-18 17:24 ` Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko [this message] 2021-08-17 1:27 ` [PATCH v8 12/34] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 13/34] drm/tegra: hdmi: Add OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 14/34] drm/tegra: gr2d: Support power management Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 15/34] drm/tegra: gr3d: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 16/34] drm/tegra: vic: Support system suspend Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 17/34] usb: chipidea: tegra: Add runtime PM and OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 18/34] bus: tegra-gmi: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 19/34] pwm: tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-19 13:21 ` Thierry Reding 2021-08-19 13:21 ` Thierry Reding 2021-08-19 14:04 ` Ulf Hansson 2021-08-19 14:04 ` Ulf Hansson 2021-08-19 16:17 ` Thierry Reding 2021-08-19 16:17 ` Thierry Reding 2021-08-17 1:27 ` [PATCH v8 20/34] mmc: sdhci-tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-19 17:03 ` Thierry Reding 2021-08-19 17:03 ` Thierry Reding 2021-08-19 22:37 ` Dmitry Osipenko 2021-08-19 22:37 ` Dmitry Osipenko 2021-08-20 11:35 ` Thierry Reding 2021-08-20 11:35 ` Thierry Reding 2021-08-25 9:45 ` Dmitry Osipenko 2021-08-25 9:45 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 21/34] mtd: rawnand: tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 8:41 ` Miquel Raynal 2021-08-17 8:41 ` Miquel Raynal 2021-08-17 1:27 ` [PATCH v8 22/34] spi: tegra20-slink: Add " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 12:22 ` Mark Brown 2021-08-17 12:22 ` Mark Brown 2021-08-17 15:53 ` Dmitry Osipenko 2021-08-17 15:53 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 23/34] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:17 ` Rob Herring 2021-08-18 1:17 ` Rob Herring 2021-08-17 1:27 ` [PATCH v8 24/34] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:17 ` Rob Herring 2021-08-18 1:17 ` Rob Herring 2021-08-17 1:27 ` [PATCH v8 25/34] media: staging: tegra-vde: Support generic power domain and OPP Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 26/34] soc/tegra: fuse: Add OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 27/34] soc/tegra: fuse: Reset hardware Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 28/34] soc/tegra: regulators: Prepare for suspend Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 29/34] soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 30/34] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 31/34] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 32/34] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 33/34] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 34/34] ARM: tegra20/30: Disable unused host1x hardware Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko
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