From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA318C4338F for ; Tue, 17 Aug 2021 09:34:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5AC5060184 for ; Tue, 17 Aug 2021 09:34:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5AC5060184 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=lmichel.fr Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:45784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mFvUo-000793-E5 for qemu-devel@archiver.kernel.org; Tue, 17 Aug 2021 05:34:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mFvTq-0005mH-KI; Tue, 17 Aug 2021 05:33:58 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:54238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mFvTo-0003Na-Iz; Tue, 17 Aug 2021 05:33:58 -0400 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 54F38C6019D; Tue, 17 Aug 2021 11:33:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1629192834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=METMcd9nRfoNTaPjmMOKcSgvLFVRhZInPlLz6EF7KSU=; b=g09eKTDfMrXjAFgV4NJ7Lz9ZvLIllWr7aPD6rvNcjcvSeQaOq+l1yTWpzGrzMuSM5TQEQ7 usjejyvcxRz5WSOTruOJlREHNADRQQV3RmoyYAK1haqRRYjZt2lnH8VXTa+NxmNLflLIMz Gvyj1DU2J0Gxh2fgUtkhoQ0UI+7VPgSY9zp+lfGhI3K7QJ06k9OmKkNHgPzXLy1GRLJBv/ J82wm+2CxqrBaS+h4OLbq3MKqsHvD6NpBJtmYNVon50VCvAq9mlDV4xrS8fkGhNd5vmP0p YO+B067NPwwLoE6KWYlpT4uEgSLl6If3WHObht4hHEItfbafkfpTD3i3cU0cLg== Date: Tue, 17 Aug 2021 11:36:06 +0200 From: Luc Michel To: Peter Maydell Subject: Re: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Message-ID: <20210817093606.wrf7nlcunwuaq4q6@sekoia-pc.home.lmichel.fr> References: <20210812093356.1946-1-peter.maydell@linaro.org> <20210812093356.1946-8-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210812093356.1946-8-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Alistair Francis , qemu-devel@nongnu.org, Subbaraya Sundeep , qemu-arm@nongnu.org, Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10:33 Thu 12 Aug , Peter Maydell wrote: > Wire up the cpuclk for the systick devices to the SSE object's > existing mainclk clock. > > We do not wire up the refclk because the SSE subsystems do not > provide a refclk. (This is documented in the IoTKit and SSE-200 > TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the > same approach.) When we update the systick device later to honour "no > refclk connected" this will fix a minor emulation inaccuracy for the > SSE-based boards. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/armsse.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index a1456cb0f42..70b52c3d4b9 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **errp) > int j; > char *gpioname; > > + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk); > + /* The SSE subsystems do not wire up a systick refclk */ > + > qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS); > /* > * In real hardware the initial Secure VTOR is set from the INITSVTOR* > -- > 2.20.1 > --