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[31.30.174.132]) by smtp.gmail.com with ESMTPSA id d16sm1300380edu.8.2021.08.17.09.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 09:28:13 -0700 (PDT) Date: Tue, 17 Aug 2021 18:28:11 +0200 From: Andrew Jones To: Richard Henderson Subject: Re: [PATCH v4 1/3] target-arm: Add support for Fujitsu A64FX Message-ID: <20210817162811.u3i5hcx7eg52akyq@gator.home> References: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> <20210812060440.1330348-2-ishii.shuuichir@fujitsu.com> <20210812091650.i5np3szvdoelu2cx@gator.home> <20210812092517.mwcfhksoe4cgy3cl@gator.home> <20210817115635.d2wxvnvis5kupegh@gator.home> <667f9384-cd28-8e4d-ebd1-4ed4b651676a@linaro.org> <20210817153639.o5fxdgmuhjusvyhq@gator.home> <3846b738-719f-a9a1-a59d-d7f54e71009c@linaro.org> MIME-Version: 1.0 In-Reply-To: <3846b738-719f-a9a1-a59d-d7f54e71009c@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.7, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "peter.maydell@linaro.org" , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "ishii.shuuichir@fujitsu.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Aug 17, 2021 at 05:53:34AM -1000, Richard Henderson wrote: > On 8/17/21 5:36 AM, Andrew Jones wrote: > > On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote: > > > On 8/17/21 1:56 AM, Andrew Jones wrote: > > > > I guess it's fine. You could easily create a new cpu_arm_set_sve_vq() > > > > which would forbid changing the properties if you wanted to, but then > > > > we need to answer Peter's question in order to see if there's a > > > > precedent for that type of property. > > > > > > I don't see the point in read-only properties. If the user wants to set > > > non-standard values on the command-line, let them. What is most important > > > is getting the correct default from '-cpu a64fx'. > > > > > > > So maybe we should just go ahead and add all sve* properties, but then > > make sure the default vq map is correct. > > I think that's the right answer. > > Presently we have a kvm_supported variable that's initialized by > kvm_arm_sve_get_vls(). I think we want to rename that variable and provide > a version of that function for tcg. Probably we should have done that > before, with a trivial function for -cpu max to set all bits. > > Then eliminate most of the other kvm_enabled() checks in > arm_cpu_sve_finalize. I think the only one we keep is the last, where we > verify that the final sve_vq_map matches kvm_enabled exactly, modulo max_vq. > > This should minimize the differences in behaviour between tcg and kvm. That's a good idea. I'll send a patch with your suggested-by. Thanks, drew