From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41CF7C4338F for ; Wed, 18 Aug 2021 14:15:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1102F610A7 for ; Wed, 18 Aug 2021 14:15:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1102F610A7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aEZFOnFvsgMxuN99MF8PGNKpw4AKvm+YvJrZfOq7OYE=; b=U80gGlxpALZXIY E+kvapefoMOU/D6CK+ua17cNXAqzkyL7aNA77C/Sof+3APElFN/WamyCbyDYbIzvk6+JGOZeF1oWQ NMKF1/iTlUcvhiH3V7d3vD+v5Wc/9iPMnDzK4fNEchZaAOaXjBEWcvasm4FGHNALo9eePOOXidmPE 28pNaeM4erViY88rXnNdDdyUAMoi0/Bb3KZsFe982TbcUV8DsYSMA9dUF160MrmzDgZRCVklGG6M1 ItZUBsJjezn4Nbezy21amms1+VctwjBTDgGfs2FNQ0x8/mLDX+4kzRRidEZSy/JrZJlifJTNdkvPb Lfsma9PSJWZFjYsUcsww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGMJk-005psV-Nh; Wed, 18 Aug 2021 14:13:21 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGMJV-005pnW-Er for linux-arm-kernel@lists.infradead.org; Wed, 18 Aug 2021 14:13:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E22E61063; Wed, 18 Aug 2021 07:13:00 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.85.180]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C242C3F40C; Wed, 18 Aug 2021 07:12:59 -0700 (PDT) Date: Wed, 18 Aug 2021 15:12:56 +0100 From: Mark Rutland To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [boot-wrapper PATCH] aarch64: Do not trap PMSNEVFR_EL1 Message-ID: <20210818141256.GB64368@C02TD0UTHF1T.local> References: <20210817163420.813631-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210817163420.813631-1-alexandru.elisei@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210818_071305_611120_F91716AF X-CRM114-Status: GOOD ( 15.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Aug 17, 2021 at 05:34:20PM +0100, Alexandru Elisei wrote: > FEAT_PMUv1p2 adds a new register, PMSNEVFR_EL1, and a new MDCR_EL3 trap bit > for it, EnPMSN. Set the bit to 1 to allow lower exception levels direct > access to the register. > > Signed-off-by: Alexandru Elisei Thanks for this; I have a couple of minor comments below, which I'll fix up when applying. > --- > arch/aarch64/boot.S | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 2215f7ed3a1f..8951f1e4676a 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -88,8 +88,12 @@ ASM_FUNC(_start) > cbz x1, 1f > > // Enable SPE for the non-secure world. > - ldr x1, =(0x3 << 12) > - orr x0, x0, x1 > + ldr x2, =(0x3 << 12) > + orr x0, x0, x2 Since we're touching this, I'll make it: orr x0, x0, #(3 << 12) > + cmp x1, #3 > + b.lt 1 For consistency, I'll make this `b.lt 1f` > + // Do not trap PMSNEVFR_EL1. > + orr x0, x0, #(1 << 36) For legibility, I'll re-order this as: // Do not trap PMSNEVFR_EL1 if present. cmp x1, #3 b.lt 1f orr x0, x0, #(1 << 36) Thanks, Mark. > > 1: mrs x1, id_aa64dfr0_el1 > ubfx x1, x1, #44, #4 > -- > 2.32.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel