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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id v14sm287148lji.32.2021.08.19.08.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Aug 2021 08:08:45 -0700 (PDT) Date: Thu, 19 Aug 2021 17:08:45 +0200 From: "Edgar E. Iglesias" To: Tong Ho Subject: Re: [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Message-ID: <20210819150845.GF3586016@toto> References: <20210819040308.675057-1-tong.ho@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210819040308.675057-1-tong.ho@xilinx.com> Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alistair@alistair23.me Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Aug 18, 2021 at 09:02:59PM -0700, Tong Ho wrote: > This series implements the Xilinx eFUSE and BBRAM devices for > the Versal and ZynqMP product families. > > Furthermore, both new devices are connected to the xlnx-versal-virt > board and the xlnx-zcu102 board. Hi Tong, A few general comments. Patch #1 should probably be moved to be the last patch of the series. I think we should remove the commands about register generation "Partially generated by xregqemu.py". It may be confusing to others since it's not a tool we run in the build process but rather a one off extraction of reg definitions... Thanks! Edgar