From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36AC4C4320A for ; Fri, 20 Aug 2021 12:07:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B0E760EB5 for ; Fri, 20 Aug 2021 12:07:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240003AbhHTMHi convert rfc822-to-8bit (ORCPT ); Fri, 20 Aug 2021 08:07:38 -0400 Received: from relay8-d.mail.gandi.net ([217.70.183.201]:48089 "EHLO relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237764AbhHTMHh (ORCPT ); Fri, 20 Aug 2021 08:07:37 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 9DFEF1BF207; Fri, 20 Aug 2021 12:06:57 +0000 (UTC) Date: Fri, 20 Aug 2021 14:06:56 +0200 From: Miquel Raynal To: Apurva Nandan Cc: Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , , Pratyush Yadav Subject: Re: [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Message-ID: <20210820140656.72819d90@xps13> In-Reply-To: References: <20210713130538.646-1-a-nandan@ti.com> <20210713130538.646-5-a-nandan@ti.com> <20210806204334.5fedea42@xps13> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Apurva, Apurva Nandan wrote on Fri, 20 Aug 2021 15:57:36 +0530: > Hi Miquèl, > > On 07/08/21 12:13 am, Miquel Raynal wrote: > > Hi Apurva, > > > > Apurva Nandan wrote on Tue, 13 Jul 2021 13:05:29 > > +0000: > > > >> In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock > >> cycle, and half-cycle instruction phases aren't supported yet. So, > >> every DTR spi_mem_op needs to have even nbytes in all phases for > >> non-erratic behaviour from the SPI controller. > >> > >> The odd length cmd and dummy phases get handled by spimem_setup_op() > >> but the odd length address and data phases need to be handled according > >> to the use case. For example in Octal DTR mode, read register operation > >> has one byte long address and data phase. So it needs to extend it > >> by adding a suitable extra byte in addr and reading 2 bytes of data, > >> discarding the second byte. > >> > >> Handle address and data phases for Octal DTR mode in read/write > >> register and write volatile configuration register operations > >> by adding a suitable extra byte in the address and data phase. > >> > >> Create spimem_setup_reg_op() helper function to ease setting up > >> read/write register operations in other functions, e.g. wait(). > >> > >> Signed-off-by: Apurva Nandan > >> --- > >> drivers/mtd/nand/spi/core.c | 26 +++++++++++++++++++++----- > >> 1 file changed, 21 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > >> index 2e59faecc8f5..a5334ad34f96 100644 > >> --- a/drivers/mtd/nand/spi/core.c > >> +++ b/drivers/mtd/nand/spi/core.c > >> @@ -65,12 +65,27 @@ static void spinand_setup_op(const struct spinand_device *spinand, > >> } > >> } > >> >> +static void spinand_setup_reg_op(const struct spinand_device *spinand, > >> + struct spi_mem_op *op) > > > > Same remark about the naming. In fact I believe we could have this > > logic in _setup_op() (or whatever its name) and add a specific > > parameter for it? > > > > Okay, I will add a parameter in argument and include this logic in _setup_op(). > > >> +{ > >> + if (spinand->reg_proto == SPINAND_OCTAL_DTR) { > >> + /* > >> + * Assigning same first and second byte will result in constant > >> + * bits on ths SPI bus between positive and negative clock edges > > > > the > > > > Ok. > > >> + */ > >> + op->addr.val = (op->addr.val << 8) | op->addr.val; > > > > I am not sure to understand what you do here? > > > > In Octal DTR mode, 2 bytes of data are sent in a clock cycle. So, we need to append one extra byte when sending a single byte. This extra byte would be sent on the negative edge. > > It will make sense to keep both the bytes same, as when it will be set on the SPI pins, the bits on the SPI IO ports will remain constant between the positive and negative edges (as 1 complete byte is set in one clock edge in MSB order). There are no restrictions by the manufacturers on this, the relevant address byte needs to be on positive edge and second byte on negative edge is don't care. I was bothered by the shift but actually my head was mixing with the raw NAND core where these addresses are in an array but here it is a u64 which is then fine. (I will continue answering probably next week) Thanks, Miquèl From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B14AC4320A for ; Fri, 20 Aug 2021 12:08:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5AB0360F92 for ; Fri, 20 Aug 2021 12:08:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5AB0360F92 Authentication-Results: mail.kernel.org; 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Fri, 20 Aug 2021 12:08:07 +0000 Received: from relay8-d.mail.gandi.net ([217.70.183.201]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH3Ic-00B3fG-6d for linux-mtd@lists.infradead.org; Fri, 20 Aug 2021 12:07:06 +0000 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 9DFEF1BF207; Fri, 20 Aug 2021 12:06:57 +0000 (UTC) Date: Fri, 20 Aug 2021 14:06:56 +0200 From: Miquel Raynal To: Apurva Nandan Cc: Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , , Pratyush Yadav Subject: Re: [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Message-ID: <20210820140656.72819d90@xps13> In-Reply-To: References: <20210713130538.646-1-a-nandan@ti.com> <20210713130538.646-5-a-nandan@ti.com> <20210806204334.5fedea42@xps13> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_050702_601145_B47AE752 X-CRM114-Status: GOOD ( 32.61 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgQXB1cnZhLAoKQXB1cnZhIE5hbmRhbiA8YS1uYW5kYW5AdGkuY29tPiB3cm90ZSBvbiBGcmks IDIwIEF1ZyAyMDIxIDE1OjU3OjM2CiswNTMwOgoKPiBIaSBNaXF1w6hsLAo+IAo+IE9uIDA3LzA4 LzIxIDEyOjEzIGFtLCBNaXF1ZWwgUmF5bmFsIHdyb3RlOgo+ID4gSGkgQXB1cnZhLAo+ID4gCj4g PiBBcHVydmEgTmFuZGFuIDxhLW5hbmRhbkB0aS5jb20+IHdyb3RlIG9uIFR1ZSwgMTMgSnVsIDIw MjEgMTM6MDU6MjkKPiA+ICswMDAwOgo+ID4gICAKPiA+PiBJbiBPY3RhbCBEVFIgU1BJIG1vZGUs IDIgYnl0ZXMgb2YgZGF0YSBnZXRzIHRyYW5zbWl0dGVkIG92ZXIgb25lIGNsb2NrCj4gPj4gY3lj bGUsIGFuZCBoYWxmLWN5Y2xlIGluc3RydWN0aW9uIHBoYXNlcyBhcmVuJ3Qgc3VwcG9ydGVkIHll dC4gU28sCj4gPj4gZXZlcnkgRFRSIHNwaV9tZW1fb3AgbmVlZHMgdG8gaGF2ZSBldmVuIG5ieXRl cyBpbiBhbGwgcGhhc2VzIGZvcgo+ID4+IG5vbi1lcnJhdGljIGJlaGF2aW91ciBmcm9tIHRoZSBT UEkgY29udHJvbGxlci4KPiA+Pgo+ID4+IFRoZSBvZGQgbGVuZ3RoIGNtZCBhbmQgZHVtbXkgcGhh c2VzIGdldCBoYW5kbGVkIGJ5IHNwaW1lbV9zZXR1cF9vcCgpCj4gPj4gYnV0IHRoZSBvZGQgbGVu Z3RoIGFkZHJlc3MgYW5kIGRhdGEgcGhhc2VzIG5lZWQgdG8gYmUgaGFuZGxlZCBhY2NvcmRpbmcK PiA+PiB0byB0aGUgdXNlIGNhc2UuIEZvciBleGFtcGxlIGluIE9jdGFsIERUUiBtb2RlLCByZWFk IHJlZ2lzdGVyIG9wZXJhdGlvbgo+ID4+IGhhcyBvbmUgYnl0ZSBsb25nIGFkZHJlc3MgYW5kIGRh dGEgcGhhc2UuIFNvIGl0IG5lZWRzIHRvIGV4dGVuZCBpdAo+ID4+IGJ5IGFkZGluZyBhIHN1aXRh YmxlIGV4dHJhIGJ5dGUgaW4gYWRkciBhbmQgcmVhZGluZyAyIGJ5dGVzIG9mIGRhdGEsCj4gPj4g ZGlzY2FyZGluZyB0aGUgc2Vjb25kIGJ5dGUuCj4gPj4KPiA+PiBIYW5kbGUgYWRkcmVzcyBhbmQg ZGF0YSBwaGFzZXMgZm9yIE9jdGFsIERUUiBtb2RlIGluIHJlYWQvd3JpdGUKPiA+PiByZWdpc3Rl ciBhbmQgd3JpdGUgdm9sYXRpbGUgY29uZmlndXJhdGlvbiByZWdpc3RlciBvcGVyYXRpb25zCj4g Pj4gYnkgYWRkaW5nIGEgc3VpdGFibGUgZXh0cmEgYnl0ZSBpbiB0aGUgYWRkcmVzcyBhbmQgZGF0 YSBwaGFzZS4KPiA+Pgo+ID4+IENyZWF0ZSBzcGltZW1fc2V0dXBfcmVnX29wKCkgaGVscGVyIGZ1 bmN0aW9uIHRvIGVhc2Ugc2V0dGluZyB1cAo+ID4+IHJlYWQvd3JpdGUgcmVnaXN0ZXIgb3BlcmF0 aW9ucyBpbiBvdGhlciBmdW5jdGlvbnMsIGUuZy4gd2FpdCgpLgo+ID4+Cj4gPj4gU2lnbmVkLW9m Zi1ieTogQXB1cnZhIE5hbmRhbiA8YS1uYW5kYW5AdGkuY29tPgo+ID4+IC0tLQo+ID4+ICAgZHJp dmVycy9tdGQvbmFuZC9zcGkvY29yZS5jIHwgMjYgKysrKysrKysrKysrKysrKysrKysrLS0tLS0K PiA+PiAgIDEgZmlsZSBjaGFuZ2VkLCAyMSBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+ ID4+Cj4gPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbXRkL25hbmQvc3BpL2NvcmUuYyBiL2RyaXZl cnMvbXRkL25hbmQvc3BpL2NvcmUuYwo+ID4+IGluZGV4IDJlNTlmYWVjYzhmNS4uYTUzMzRhZDM0 Zjk2IDEwMDY0NAo+ID4+IC0tLSBhL2RyaXZlcnMvbXRkL25hbmQvc3BpL2NvcmUuYwo+ID4+ICsr KyBiL2RyaXZlcnMvbXRkL25hbmQvc3BpL2NvcmUuYwo+ID4+IEBAIC02NSwxMiArNjUsMjcgQEAg c3RhdGljIHZvaWQgc3BpbmFuZF9zZXR1cF9vcChjb25zdCBzdHJ1Y3Qgc3BpbmFuZF9kZXZpY2Ug KnNwaW5hbmQsCj4gPj4gICAJfQo+ID4+ICAgfSAgCj4gPj4gICA+PiArc3RhdGljIHZvaWQgc3Bp bmFuZF9zZXR1cF9yZWdfb3AoY29uc3Qgc3RydWN0IHNwaW5hbmRfZGV2aWNlICpzcGluYW5kLCAg Cj4gPj4gKwkJCQkgc3RydWN0IHNwaV9tZW1fb3AgKm9wKSAgCj4gPiAKPiA+IFNhbWUgcmVtYXJr IGFib3V0IHRoZSBuYW1pbmcuIEluIGZhY3QgSSBiZWxpZXZlIHdlIGNvdWxkIGhhdmUgdGhpcwo+ ID4gbG9naWMgaW4gX3NldHVwX29wKCkgKG9yIHdoYXRldmVyIGl0cyBuYW1lKSBhbmQgYWRkIGEg c3BlY2lmaWMKPiA+IHBhcmFtZXRlciBmb3IgaXQ/Cj4gPiAgIAo+IAo+IE9rYXksIEkgd2lsbCBh ZGQgYSBwYXJhbWV0ZXIgaW4gYXJndW1lbnQgYW5kIGluY2x1ZGUgdGhpcyBsb2dpYyBpbiBfc2V0 dXBfb3AoKS4KPiAKPiA+PiArewo+ID4+ICsJaWYgKHNwaW5hbmQtPnJlZ19wcm90byA9PSBTUElO QU5EX09DVEFMX0RUUikgewo+ID4+ICsJCS8qCj4gPj4gKwkJICogQXNzaWduaW5nIHNhbWUgZmly c3QgYW5kIHNlY29uZCBieXRlIHdpbGwgcmVzdWx0IGluIGNvbnN0YW50Cj4gPj4gKwkJICogYml0 cyBvbiB0aHMgU1BJIGJ1cyBiZXR3ZWVuIHBvc2l0aXZlIGFuZCBuZWdhdGl2ZSBjbG9jayBlZGdl cyAgCj4gPiAKPiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICB0aGUKPiA+ICAgCj4gCj4g T2suCj4gCj4gPj4gKwkJICovCj4gPj4gKwkJb3AtPmFkZHIudmFsID0gKG9wLT5hZGRyLnZhbCA8 PCA4KSB8IG9wLT5hZGRyLnZhbDsgIAo+ID4gCj4gPiBJIGFtIG5vdCBzdXJlIHRvIHVuZGVyc3Rh bmQgd2hhdCB5b3UgZG8gaGVyZT8KPiA+ICAgCj4gCj4gSW4gT2N0YWwgRFRSIG1vZGUsIDIgYnl0 ZXMgb2YgZGF0YSBhcmUgc2VudCBpbiBhIGNsb2NrIGN5Y2xlLiBTbywgd2UgbmVlZCB0byBhcHBl bmQgb25lIGV4dHJhIGJ5dGUgd2hlbiBzZW5kaW5nIGEgc2luZ2xlIGJ5dGUuIFRoaXMgZXh0cmEg Ynl0ZSB3b3VsZCBiZSBzZW50IG9uIHRoZSBuZWdhdGl2ZSBlZGdlLgo+IAo+IEl0IHdpbGwgbWFr ZSBzZW5zZSB0byBrZWVwIGJvdGggdGhlIGJ5dGVzIHNhbWUsIGFzIHdoZW4gaXQgd2lsbCBiZSBz ZXQgb24gdGhlIFNQSSBwaW5zLCB0aGUgYml0cyBvbiB0aGUgU1BJIElPIHBvcnRzIHdpbGwgcmVt YWluIGNvbnN0YW50IGJldHdlZW4gdGhlIHBvc2l0aXZlIGFuZCBuZWdhdGl2ZSBlZGdlcyAoYXMg MSBjb21wbGV0ZSBieXRlIGlzIHNldCBpbiBvbmUgY2xvY2sgZWRnZSBpbiBNU0Igb3JkZXIpLiBU aGVyZSBhcmUgbm8gcmVzdHJpY3Rpb25zIGJ5IHRoZSBtYW51ZmFjdHVyZXJzIG9uIHRoaXMsIHRo ZSByZWxldmFudCBhZGRyZXNzIGJ5dGUgbmVlZHMgdG8gYmUgb24gcG9zaXRpdmUgZWRnZSBhbmQg c2Vjb25kIGJ5dGUgb24gbmVnYXRpdmUgZWRnZSBpcyBkb24ndCBjYXJlLgoKSSB3YXMgYm90aGVy ZWQgYnkgdGhlIHNoaWZ0IGJ1dCBhY3R1YWxseSBteSBoZWFkIHdhcyBtaXhpbmcgd2l0aCB0aGUK cmF3IE5BTkQgY29yZSB3aGVyZSB0aGVzZSBhZGRyZXNzZXMgYXJlIGluIGFuIGFycmF5IGJ1dCBo ZXJlIGl0IGlzIGEKdTY0IHdoaWNoIGlzIHRoZW4gZmluZS4KCihJIHdpbGwgY29udGludWUgYW5z d2VyaW5nIHByb2JhYmx5IG5leHQgd2VlaykKClRoYW5rcywKTWlxdcOobAoKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4IE1URCBkaXNj dXNzaW9uIG1haWxpbmcgbGlzdApodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2xpbnV4LW10ZC8K