All of lore.kernel.org
 help / color / mirror / Atom feed
From: Greg Kurz <groug@kaod.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 01/26] ppc: Add a POWER10 DD2 CPU
Date: Fri, 20 Aug 2021 15:40:26 +0200	[thread overview]
Message-ID: <20210820154026.614dd703@bahia.lan> (raw)
In-Reply-To: <20210809134547.689560-2-clg@kaod.org>

On Mon, 9 Aug 2021 15:45:22 +0200
Cédric Le Goater <clg@kaod.org> wrote:

> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
> HAIL but since it does not break the modeling and that we don't plan
> to support DD1, modify the LPCR mask of all the POWER10 family.
> 

Maybe consider dropping DD1 at some point then ?

Anyway,

Reviewed-by: Greg Kurz <groug@kaod.org>

> Setting the HAIL bit is a requirement to support the scv instruction
> on PowerNV POWER10 platforms since glibc-2.33.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  target/ppc/cpu-models.h | 1 +
>  target/ppc/cpu-models.c | 4 +++-
>  target/ppc/cpu_init.c   | 3 +++
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index fc5e21728d7e..095259275941 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -375,6 +375,7 @@ enum {
>      CPU_POWERPC_POWER9_DD20        = 0x004E1200,
>      CPU_POWERPC_POWER10_BASE       = 0x00800000,
>      CPU_POWERPC_POWER10_DD1        = 0x00800100,
> +    CPU_POWERPC_POWER10_DD20       = 0x00800200,
>      CPU_POWERPC_970_v22            = 0x00390202,
>      CPU_POWERPC_970FX_v10          = 0x00391100,
>      CPU_POWERPC_970FX_v20          = 0x003C0200,
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index 87e4228614b0..4baa111713b0 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -776,6 +776,8 @@
>                  "POWER9 v2.0")
>      POWERPC_DEF("power10_v1.0",  CPU_POWERPC_POWER10_DD1,            POWER10,
>                  "POWER10 v1.0")
> +    POWERPC_DEF("power10_v2.0",  CPU_POWERPC_POWER10_DD20,           POWER10,
> +                "POWER10 v2.0")
>  #endif /* defined (TARGET_PPC64) */
>  
>  /***************************************************************************/
> @@ -952,7 +954,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>      { "power8", "power8_v2.0" },
>      { "power8nvl", "power8nvl_v1.0" },
>      { "power9", "power9_v2.0" },
> -    { "power10", "power10_v1.0" },
> +    { "power10", "power10_v2.0" },
>  #endif
>  
>      /* Generic PowerPCs */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 505a0ed6ac09..66deb18a6b65 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -8270,6 +8270,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>                               LPCR_DEE | LPCR_OEE))
>          | LPCR_MER | LPCR_GTSE | LPCR_TC |
>          LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> +    /* DD2 adds an extra HAIL bit */
> +    pcc->lpcr_mask |= LPCR_HAIL;
> +
>      pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
>      pcc->mmu_model = POWERPC_MMU_3_00;
>  #if defined(CONFIG_SOFTMMU)



  reply	other threads:[~2021-08-20 13:41 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-09 13:45 [PATCH 00/26] ppc/pnv: Extend the powernv10 machine Cédric Le Goater
2021-08-09 13:45 ` [PATCH 01/26] ppc: Add a POWER10 DD2 CPU Cédric Le Goater
2021-08-20 13:40   ` Greg Kurz [this message]
2021-08-30  7:10     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 02/26] ppc/pnv: Change the POWER10 machine to support DD2 only Cédric Le Goater
2021-08-20 13:41   ` Greg Kurz
2021-08-09 13:45 ` [PATCH 03/26] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode Cédric Le Goater
2021-08-09 13:45 ` [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id Cédric Le Goater
2021-08-20 13:51   ` Greg Kurz
2021-08-30  7:11     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 05/26] ppc/pnv: Distribute RAM among the chips Cédric Le Goater
2021-08-20 14:08   ` Greg Kurz
2021-08-30  7:14     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 06/26] ppc/pnv: add a chip topology index for POWER10 Cédric Le Goater
2021-08-20 14:12   ` Greg Kurz
2021-08-30  7:15     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 07/26] ppc/xive: Export PQ get/set routines Cédric Le Goater
2021-08-09 13:45 ` [PATCH 08/26] ppc/xive: Export xive_presenter_notify() Cédric Le Goater
2021-08-09 13:45 ` [PATCH 09/26] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
2021-08-10  6:06   ` David Gibson
2021-08-10 13:04     ` Cédric Le Goater
2021-08-23 15:15   ` Greg Kurz
2021-08-30  7:17     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
2021-08-25  6:01   ` David Gibson
2021-08-30  7:15     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 11/26] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
2021-08-09 13:45 ` [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
2021-08-25  6:06   ` David Gibson
2021-08-09 13:45 ` [PATCH 13/26] ppc/pnv: Add POWER10 quads Cédric Le Goater
2021-08-25  6:09   ` David Gibson
2021-08-31 13:45     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 14/26] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
2021-08-09 13:45 ` [PATCH 15/26] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
2021-08-25  6:12   ` David Gibson
2021-08-09 13:45 ` [PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
2021-08-09 13:45 ` [PATCH 17/26] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
2021-08-09 13:45 ` [PATCH 18/26] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
2021-08-09 13:45 ` [PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
2021-08-09 13:45 ` [PATCH 20/26] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
2021-08-09 13:45 ` [PATCH 21/26] pnv/xive2: Introduce new capability bits Cédric Le Goater
2021-08-09 13:45 ` [PATCH 22/26] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
2021-08-09 13:45 ` [PATCH 23/26] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
2021-08-09 13:45 ` [PATCH 24/26] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
2021-08-09 13:45 ` [PATCH 25/26] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
2021-08-09 13:45 ` [PATCH 26/26] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
2021-08-10  3:07 ` [PATCH 00/26] ppc/pnv: Extend the powernv10 machine David Gibson
2021-08-10  3:12 ` David Gibson
2021-08-10  8:58   ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210820154026.614dd703@bahia.lan \
    --to=groug@kaod.org \
    --cc=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.