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From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [PATCH 2/9] global: Remove unused or unnecessary CONFIG symbols related to DDR
Date: Sat, 21 Aug 2021 13:50:12 -0400	[thread overview]
Message-ID: <20210821175019.24180-2-trini@konsulko.com> (raw)
In-Reply-To: <20210821175019.24180-1-trini@konsulko.com>

These symbols are now either unused or were only used within the config
file to determine other logic, which could be done in a way that doesn't
further pollute the CONFIG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc83xx/spd_sdram.c      | 10 -------
 arch/powerpc/include/asm/config.h         |  3 +-
 board/freescale/mpc8349emds/mpc8349emds.c | 23 ---------------
 drivers/dma/fsl_dma.c                     |  4 +--
 include/configs/MPC8349EMDS.h             | 36 -----------------------
 include/configs/MPC8349EMDS_SDRAM.h       | 36 -----------------------
 include/configs/MPC837XERDB.h             |  8 -----
 include/configs/UCP1020.h                 |  9 ------
 include/configs/km/km-mpc83xx.h           |  1 -
 include/configs/socrates.h                |  1 -
 post/cpu/mpc83xx/ecc.c                    |  5 ----
 11 files changed, 2 insertions(+), 134 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index a861e8dd2ddc..e12043b26093 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -834,12 +834,6 @@ long int spd_sdram()
 #endif
 	debug("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
 
-#if defined(CONFIG_DDR_2T_TIMING)
-	/*
-	 * Enable 2T timing by setting sdram_cfg[16].
-	 */
-	sdram_cfg |= SDRAM_CFG_2T_EN;
-#endif
 	/* Enable controller, and GO! */
 	ddr->sdram_cfg = sdram_cfg;
 	sync();
@@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size)
 	pattern[0] = 0xdeadbeef;
 	pattern[1] = 0xdeadbeef;
 
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-	dma_meminit(pattern[0], dram_size);
-#else
 	debug("ddr init: CPU FP write method\n");
 	size = dram_size;
 	for (p = 0; p < (u64*)(size); p++) {
 		ppcDWstore((u32*)p, pattern);
 	}
 	sync();
-#endif
 
 	t_end = get_tbms();
 	icache_disable();
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 2c96378efef8..2a78551ce39c 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -28,8 +28,7 @@
 
 /* Check if boards need to enable FSL DMA engine for SDRAM init */
 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
-	((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+#if ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
 	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
 #define CONFIG_FSL_DMA
 #endif
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 5f38639afd42..861cf5d6b7ec 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -102,21 +102,6 @@ int fixed_sdram(void)
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
-#ifdef CONFIG_DDR_II
-	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
@@ -136,18 +121,10 @@ int fixed_sdram(void)
 
 	im->ddr.sdram_cfg =
 		SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-		| SDRAM_CFG_2T_EN
-#endif
 		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
-	/* for 32-bit mode burst length is 8 */
-	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 
 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
 	udelay(200);
 
 	/* enable DDR controller */
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index b7eddf0f04c5..1864b5d88b08 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -130,11 +130,9 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
 
 /*
  * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
- * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
  */
 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&	\
-	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||		\
-	(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
 void dma_meminit(uint val, uint size)
 {
 	uint *p = 0;
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index d6ae419456ae..97f6d2678dab 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -38,23 +38,9 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef  CONFIG_DDR_2T_TIMING
-
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -70,21 +56,6 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR		0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
-#define CONFIG_SYS_DDR_TIMING_0		0x00220802
-#define CONFIG_SYS_DDR_TIMING_1		0x38357322
-#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
-#define CONFIG_SYS_DDR_MODE		0x47d00432
-#define CONFIG_SYS_DDR_MODE2		0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#else
 #define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
 				| CSCONFIG_ROW_BIT_13 \
 				| CSCONFIG_COL_BIT_10)
@@ -93,17 +64,10 @@
 #define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
-				/* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE	0x00000023
-#else
 /* the default burst length is 4 - for 64-bit data path */
 				/* DLL,normal,seq,4/2.5, 4 burst len */
 #define CONFIG_SYS_DDR_MODE	0x00000022
 #endif
-#endif
-#endif
 
 /*
  * SDRAM on the Local Bus
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 8ebca99d98b8..4c1073d52720 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -38,23 +38,9 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef  CONFIG_DDR_2T_TIMING
-
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -70,21 +56,6 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR		0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
-#define CONFIG_SYS_DDR_TIMING_0		0x00220802
-#define CONFIG_SYS_DDR_TIMING_1		0x38357322
-#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
-#define CONFIG_SYS_DDR_MODE		0x47d00432
-#define CONFIG_SYS_DDR_MODE2		0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#else
 #define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
 				| CSCONFIG_ROW_BIT_13 \
 				| CSCONFIG_COL_BIT_10)
@@ -93,17 +64,10 @@
 #define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
-				/* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE	0x00000023
-#else
 /* the default burst length is 4 - for 64-bit data path */
 				/* DLL,normal,seq,4/2.5, 4 burst len */
 #define CONFIG_SYS_DDR_MODE	0x00000022
 #endif
-#endif
-#endif
 
 /*
  * SDRAM on the Local Bus
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 0a136b4f92f5..f60bc5c1ee0e 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -113,17 +113,9 @@
 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */
 
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-					| SDRAM_CFG_32_BE \
-					| SDRAM_CFG_2T_EN)
-					/* 0x43088000 */
-#else
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
 					/* 0x43000000 */
-#endif
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index d9a777ea1a0e..70dbb4cb0d20 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -171,11 +171,6 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
@@ -204,11 +199,7 @@
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
 #define CONFIG_SYS_DDR_CONTROL		0xE70C0000	/* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3 */
-#endif
 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index ecf4378bf1cc..96eb81df4c20 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -18,7 +18,6 @@
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE		2048 /* MB */
 
 /*
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index da60546966cd..0efb44ad43c3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -72,7 +72,6 @@
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */
 
-#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
 
 /* Hardcoded values, to use instead of SPD */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c
index cc971a890978..f88eff8998f9 100644
--- a/post/cpu/mpc83xx/ecc.c
+++ b/post/cpu/mpc83xx/ecc.c
@@ -70,10 +70,6 @@ int ecc_post_test(int flags)
 	int_state = disable_interrupts();
 	icache_enable();
 
-#ifdef CONFIG_DDR_32BIT
-	/* It seems like no one really uses the CONFIG_DDR_32BIT mode */
-#error "Add ECC POST support for CONFIG_DDR_32BIT here!"
-#else
 	for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
 	     addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
 
@@ -138,7 +134,6 @@ int ecc_post_test(int flags)
 
 		errbit %= 63;
 	}
-#endif /* !CONFIG_DDR_32BIT */
 
 	ecc_clear(ddr);
 
-- 
2.17.1


  reply	other threads:[~2021-08-21 17:50 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-21 17:50 [PATCH 1/9] Kconfig: Use spaces not tabs in Kconfig entires Tom Rini
2021-08-21 17:50 ` Tom Rini [this message]
2021-08-21 17:50 ` [PATCH 3/9] mvebu: Migrate CONFIG_DDR_32BIT/64BIT to Kconfig Tom Rini
2021-08-24 10:53   ` Marek Behún
2021-08-31  5:45   ` Stefan Roese
2021-08-21 17:50 ` [PATCH 4/9] mvebu: ddr: Rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE Tom Rini
2021-08-22 11:35   ` Marek Behún
2021-08-22 11:40     ` Pali Rohár
2021-08-24 10:52   ` Marek Behún
2021-08-31  5:51   ` Stefan Roese
2021-08-31 12:43     ` Tom Rini
2021-09-01  5:27       ` Stefan Roese
2021-09-01 11:29         ` Tom Rini
2021-09-01 14:32           ` Stefan Roese
2021-08-21 17:50 ` [PATCH 5/9] mvebe: Migrate CONFIG_DDR_LOG_LEVEL to Kconfig Tom Rini
2021-08-21 17:50 ` [PATCH 6/9] ddr: Migrate DDR_SPD " Tom Rini
2021-08-21 17:50 ` [PATCH 7/9] nxp: Migrate CONFIG_DDR_CLK_FREQ " Tom Rini
2021-08-21 17:50 ` [PATCH 8/9] nxp: Migrate a number of DDR related symbols " Tom Rini
2021-08-21 17:50 ` [PATCH 9/9] Convert CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT " Tom Rini
2021-08-31 22:09 ` [PATCH 1/9] Kconfig: Use spaces not tabs in Kconfig entires Tom Rini

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