From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BC6DC432BE for ; Wed, 25 Aug 2021 10:06:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0AD7760E76 for ; Wed, 25 Aug 2021 10:06:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0AD7760E76 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B3B76E198; Wed, 25 Aug 2021 10:06:16 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 651B36E17E for ; Wed, 25 Aug 2021 10:05:40 +0000 (UTC) X-UUID: 9198d289dc1d46dda1ac29b2d402d2ca-20210825 X-UUID: 9198d289dc1d46dda1ac29b2d402d2ca-20210825 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 803453213; Wed, 25 Aug 2021 18:05:36 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 Aug 2021 18:05:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 25 Aug 2021 18:05:35 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v4 11/17] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Wed, 25 Aug 2021 18:05:25 +0800 Message-ID: <20210825100531.5653-12-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210825100531.5653-1-nancy.lin@mediatek.com> References: <20210825100531.5653-1-nancy.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements, so change it to support multi-bit control. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++------------- 1 file changed, 162 insertions(+), 108 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c177156ee2fa..588e378d1855 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -29,101 +29,130 @@ #define INT_MUTEX BIT(1) -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8183_MUTEX_MOD_DISP_RDMA0 0 -#define MT8183_MUTEX_MOD_DISP_RDMA1 1 -#define MT8183_MUTEX_MOD_DISP_OVL0 9 -#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 -#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 -#define MT8183_MUTEX_MOD_DISP_WDMA0 12 -#define MT8183_MUTEX_MOD_DISP_COLOR0 13 -#define MT8183_MUTEX_MOD_DISP_CCORR0 14 -#define MT8183_MUTEX_MOD_DISP_AAL0 15 -#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 -#define MT8183_MUTEX_MOD_DISP_DITHER0 17 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT8195_MUTEX_MOD_DISP_OVL0 0 -#define MT8195_MUTEX_MOD_DISP_WDMA0 1 -#define MT8195_MUTEX_MOD_DISP_RDMA0 2 -#define MT8195_MUTEX_MOD_DISP_COLOR0 3 -#define MT8195_MUTEX_MOD_DISP_CCORR0 4 -#define MT8195_MUTEX_MOD_DISP_AAL0 5 -#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 -#define MT8195_MUTEX_MOD_DISP_DITHER0 7 -#define MT8195_MUTEX_MOD_DISP_DSI0 8 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 -#define MT8195_MUTEX_MOD_DISP_OVL1 10 -#define MT8195_MUTEX_MOD_DISP_WDMA1 11 -#define MT8195_MUTEX_MOD_DISP_RDMA1 12 -#define MT8195_MUTEX_MOD_DISP_COLOR1 13 -#define MT8195_MUTEX_MOD_DISP_CCORR1 14 -#define MT8195_MUTEX_MOD_DISP_AAL1 15 -#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 -#define MT8195_MUTEX_MOD_DISP_DITHER1 17 -#define MT8195_MUTEX_MOD_DISP_DSI1 18 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 -#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 -#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 -#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 -#define MT8195_MUTEX_MOD_DISP_PWM0 27 -#define MT8195_MUTEX_MOD_DISP_PWM1 28 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 +#define MT8167_MUTEX_MOD_DISP_PWM BIT(1) +#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6) +#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7) +#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8) +#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9) +#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10) +#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11) +#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12) +#define MT8167_MUTEX_MOD_DISP_AAL BIT(13) +#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14) +#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15) +#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16) + +#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0) +#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1) +#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9) +#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10) +#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11) +#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12) +#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13) +#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14) +#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15) +#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16) +#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17) + +#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) +#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) +#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT8173_MUTEX_MOD_DISP_OD BIT(25) + +#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0) +#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1) +#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2) +#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3) +#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4) +#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5) +#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6) +#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7) +#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9) +#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10) +#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11) +#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13) +#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14) +#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15) +#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16) +#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17) +#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19) +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20) +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23) +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26) +#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) +#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) + +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20) +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25) +#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33) +#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34) + +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT2712_MUTEX_SOF_SINGLE_MODE 0 #define MT2712_MUTEX_SOF_DSI0 1 @@ -174,7 +203,7 @@ enum mtk_mutex_sof_id { }; struct mtk_mutex_data { - const unsigned int *mutex_mod; + const unsigned long *mutex_mod; const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; @@ -189,7 +218,7 @@ struct mtk_mutex_ctx { const struct mtk_mutex_data *data; }; -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, @@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, @@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, @@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, @@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, @@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, @@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << mtx->data->mutex_mod[id]; + reg |= mtx->data->mutex_mod[id]; writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << (mtx->data->mutex_mod[id] - 32); + reg |= (mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } return; @@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << mtx->data->mutex_mod[id]); + reg &= ~(mtx->data->mutex_mod[id]); writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + reg &= ~(mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } break; -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCFAAC4320A for ; Wed, 25 Aug 2021 10:25:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABDBA6120A for ; Wed, 25 Aug 2021 10:25:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org ABDBA6120A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fHkzRPoOnbokdahULA4NCiHEpnmsn4rZawVLB7BupOM=; b=XmdjXQFaMyDfev WRzbpElezdf+WGJKNRthfM4uR7HYgrX6SyluH3mgPfyNPCVWcSJCaHqKNPBx2/mroKDBEEujPyZPb J2w7UjhovNlJXzSq8F7Hb2FzHR2MegR6hqmbRK8Ov5iQLTaD+TqpF72PWwMtpwUQvwKWEFnttPXtm dB7EwRqPO5hGfq6kSZ+fkvSnpzV6kV2ecjG7nl/9D1yyXSxNijb84GvTblAmLg6NFt4Uh1sD7twjS +Ymt0ZLV896u9tgK9NFq1/edoN8q7zBGCGwmAoHZEKg5KAQWsVaCzwN9X0aL2h5nX5E3U1U7rLOt9 k2rlfaapF2pc0cN19Vmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIq5W-006Sv1-5Y; Wed, 25 Aug 2021 10:24:54 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIpuq-006NXw-K8; Wed, 25 Aug 2021 10:13:55 +0000 X-UUID: a595f0a586a04c90bb53ece8f96a5a6a-20210825 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Dqs8scmQVahYrsNL7yT7wJaai6xyOp9T3oRAcN+jXh4=; b=HFxE67RoWocCdXGnP+aAJZy6NqNfzsfaz7yKHyZq8CvY83vGj4LQoGK1TjVLvgBQ9G7ZpVN3MKbep6g6733pnqBumBEKRZpkF1xSBq9iAe0MEecVgNk+Ur/xns/fZXNnyDiuuhPxVxCS4+0MksdbGmyZ1E85TdFEMtgnsTihrRQ=; X-UUID: a595f0a586a04c90bb53ece8f96a5a6a-20210825 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 731994106; Wed, 25 Aug 2021 03:13:27 -0700 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 Aug 2021 03:05:36 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 Aug 2021 18:05:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 25 Aug 2021 18:05:35 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v4 11/17] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Wed, 25 Aug 2021 18:05:25 +0800 Message-ID: <20210825100531.5653-12-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210825100531.5653-1-nancy.lin@mediatek.com> References: <20210825100531.5653-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210825_031352_773810_28775C0F X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements, so change it to support multi-bit control. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++------------- 1 file changed, 162 insertions(+), 108 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c177156ee2fa..588e378d1855 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -29,101 +29,130 @@ #define INT_MUTEX BIT(1) -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8183_MUTEX_MOD_DISP_RDMA0 0 -#define MT8183_MUTEX_MOD_DISP_RDMA1 1 -#define MT8183_MUTEX_MOD_DISP_OVL0 9 -#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 -#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 -#define MT8183_MUTEX_MOD_DISP_WDMA0 12 -#define MT8183_MUTEX_MOD_DISP_COLOR0 13 -#define MT8183_MUTEX_MOD_DISP_CCORR0 14 -#define MT8183_MUTEX_MOD_DISP_AAL0 15 -#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 -#define MT8183_MUTEX_MOD_DISP_DITHER0 17 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT8195_MUTEX_MOD_DISP_OVL0 0 -#define MT8195_MUTEX_MOD_DISP_WDMA0 1 -#define MT8195_MUTEX_MOD_DISP_RDMA0 2 -#define MT8195_MUTEX_MOD_DISP_COLOR0 3 -#define MT8195_MUTEX_MOD_DISP_CCORR0 4 -#define MT8195_MUTEX_MOD_DISP_AAL0 5 -#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 -#define MT8195_MUTEX_MOD_DISP_DITHER0 7 -#define MT8195_MUTEX_MOD_DISP_DSI0 8 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 -#define MT8195_MUTEX_MOD_DISP_OVL1 10 -#define MT8195_MUTEX_MOD_DISP_WDMA1 11 -#define MT8195_MUTEX_MOD_DISP_RDMA1 12 -#define MT8195_MUTEX_MOD_DISP_COLOR1 13 -#define MT8195_MUTEX_MOD_DISP_CCORR1 14 -#define MT8195_MUTEX_MOD_DISP_AAL1 15 -#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 -#define MT8195_MUTEX_MOD_DISP_DITHER1 17 -#define MT8195_MUTEX_MOD_DISP_DSI1 18 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 -#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 -#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 -#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 -#define MT8195_MUTEX_MOD_DISP_PWM0 27 -#define MT8195_MUTEX_MOD_DISP_PWM1 28 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 +#define MT8167_MUTEX_MOD_DISP_PWM BIT(1) +#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6) +#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7) +#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8) +#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9) +#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10) +#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11) +#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12) +#define MT8167_MUTEX_MOD_DISP_AAL BIT(13) +#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14) +#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15) +#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16) + +#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0) +#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1) +#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9) +#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10) +#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11) +#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12) +#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13) +#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14) +#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15) +#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16) +#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17) + +#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) +#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) +#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT8173_MUTEX_MOD_DISP_OD BIT(25) + +#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0) +#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1) +#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2) +#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3) +#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4) +#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5) +#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6) +#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7) +#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9) +#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10) +#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11) +#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13) +#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14) +#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15) +#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16) +#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17) +#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19) +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20) +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23) +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26) +#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) +#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) + +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20) +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25) +#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33) +#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34) + +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT2712_MUTEX_SOF_SINGLE_MODE 0 #define MT2712_MUTEX_SOF_DSI0 1 @@ -174,7 +203,7 @@ enum mtk_mutex_sof_id { }; struct mtk_mutex_data { - const unsigned int *mutex_mod; + const unsigned long *mutex_mod; const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; @@ -189,7 +218,7 @@ struct mtk_mutex_ctx { const struct mtk_mutex_data *data; }; -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, @@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, @@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, @@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, @@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, @@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, @@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << mtx->data->mutex_mod[id]; + reg |= mtx->data->mutex_mod[id]; writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << (mtx->data->mutex_mod[id] - 32); + reg |= (mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } return; @@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << mtx->data->mutex_mod[id]); + reg &= ~(mtx->data->mutex_mod[id]); writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + reg &= ~(mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } break; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CFDC4338F for ; Wed, 25 Aug 2021 10:27:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 558DE611EF for ; Wed, 25 Aug 2021 10:27:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 558DE611EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z1RRbd/tp/ateQc1B1lrS+1iDRWxlseb/7kA4kkRzNI=; b=lSSVwzAVLNvRZK mBJu1lN4rtzDN2h0NpJ+WBox5D/fd++OBL5Rq2v7cWHtPHkI34oVVfPBrPe/HINyqA5y+Gdckxjs2 KrYTGL21QQgX1bQILjD82lIjxWt0HqNkY40r3LpsyOlL5331CpQSyqXqelTxff7xRhudOEwy1DSmc DmZsQGuiLpFNv4r30E9p6YqnBnnmLrJ1/NTtQTZ/ZDJ2RI7FYUmfSgPYVGShwysY9UnSOm/ieBsME 8oWYyDgltkYwYwIZKjhkwOLNDIBLoaiUPotPUJkmFMgeDvMnVli8hV1rkp3ortj6id4KWMinpnL+b KUm4b8BO6XtMHbZU/mPQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIq4n-006SXx-Ux; Wed, 25 Aug 2021 10:24:10 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIpuq-006NXw-K8; Wed, 25 Aug 2021 10:13:55 +0000 X-UUID: a595f0a586a04c90bb53ece8f96a5a6a-20210825 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Dqs8scmQVahYrsNL7yT7wJaai6xyOp9T3oRAcN+jXh4=; b=HFxE67RoWocCdXGnP+aAJZy6NqNfzsfaz7yKHyZq8CvY83vGj4LQoGK1TjVLvgBQ9G7ZpVN3MKbep6g6733pnqBumBEKRZpkF1xSBq9iAe0MEecVgNk+Ur/xns/fZXNnyDiuuhPxVxCS4+0MksdbGmyZ1E85TdFEMtgnsTihrRQ=; X-UUID: a595f0a586a04c90bb53ece8f96a5a6a-20210825 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 731994106; Wed, 25 Aug 2021 03:13:27 -0700 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 Aug 2021 03:05:36 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 Aug 2021 18:05:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 25 Aug 2021 18:05:35 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v4 11/17] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Wed, 25 Aug 2021 18:05:25 +0800 Message-ID: <20210825100531.5653-12-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210825100531.5653-1-nancy.lin@mediatek.com> References: <20210825100531.5653-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210825_031352_773810_28775C0F X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements, so change it to support multi-bit control. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++------------- 1 file changed, 162 insertions(+), 108 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c177156ee2fa..588e378d1855 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -29,101 +29,130 @@ #define INT_MUTEX BIT(1) -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8183_MUTEX_MOD_DISP_RDMA0 0 -#define MT8183_MUTEX_MOD_DISP_RDMA1 1 -#define MT8183_MUTEX_MOD_DISP_OVL0 9 -#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 -#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 -#define MT8183_MUTEX_MOD_DISP_WDMA0 12 -#define MT8183_MUTEX_MOD_DISP_COLOR0 13 -#define MT8183_MUTEX_MOD_DISP_CCORR0 14 -#define MT8183_MUTEX_MOD_DISP_AAL0 15 -#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 -#define MT8183_MUTEX_MOD_DISP_DITHER0 17 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT8195_MUTEX_MOD_DISP_OVL0 0 -#define MT8195_MUTEX_MOD_DISP_WDMA0 1 -#define MT8195_MUTEX_MOD_DISP_RDMA0 2 -#define MT8195_MUTEX_MOD_DISP_COLOR0 3 -#define MT8195_MUTEX_MOD_DISP_CCORR0 4 -#define MT8195_MUTEX_MOD_DISP_AAL0 5 -#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 -#define MT8195_MUTEX_MOD_DISP_DITHER0 7 -#define MT8195_MUTEX_MOD_DISP_DSI0 8 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 -#define MT8195_MUTEX_MOD_DISP_OVL1 10 -#define MT8195_MUTEX_MOD_DISP_WDMA1 11 -#define MT8195_MUTEX_MOD_DISP_RDMA1 12 -#define MT8195_MUTEX_MOD_DISP_COLOR1 13 -#define MT8195_MUTEX_MOD_DISP_CCORR1 14 -#define MT8195_MUTEX_MOD_DISP_AAL1 15 -#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 -#define MT8195_MUTEX_MOD_DISP_DITHER1 17 -#define MT8195_MUTEX_MOD_DISP_DSI1 18 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 -#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 -#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 -#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 -#define MT8195_MUTEX_MOD_DISP_PWM0 27 -#define MT8195_MUTEX_MOD_DISP_PWM1 28 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 +#define MT8167_MUTEX_MOD_DISP_PWM BIT(1) +#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6) +#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7) +#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8) +#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9) +#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10) +#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11) +#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12) +#define MT8167_MUTEX_MOD_DISP_AAL BIT(13) +#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14) +#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15) +#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16) + +#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0) +#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1) +#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9) +#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10) +#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11) +#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12) +#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13) +#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14) +#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15) +#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16) +#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17) + +#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) +#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) +#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT8173_MUTEX_MOD_DISP_OD BIT(25) + +#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0) +#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1) +#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2) +#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3) +#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4) +#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5) +#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6) +#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7) +#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9) +#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10) +#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11) +#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13) +#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14) +#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15) +#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16) +#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17) +#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19) +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20) +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23) +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26) +#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) +#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) + +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20) +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25) +#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33) +#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34) + +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT2712_MUTEX_SOF_SINGLE_MODE 0 #define MT2712_MUTEX_SOF_DSI0 1 @@ -174,7 +203,7 @@ enum mtk_mutex_sof_id { }; struct mtk_mutex_data { - const unsigned int *mutex_mod; + const unsigned long *mutex_mod; const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; @@ -189,7 +218,7 @@ struct mtk_mutex_ctx { const struct mtk_mutex_data *data; }; -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, @@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, @@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, @@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, @@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, @@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, @@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << mtx->data->mutex_mod[id]; + reg |= mtx->data->mutex_mod[id]; writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << (mtx->data->mutex_mod[id] - 32); + reg |= (mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } return; @@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << mtx->data->mutex_mod[id]); + reg &= ~(mtx->data->mutex_mod[id]); writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + reg &= ~(mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } break; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel