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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
Date: Wed, 25 Aug 2021 11:34:53 +0100	[thread overview]
Message-ID: <20210825103534.6936-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org>

In the MVE shift-and-insert insns, we special case VSLI by 0
and VSRI by <dt>. VSRI by <dt> means "don't update the destination",
which is what we've implemented. However VSLI by 0 is "set
destination to the input", so we don't want to use the same
special-casing that we do for VSRI by <dt>.

Since the generic logic gives the right answer for a shift
by 0, just use that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/mve_helper.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index db5d6220854..f14fa914b68 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1279,11 +1279,12 @@ DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
         uint16_t mask;                                                  \
         uint64_t shiftmask;                                             \
         unsigned e;                                                     \
-        if (shift == 0 || shift == ESIZE * 8) {                         \
+        if (shift == ESIZE * 8) {                                       \
             /*                                                          \
-             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
-             * The generic logic would give the right answer for 0 but  \
-             * fails for <dt>.                                          \
+             * Only VSRI can shift by <dt>; it should mean "don't       \
+             * update the destination". The generic logic can't handle  \
+             * this because it would try to shift by an out-of-range    \
+             * amount, so special case it here.                         \
              */                                                         \
             goto done;                                                  \
         }                                                               \
-- 
2.20.1



  parent reply	other threads:[~2021-08-25 10:38 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 10:34 [PULL 00/44] target-arm queue Peter Maydell
2021-08-25 10:34 ` [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL Peter Maydell
2021-08-25 10:34 ` [PULL 02/44] target/arm: Print MVE VPR in CPU dumps Peter Maydell
2021-08-25 10:34 ` Peter Maydell [this message]
2021-08-25 10:34 ` [PULL 04/44] target/arm: Fix signed VADDV Peter Maydell
2021-08-25 10:34 ` [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations Peter Maydell
2021-08-25 10:34 ` [PULL 06/44] target/arm: Fix 48-bit saturating shifts Peter Maydell
2021-08-25 10:34 ` [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts Peter Maydell
2021-08-25 10:34 ` [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0 Peter Maydell
2021-08-25 10:34 ` [PULL 09/44] target/arm: Factor out mve_eci_mask() Peter Maydell
2021-08-25 10:35 ` [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero Peter Maydell
2021-08-25 10:35 ` [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements Peter Maydell
2021-08-25 10:35 ` [PULL 12/44] target/arm: Implement MVE VMULL (polynomial) Peter Maydell
2021-08-25 10:35 ` [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns Peter Maydell
2021-08-25 10:35 ` [PULL 14/44] target/arm: Factor out gen_vpst() Peter Maydell
2021-08-25 10:35 ` [PULL 15/44] target/arm: Implement MVE integer vector comparisons Peter Maydell
2021-08-25 10:35 ` [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons Peter Maydell
2021-08-25 10:35 ` [PULL 17/44] target/arm: Implement MVE VPSEL Peter Maydell
2021-08-25 10:35 ` [PULL 18/44] target/arm: Implement MVE VMLAS Peter Maydell
2021-08-25 10:35 ` [PULL 19/44] target/arm: Implement MVE shift-by-scalar Peter Maydell
2021-08-25 10:35 ` [PULL 20/44] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats Peter Maydell
2021-08-25 10:35 ` [PULL 21/44] target/arm: Implement MVE integer min/max across vector Peter Maydell
2021-08-25 10:35 ` [PULL 22/44] target/arm: Implement MVE VABAV Peter Maydell
2021-08-25 10:35 ` [PULL 23/44] target/arm: Implement MVE narrowing moves Peter Maydell
2021-08-25 10:35 ` [PULL 24/44] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn Peter Maydell
2021-08-25 10:35 ` [PULL 25/44] target/arm: Implement MVE VMLADAV and VMLSLDAV Peter Maydell
2021-08-25 10:35 ` [PULL 26/44] target/arm: Implement MVE VMLA Peter Maydell
2021-08-25 10:35 ` [PULL 27/44] target/arm: Implement MVE saturating doubling multiply accumulates Peter Maydell
2021-08-25 10:35 ` [PULL 28/44] target/arm: Implement MVE VQABS, VQNEG Peter Maydell
2021-08-25 10:35 ` [PULL 29/44] target/arm: Implement MVE VMAXA, VMINA Peter Maydell
2021-08-25 10:35 ` [PULL 30/44] target/arm: Implement MVE VMOV to/from 2 general-purpose registers Peter Maydell
2021-08-25 10:35 ` [PULL 31/44] target/arm: Implement MVE VPNOT Peter Maydell
2021-08-25 10:35 ` [PULL 32/44] target/arm: Implement MVE VCTP Peter Maydell
2021-08-25 10:35 ` [PULL 33/44] target/arm: Implement MVE scatter-gather insns Peter Maydell
2021-08-25 10:35 ` [PULL 34/44] target/arm: Implement MVE scatter-gather immediate forms Peter Maydell
2021-08-25 10:35 ` [PULL 35/44] target/arm: Implement MVE interleaving loads/stores Peter Maydell
2021-08-25 10:35 ` [PULL 36/44] target/arm: Re-indent sdiv and udiv helpers Peter Maydell
2021-08-25 10:35 ` [PULL 37/44] target/arm: Implement M-profile trapping on division by zero Peter Maydell
2021-08-25 10:35 ` [PULL 38/44] target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() Peter Maydell
2021-08-25 10:35 ` [PULL 39/44] hw/char/pl011: add support for sending break Peter Maydell
2021-08-25 10:35 ` [PULL 40/44] fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices Peter Maydell
2021-08-25 10:35 ` [PULL 41/44] hw/dma/pl330: Add memory region to replace default Peter Maydell
2021-08-25 10:35 ` [PULL 42/44] sbsa-ref: Rename SBSA_GWDT enum value Peter Maydell
2021-08-25 10:35 ` [PULL 43/44] fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices Peter Maydell
2021-08-25 10:35 ` [PULL 44/44] docs: Document how to use gdb with unix sockets Peter Maydell
2021-08-25 17:49 ` [PULL 00/44] target-arm queue Peter Maydell

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