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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id c7sm5050577wmq.13.2021.08.25.06.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 06:02:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 00/28] MIPS patches for 2021-08-25 Date: Wed, 25 Aug 2021 15:01:43 +0200 Message-Id: <20210825130211.1542338-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef= :=0D =0D Open 6.2 development tree (2021-08-25 10:25:12 +0100)=0D =0D are available in the Git repository at:=0D =0D https://github.com/philmd/qemu.git tags/mips-20210825=0D =0D for you to fetch changes up to bf78469cc8ddb117b6db4a353e59fb4664a96de4:=0D =0D target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() (2021-0= 8-25 13:02:14 +0200)=0D =0D ----------------------------------------------------------------=0D MIPS patches queue=0D =0D - minor simplifications in PREF / JR opcodes=0D - merge 32-bit/64-bit Release6 decodetree definitions=0D - converted NEC Vr54xx extension opcodes to decodetree=0D - housekeeping in gen_helper() macros=0D - replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()=0D - allow Loongson 3A1000 to use up to 48-bit VAddr=0D =0D ----------------------------------------------------------------=0D =0D One false positive because whole target/mips/ is coverd in MAINTAINERS:=0D =0D WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?=0D =0D MIPS TCG CPUs=0D F: target/mips/=0D =0D Two style warnings:=0D =0D WARNING: line over 80 characters=0D =0D Preexisting failure (fixes from John Snow available on the list):=0D =0D ERROR: py36: commands failed=0D ERROR: py37: commands failed=0D ERROR: py38: commands failed=0D ERROR: py39: commands failed=0D ERROR: py310: commands failed=0D make: *** [Makefile:93: check-tox] Error 1=0D =0D Philippe Mathieu-Daud=C3=A9 (28):=0D target/mips: Remove JR opcode unused arguments=0D target/mips: Simplify PREF opcode=0D target/mips: Decode vendor extensions before MIPS ISAs=0D target/mips: Merge 32-bit/64-bit Release6 decodetree definitions=0D target/mips: Rename 'rtype' as 'r'=0D target/mips: Introduce generic TRANS() macro for decodetree helpers=0D target/mips: Extract NEC Vr54xx helper definitions=0D target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c=0D target/mips: Introduce decodetree structure for NEC Vr54xx extension=0D target/mips: Convert Vr54xx MACC* opcodes to decodetree=0D target/mips: Convert Vr54xx MUL* opcodes to decodetree=0D target/mips: Convert Vr54xx MSA* opcodes to decodetree=0D target/mips: Document Loongson-3A CPU definitions=0D target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr=0D target/mips: Remove duplicated check_cp1_enabled() calls in Loongson=0D EXT=0D target/mips: Remove gen_helper_0e3i()=0D target/mips: Remove gen_helper_1e2i()=0D target/mips: Use tcg_constant_i32() in gen_helper_0e2i()=0D target/mips: Simplify gen_helper() macros by using tcg_constant_i32()=0D target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros=0D target/mips: Inline gen_helper_0e0i()=0D target/mips: Use tcg_constant_i32() in generate_exception_err()=0D target/mips: Define gen_helper() macros in translate.h=0D target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st=0D helpers=0D target/mips: Replace GET_LMASK() macro by get_lmask(32) function=0D target/mips: Replace GET_LMASK64() macro by get_lmask(64) function=0D target/mips: Store CP0_Config0 in DisasContext=0D target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()=0D =0D target/mips/helper.h | 18 +-=0D target/mips/tcg/translate.h | 27 ++=0D target/mips/tcg/vr54xx_helper.h.inc | 24 ++=0D target/mips/tcg/mips64r6.decode | 27 --=0D target/mips/tcg/msa.decode | 4 +-=0D .../mips/tcg/{mips32r6.decode =3D> rel6.decode} | 17 +-=0D target/mips/tcg/tx79.decode | 14 +-=0D target/mips/tcg/vr54xx.decode | 27 ++=0D target/mips/tcg/ldst_helper.c | 122 +++++----=0D target/mips/tcg/msa_translate.c | 4 +-=0D target/mips/tcg/op_helper.c | 118 --------=0D target/mips/tcg/rel6_translate.c | 20 +-=0D target/mips/tcg/translate.c | 258 ++++--------------=0D target/mips/tcg/tx79_translate.c | 62 ++---=0D target/mips/tcg/vr54xx_helper.c | 142 ++++++++++=0D target/mips/tcg/vr54xx_translate.c | 72 +++++=0D target/mips/cpu-defs.c.inc | 6 +-=0D target/mips/tcg/nanomips_translate.c.inc | 20 +-=0D target/mips/tcg/meson.build | 6 +-=0D 19 files changed, 502 insertions(+), 486 deletions(-)=0D create mode 100644 target/mips/tcg/vr54xx_helper.h.inc=0D delete mode 100644 target/mips/tcg/mips64r6.decode=0D rename target/mips/tcg/{mips32r6.decode =3D> rel6.decode} (64%)=0D create mode 100644 target/mips/tcg/vr54xx.decode=0D create mode 100644 target/mips/tcg/vr54xx_helper.c=0D create mode 100644 target/mips/tcg/vr54xx_translate.c=0D =0D -- =0D 2.31.1=0D =0D