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Wed, 25 Aug 2021 11:37:36 -0400 (EDT) Date: Wed, 25 Aug 2021 17:37:34 +0200 From: Maxime Ripard To: Jernej =?utf-8?Q?=C5=A0krabec?= Cc: Icenowy Zheng , Rob Herring , Chen-Yu Tsai , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Message-ID: <20210825153734.3cwlufietc63ma3m@gilmour> References: <20210802062212.73220-1-icenowy@sipeed.com> <5432230.1UTMcGJKg4@jernej-laptop> <20210825145027.ixc7wnh3x5w6wzny@gilmour> <3221818.pD4rYpbbZ1@jernej-laptop> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ujvj4sh6srxe5rru" Content-Disposition: inline In-Reply-To: <3221818.pD4rYpbbZ1@jernej-laptop> --ujvj4sh6srxe5rru Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Aug 25, 2021 at 05:03:30PM +0200, Jernej =C5=A0krabec wrote: > Dne sreda, 25. avgust 2021 ob 16:50:27 CEST je Maxime Ripard napisal(a): > > Hi, > >=20 > > On Fri, Aug 20, 2021 at 06:34:38AM +0200, Jernej =C5=A0krabec wrote: > > > > > +static void __init sun50i_r329_r_ccu_setup(struct device_node *n= ode) > > > > > +{ > > > > > + void __iomem *reg; > > > > > + u32 val; > > > > > + int i; > > > > > + > > > > > + reg =3D of_io_request_and_map(node, 0, of_node_full_name(node)); > > > > > + if (IS_ERR(reg)) { > > > > > + pr_err("%pOF: Could not map clock registers\n", node); > > > > > + return; > > > > > + } > > > > > + > > > > > + /* Enable the lock bits and the output enable bits on all PLLs = */ > > > > > + for (i =3D 0; i < ARRAY_SIZE(pll_regs); i++) { > > > > > + val =3D readl(reg + pll_regs[i]); > > > > > + val |=3D BIT(29) | BIT(27); > > > > > + writel(val, reg + pll_regs[i]); > > > > > + } > > > > > + > > > > > + /* > > > > > + * Force the I/O dividers of PLL-AUDIO1 to reset default value > > > > > + * > > > > > + * See the comment before pll-audio1 definition for the reason. > > > > > + */ > > > > > + > > > > > + val =3D readl(reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > > + val &=3D ~BIT(1); > > > > > + val |=3D BIT(0); > > > > > + writel(val, reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > > + > > > > > + i =3D sunxi_ccu_probe(node, reg, &sun50i_r329_r_ccu_desc); > > > > > + if (i) > > > > > + pr_err("%pOF: probing clocks fails: %d\n", node, i); > > > > > +} > > > > > + > > > > > +CLK_OF_DECLARE(sun50i_r329_r_ccu, "allwinner,sun50i-r329-r-ccu", > > > > > + sun50i_r329_r_ccu_setup); > > > >=20 > > > > Please make this a platform driver. There is no particular reason w= hy it > > > > needs to be an early OF clock provider. > > >=20 > > > Why? It's good to have it as early clock provider. It has no dependen= cies > > > and other drivers that depends on it, like IR, can be deferred, if th= is > > > is loaded later. > >=20 > > No, Samuel is right, we should make them regular drivers as much as we > > can. > >=20 > > The reason we had CLK_OF_DECLARE in the first place is that timers > > usually have a parent clock, and you need the timers before the device > > model is set up. > >=20 > > Fortunately for us, since the A20, the architected timers don't require > > a parent clock from us, and we can thus boot up fine. >=20 > There are other timers. A lot of SoCs, newer than A20 (like H6), have Hig= h=20 > Speed Timer, which requires parent clock to be enabled. We just choose no= t to=20 > add node for it to DT, even if it's there and driver already exists. Yeah, I know. The thing is, we just need one timer in order to boot to the point where the DM is there. We can totally have a timer driver probing just like any other driver, through the DM, later on. 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Wed, 25 Aug 2021 11:37:36 -0400 (EDT) Date: Wed, 25 Aug 2021 17:37:34 +0200 From: Maxime Ripard To: Jernej =?utf-8?Q?=C5=A0krabec?= Cc: Icenowy Zheng , Rob Herring , Chen-Yu Tsai , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Message-ID: <20210825153734.3cwlufietc63ma3m@gilmour> References: <20210802062212.73220-1-icenowy@sipeed.com> <5432230.1UTMcGJKg4@jernej-laptop> <20210825145027.ixc7wnh3x5w6wzny@gilmour> <3221818.pD4rYpbbZ1@jernej-laptop> MIME-Version: 1.0 In-Reply-To: <3221818.pD4rYpbbZ1@jernej-laptop> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210825_083740_831120_44C0F00F X-CRM114-Status: GOOD ( 36.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5369373869225896582==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============5369373869225896582== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ujvj4sh6srxe5rru" Content-Disposition: inline --ujvj4sh6srxe5rru Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Aug 25, 2021 at 05:03:30PM +0200, Jernej =C5=A0krabec wrote: > Dne sreda, 25. avgust 2021 ob 16:50:27 CEST je Maxime Ripard napisal(a): > > Hi, > >=20 > > On Fri, Aug 20, 2021 at 06:34:38AM +0200, Jernej =C5=A0krabec wrote: > > > > > +static void __init sun50i_r329_r_ccu_setup(struct device_node *n= ode) > > > > > +{ > > > > > + void __iomem *reg; > > > > > + u32 val; > > > > > + int i; > > > > > + > > > > > + reg =3D of_io_request_and_map(node, 0, of_node_full_name(node)); > > > > > + if (IS_ERR(reg)) { > > > > > + pr_err("%pOF: Could not map clock registers\n", node); > > > > > + return; > > > > > + } > > > > > + > > > > > + /* Enable the lock bits and the output enable bits on all PLLs = */ > > > > > + for (i =3D 0; i < ARRAY_SIZE(pll_regs); i++) { > > > > > + val =3D readl(reg + pll_regs[i]); > > > > > + val |=3D BIT(29) | BIT(27); > > > > > + writel(val, reg + pll_regs[i]); > > > > > + } > > > > > + > > > > > + /* > > > > > + * Force the I/O dividers of PLL-AUDIO1 to reset default value > > > > > + * > > > > > + * See the comment before pll-audio1 definition for the reason. > > > > > + */ > > > > > + > > > > > + val =3D readl(reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > > + val &=3D ~BIT(1); > > > > > + val |=3D BIT(0); > > > > > + writel(val, reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > > + > > > > > + i =3D sunxi_ccu_probe(node, reg, &sun50i_r329_r_ccu_desc); > > > > > + if (i) > > > > > + pr_err("%pOF: probing clocks fails: %d\n", node, i); > > > > > +} > > > > > + > > > > > +CLK_OF_DECLARE(sun50i_r329_r_ccu, "allwinner,sun50i-r329-r-ccu", > > > > > + sun50i_r329_r_ccu_setup); > > > >=20 > > > > Please make this a platform driver. There is no particular reason w= hy it > > > > needs to be an early OF clock provider. > > >=20 > > > Why? It's good to have it as early clock provider. It has no dependen= cies > > > and other drivers that depends on it, like IR, can be deferred, if th= is > > > is loaded later. > >=20 > > No, Samuel is right, we should make them regular drivers as much as we > > can. > >=20 > > The reason we had CLK_OF_DECLARE in the first place is that timers > > usually have a parent clock, and you need the timers before the device > > model is set up. > >=20 > > Fortunately for us, since the A20, the architected timers don't require > > a parent clock from us, and we can thus boot up fine. >=20 > There are other timers. A lot of SoCs, newer than A20 (like H6), have Hig= h=20 > Speed Timer, which requires parent clock to be enabled. We just choose no= t to=20 > add node for it to DT, even if it's there and driver already exists. Yeah, I know. The thing is, we just need one timer in order to boot to the point where the DM is there. We can totally have a timer driver probing just like any other driver, through the DM, later on. Maxime --ujvj4sh6srxe5rru Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYSZjvgAKCRDj7w1vZxhR xX+TAP0WGHG2s4yHamp+fjkYZIyN3blRmTbmA8bbbYAZDDpWPAD8D3b0gM0/5VYF c22yVcU2bytiqTiat5LMPSwOhQzTCQo= =zJhK -----END PGP SIGNATURE----- --ujvj4sh6srxe5rru-- --===============5369373869225896582== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============5369373869225896582==--